DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028786 A1; hereinafter “Huang”) in view of Wang et al. (US 2021/0335709 A1; hereinafter “Wang”).
Regarding claim 11, referring to Figs. 1, 20, 21B, and related text, Huang teaches an integrated circuit device, comprising: a substrate having a first surface and a second surface (256 having a top surface and a bottom surface as shown in Fig. 21B), the first and second surfaces being opposite one another (paragraph 34); a fin-type active region (206) extending in a first horizontal direction (a x-direction) on the first surface of the substrate (paragraph 16); a plurality of gate lines (250) extending in a second horizontal direction (a y-direction) crossing the first horizontal direction on the fin-type active region and spaced apart from each other in the first horizontal direction (paragraph 31); a back side contact (262) between the plurality of gate lines and overlapping the fin-type active region in the second horizontal direction (paragraph 38); a source/drain area (240S) on the back side contact (paragraph 27); and a back side conductive layer (270) extending in the first horizontal direction on the second surface of the substrate, wherein the back side contact is electrically connected to the source/drain area and the back side conductive layer (paragraph 40), the back side contact includes a first portion (a top portion of 262 having a width W1) protruding from the substrate and a second portion (a bottom portion of 262 having a width W2) that is coplanar with the first surface of the substrate (paragraph 38), and a width of the second portion in the second horizontal direction is greater than a width of the first portion in the second horizontal direction (Figs. 20 and 21B and paragraph 38).
Huang does not explicitly teach that the back side contact (262) is spaced apart from the substrate (256) (Fig. 21B and paragraphs 1 and 40). Wang teaches an integrated circuit device (a gate-all-around field-effect transistor), which is within the same field of endeavor that of Huang, comprising: a back side contact (a conductive material/structure of 158) formed in a substrate (152), wherein the back side contact is spaced apart from the substrate by a liner (not shown) as a diffusion barrier layer or an adhesion layer (Fig. 25 and paragraphs 13 and 92-95). Therefore, it would have been obvious to one of ordinary skill in the art to combine Huang teaching the back side contact and the substrate with Wang teaching the liner between the back side contact and the substrate in order to provide the liner as the diffusion barrier layer or the adhesion layer for the back side contact (the conductive material/structure of 158).
Regarding claim 12, Huang teaches wherein the back side conductive layer at least partially overlaps the back side contact in a vertical direction (a z-direction) (Fig. 21B).
Regarding claim 13, Huang teaches wherein the back side conductive layer is nonoverlapping, in a vertical direction, relative to the first portion of the back side contact (Figs. 20 and 21B, side portions of 270 is not overlapping relative to the top portion of 262 having the width W1).
Regarding claim 16, referring to Figs. 1, 20, 21B, and related text, Huang teaches an integrated circuit device, comprising: a substrate having a first surface and a second surface (256 having a top surface and a bottom surface as shown in Fig. 21B), the second surface being opposite the first surface (paragraph 34); a fin-type active region (206) extending in a first horizontal direction (a x-direction) on the first surface of the substrate (paragraph 16); a plurality of nanosheets (210B) on the fin-type active region and spaced apart from an upper surface of the fin-type active region (an upper surface of 206) in a vertical direction (a z-direction) (paragraphs 30-31); a gate line (250) surrounding the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction (a y-direction) crossing the first horizontal direction (paragraph 31); a back side contact (262) on one side of the gate line and overlapping the fin-type active region in the second horizontal direction (paragraph 38); a first source/drain area (240D) on the fin-type active region and contacting the plurality of nanosheets (paragraph 27); a second source/drain area (240S) on the back side contact and contacting the plurality of nanosheets (paragraph 27); and a back side conductive layer (270) extending in the first horizontal direction on the second surface of the substrate, wherein the back side contact is electrically connected to the second source/drain area and the back side conductive layer (paragraph 40), the back side contact includes a first portion (a top portion of 262 having a width W1) protruding from the substrate and a second portion (a bottom portion of 262 having a width W2) that is coplanar with the first surface of the substrate (paragraph 38), and a width of the second portion in the second horizontal direction is greater than a width of the first portion in the second horizontal direction (Figs. 20 and 21B and paragraph 38).
Huang does not explicitly teach that the back side contact (262) is spaced apart from the substrate (256) (Fig. 21B and paragraphs 1 and 40). Wang teaches an integrated circuit device (a gate-all-around field-effect transistor), which is within the same field of endeavor that of Huang, comprising: a back side contact (a conductive material/structure of 158) formed in a substrate (152), wherein the back side contact is spaced apart from the substrate by a liner (not shown) as a diffusion barrier layer or an adhesion layer (Fig. 25 and paragraphs 13 and 92-95). Therefore, it would have been obvious to one of ordinary skill in the art to combine Huang teaching the back side contact and the substrate with Wang teaching the liner between the back side contact and the substrate in order to provide the liner as the diffusion barrier layer or the adhesion layer for the back side contact (the conductive material/structure of 158).
Regarding claim 17, Huang teaches wherein the back side conductive layer at least partially overlaps the back side contact in the vertical direction (Fig. 2B).
Regarding claim 18, Huang teaches wherein the back side conductive layer is nonoverlapping, in the vertical direction, relative to the first portion of the back side contact (Figs. 20 and 21B, side portions of 270 is not overlapping relative to the top portion of 262 having the width W1).
Claims 11-12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2024/0421207 A1; hereinafter “Yoo”) in view of Wang.
Regarding claim 11, referring to Figs. 1-2B and related text, Yoo teaches an integrated circuit device, comprising: a substrate having a first surface and a second surface (194 having a top surface and a bottom surface as shown in Fig. 2A), the first and second surfaces being opposite one another (paragraphs 24-28); a fin-type active region (194L) extending in a first horizontal direction (a x-direction) on the first surface of the substrate (paragraphs 24-28); a plurality of gate lines (160) extending in a second horizontal direction (a y-direction) crossing the first horizontal direction on the fin-type active region and spaced apart from each other in the first horizontal direction (paragraph 38); a back side contact (260) between the plurality of gate lines and overlapping the fin-type active region in the second horizontal direction (paragraph 56-58); a source/drain area (150) on the back side contact (paragraph 45); and a back side conductive layer (265) extending in the first horizontal direction on the second surface of the substrate, wherein the back side contact is electrically connected to the source/drain area and the back side conductive layer (paragraph 59), the back side contact includes a first portion protruding from the substrate and a second portion that is coplanar with the first surface of the substrate (Figs. 1-2A, an top portion of 260 protruding from the top surface of 194 and a bottom portion of 260 having a top surface coplanar with the top surface of 194), and a width of the second portion in the second horizontal direction is greater than a width of the first portion in the second horizontal direction (Figs. 1-2A and paragraph 58, a width of the bottom portion of 260 in the y-direction is greater than the width of the top portion of 260 since the bottom portion of 260 continuously/gradually increases in a direction approaching a bottom surface of 260).
You does not explicitly teach that the back side contact (260) is spaced apart from the substrate (194) (Fig. 2A and paragraphs 37 and 45). Wang teaches an integrated circuit device (a gate-all-around field-effect transistor) (paragraph 13), which is within the same field of endeavor that of You, comprising: a back side contact (a conductive material/structure of 158) formed in a substrate (152), wherein the back side contact is spaced apart from the substrate by a liner (not shown) as a diffusion barrier layer or an adhesion layer (Fig. 25 and paragraphs 13 and 92-95). Therefore, it would have been obvious to one of ordinary skill in the art to combine You teaching the back side contact and the substrate with Wang teaching the liner between the back side contact and the substrate in order to provide the liner as the diffusion barrier layer or the adhesion layer for the back side contact (the conductive material/structure of 158).
Regarding claim 12, Yoo teaches wherein the back side conductive layer at least partially overlaps the back side contact in a vertical direction (a z-direction) (Fig. 2A).
Regarding claim 16, referring to Figs. 1-2B and related text, Yoo teaches an integrated circuit device, comprising: a substrate having a first surface and a second surface (194 having a top surface and a bottom surface as shown in Fig. 2A), the second surface being opposite the first surface (paragraphs 24-28); a fin-type active region (194L) extending in a first horizontal direction (a x-direction) on the first surface of the substrate (paragraphs 24-28); a plurality of nanosheets (140) on the fin-type active region and spaced apart from an upper surface of the fin-type active region (an upper surface of 194L) in a vertical direction (a z-direction) (paragraph 35); a gate line (160) surrounding the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction (a y-direction) crossing the first horizontal direction (paragraph 38); a back side contact (260) on one side of the gate line and overlapping the fin-type active region in the second horizontal direction (paragraph 56-58); a first source/drain area (151 of 150) on the fin-type active region and contacting the plurality of nanosheets (paragraph 45); a second source/drain area (152 of 150) on the back side contact and contacting the plurality of nanosheets (paragraph 45); and a back side conductive layer (265) extending in the first horizontal direction on the second surface of the substrate, wherein the back side contact is electrically connected to the second source/drain area and the back side conductive layer (paragraphs 56-59), the back side contact includes a first portion protruding from the substrate and a second portion that is coplanar with the first surface of the substrate (Figs. 1-2A, an top portion of 260 protruding from the top surface of 194 and a bottom portion of 260 having a top surface coplanar with the top surface of 194), and a width of the second portion in the second horizontal direction is greater than a width of the first portion in the second horizontal direction (Figs. 1-2A and paragraph 58, a width of the bottom portion of 260 in the y-direction is greater than the width of the top portion of 260 since the bottom portion of 260 continuously/gradually increases in a direction approaching a bottom surface of 260).
You does not explicitly teach that the back side contact (260) is spaced apart from the substrate (194) (Fig. 2A and paragraphs 37 and 45). Wang teaches an integrated circuit device (a gate-all-around field-effect transistor) (paragraph 13), which is within the same field of endeavor that of You, comprising: a back side contact (a conductive material/structure of 158) formed in a substrate (152), wherein the back side contact is spaced apart from the substrate by a liner (not shown) as a diffusion barrier layer or an adhesion layer (Fig. 25 and paragraphs 13 and 92-95). Therefore, it would have been obvious to one of ordinary skill in the art to combine You teaching the back side contact and the substrate with Wang teaching the liner between the back side contact and the substrate in order to provide the liner as the diffusion barrier layer or the adhesion layer for the back side contact (the conductive material/structure of 158).
Regarding claim 17, Yoo teaches wherein the back side conductive layer at least partially overlaps the back side contact in the vertical direction (Fig. 2A).
Allowable Subject Matter
Claims 14-15 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-10 are allowable over the cited prior arts of record. See the Office Action dated 01/02/2026 for reasons indicating allowable subject matter.
Response to Arguments
Applicant’s arguments with respect to claims 11 and 16 have been considered but are moot in view of new grounds of rejection as set forth above in this Office Action.
Furthermore, Applicant’s additional argument that You does not qualify as the prior art since the effective filing date of the present application is 11/16/2022 based on the foreign priority, which is before the effectively filed date 06/19/2023 of You, is not found persuasive. Applicant is remined that the foreign priority date of the present Application (i.e., 11/16/2022) can be the effective filing date of the claimed invention if: the foreign application supports the claimed invention under 112(a), AND the Applicant has perfected the right of priority by providing: a certified copy of the priority application, and a translation of the priority application (if not in English). It is noted that the certified copy of the priority application is not in English (See Priority Document dated 11/30/2023).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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