Prosecution Insights
Last updated: April 19, 2026
Application No. 18/490,397

APPARATUS AND METHOD FOR PROVIDING PROCESSOR BASED POWER SHIFTING FOR PERIPHERAL DEVICES

Non-Final OA §103
Filed
Oct 19, 2023
Examiner
HUYNH, KIM NGOC
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Ati Technologies Ulc
OA Round
4 (Non-Final)
56%
Grant Probability
Moderate
4-5
OA Rounds
2y 8m
To Grant
57%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allow Rate
40 granted / 71 resolved
+1.3% vs TC avg
Minimal +1% lift
Without
With
+0.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
7 currently pending
Career history
78
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
50.5%
+10.5% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
19.3%
-20.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 71 resolved cases

Office Action

§103
DETAILED ACTION This communication is in response to RCE filed 2/27/26. Claims 1 – 20 are canceled, claims 21 - 40 are pending Claims 21,22, 24-26, 28-29, 31-33, 35-36 and 38-40 are rejected. Claims 23, 27, 30, 34, 37, and 40 are objected as containing allowable subject matter. Allowable Subject Matter Claims 23, 27, 30, 34, 37, and 40 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 02/27/26 have been fully considered but they are not persuasive. Regarding claim 28, Applicant argued that the power controller 150/450 equates to the processing in the rejection of claim 28. Examiner disagrees with this interpretation of the rejection. In the rejection of claim 28, the rejection points to the power delivery controllers for communicating to the port connecting to the peripheral devices and pointed to col. 7, ll. 20-22 which indicates processing core 101 as the claimed processor. The rest of the claim discussed the power balancing operation ( allocate and shifting power among the multiple devices connected to the system) as recited in claim 21 and is rejected based on the same rational. Please note that in claim 21, the first processor is mapped to processing cores 101 and the second processing core is the controller 150/450 as shown in Fig. 1-5, The rejection states that second processor coordinates with the processing device to implement the token based to manage distribution of power. In power management, the CPU and Controller work together to process data by executing instructions, managing data flow, and generating output, thus producing data. As such the processor of Meier operate to allocate and shifting data to the various devices within the computer system as claimed. In Meier, despite the naming convention, the power controller 150 is part of the ACPI to performs power management functions and thus working with the processor to issue allocate power information and shifting power among the processors and connected devices. Applicant’s own disclosure (par. 21) teaches the USB power shifting logic 120 is firmware stored in ROM and the power delivery controller 106 and executed by the processor and the PD power allocation is part of the firmware initialization process (par 27) in the same manner as disclosed by Meier. In modern computer, Advanced Configuration and Power Interface (ACPI) and is the industry standard widely used power and configuration interface for laptops, desktops, and server systems and is an integral part of the computer system to provide power management functions. ACPI allows OS-level control over power states, device configuration, and thermal monitoring. ACPI acts as an intermediary between the operating system and the hardware. It uses tables (stored in firmware) to tell the OS what hardware exists and how to control it. The OS runs an ACPI driver that interprets these tables to manage power, plug-and-play devices, and system events. Applicant is invited to review the NPLs titled “Modern System Power” and the “Advanced Configuration and Power Interface” as extrinsic evidence of the operation power management in computer. Regarding claim 21, the claim is amended to remove the second processor and reciting that the first processor (equivalent to the processor of claim 28) to perform the power balancing function and thus the argument is moot. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21,22, 24-26, 28-29, 31-33, 35-36 and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Meier US 20080263373 A1 in view of Pawar US 20180275738 A1. Regarding claim 21, Meier teaches a method for controlling power consumption of a first processor in a first device (processor 100 of system 400, Fig, 4, see also Fig. 1-3, and 5) comprising: issuing, by the first processor that is operative to produce data (processor executes instructions and communicates with various devices including system memory to par. 15 and 40), allocated power information for a peripheral device (Fig. 1 and 4, devices 471-474) to cause an allocated power to be provided to the device (processor 100 may include a power controller 150 to implement a token-based power control mechanism to manage the distribution of power from the power supply to the processing devices within computer system as shown inf Fig. 2-3, steps 210-230 and 305-315, see par. 16-17 and 24, token based information is exchanged from the processor/power controller and peripheral devices) shifting, by the first processor, at least a portion of the allocated power from the various connected device including peripheral devices in response to a usage change event associated with the connected device (for each connected device, detect change in power usage and redistribute power toke by reallocate excess power to another device. See Fig. 2, step 240-260, Fig. 3, 315-350). Though not explicitly state that power is shifted from the peripheral device to the processor based on the usage change in the peripheral device. Meier teaches balancing power based on power demand and usage thus would inherently shifting power from peripheral to processor based on the changes in power usage and demand of the peripheral devices. In the alternative, Pawar teaches method for controlling power consumption of a first processor (Fig. 8, processor 2110 of SOC 2100, par. 95) similar to Meier and further teaches ACPI power management (par. 39) wherein the processor issues allocated power information to peripheral devices (Fig. 4, dynamically scan and monitor ports to collect power information, par. 77) and shifting, by the fist processor, at least a portion of the allocated power from the device to the processor in response to a usage change event associated with the device (Fig. 4-5, monitoring the ports, adjust power profiles and reassign power unused power from the peripheral, par. 83-90). It would have been obvious to one having ordinary skills in the art to prior to the effective filing date to combine the teaching of Meier and Pawar to monitor and dynamically reassign unused power from the peripheral devices (un-core) to allow a power management policy to provide for processor core to operate in turbo modes in which a platform power budget may be dynamically re-balanced, while allowing the overall platform to be designed for a smaller maximum power level (Varma, par. 35, 39 and 110 and 118) Regarding claim 22, Meier teaches the method of claim 21 wherein shifting by the first processor comprises using the allocated power shifted from the peripheral device to change a performance level of the first processor while leaving one or more of a frequency and voltage setting of the first processor at a current level (Fig. 2 and 3, redistributing power tokens does not require to change in frequency or voltage settings). Regarding claim 24; Meier teaches method of claim 21 further comprising shifting, by the first processor, at least a portion of the allocated power back to the peripheral device in response to another usage change event. (see loop, Fig. 2, loop 245 to 230, Fig 3, 305-355) Regarding claim 25; Meier teaches method of claim 21 wherein the allocated power for the peripheral device is based on power usage requirements of the first processor and based on the power usage requirements of the peripheral device (see Fig. 2-3, redistributing power tokens based on power usage requirements of both computing devices). Regarding claim 26; Meier teaches method of claim 21 wherein shifting, by the first processor, at least the portion of the allocated power from the peripheral device to the first processor comprises at least one of: maintaining an amount of allocated power constant or changing an amount of allocated power upon request from the peripheral device (power distributed using power budget of the apparatus, par. 5, 20-22 and 27). Regarding claim 28, Meier teaches a computing device comprising: at least one peripheral communication port (ports connected interface 130 and southbridge, par. 16); a power delivery controller (power controller 150/450) operatively coupled to the at least one peripheral communication port (ports connected interface 130); and at least one processor of the computing device that is operative to produce data (processing device 100 executes instructions to access data in memory 140, par. 15 and 40) operatively couple to the power delivery controller and to at least one of peripheral communication port (Fig. 1 and 4). The rest of the claims regarding the operation of the processor to issue and shifting power is the same as recited in claim 21 and therefore rejected accordingly. Claims 35 includes all the limitations of claim 1 and is rejected on the same basis. Claims 29, 31-33 and 36, 38-39 repeat the same limitations of claims 22, 24-26 and rejected accordingly. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM HUYNH whose telephone number is (571)272-4147. The examiner can normally be reached M-Th 5:30am-3:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAWEED ABBASZADEH can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KIM HUYNH/ Primary Patent Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Oct 19, 2023
Application Filed
Jun 06, 2024
Response after Non-Final Action
Feb 26, 2025
Non-Final Rejection — §103
May 29, 2025
Response Filed
Jul 15, 2025
Non-Final Rejection — §103
Oct 06, 2025
Response Filed
Nov 17, 2025
Final Rejection — §103
Feb 12, 2026
Applicant Interview (Telephonic)
Feb 12, 2026
Examiner Interview Summary
Feb 27, 2026
Request for Continued Examination
Mar 09, 2026
Response after Non-Final Action
Mar 20, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
56%
Grant Probability
57%
With Interview (+0.6%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 71 resolved cases by this examiner. Grant probability derived from career allow rate.

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