DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the inverted input signal is at a voltage level opposite to a voltage level of the input signal recited in claims 1 and 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-12 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Kato (Fig. 1); 8,222,957].
Regarding claim 1, wherein the inverted input signal (Vin-) is at a voltage level (voltage level of the Vin-) opposite to a voltage level (voltage level of the Vin+) of the input signal (Vin+) and the remainder of the claim 1 rejection is exactly same as the previous office action.
Regarding claim 2, exactly same as the previous office action.
Regarding claims 3 and 16, exactly same as the previous office action.
Regarding claim 4, exactly same as the previous office action.
Regarding claim 5, exactly same as the previous office action.
Regarding claim 7, exactly same as the previous office action.
Regarding claim 8, exactly same as the previous office action.
Regarding claim 9, exactly same as the previous office action.
Regarding claims 10 and 17, exactly same as the previous office action.
Regarding claim 11, exactly same as the previous office action.
Regarding claims 12 and 18, exactly same as the previous office action.
Regarding claim 15, Kato discloses an amplifier circuit comprising a transmission circuit (105 in Fig. 1) configured to output (Vout) an input signal (Vin+) and an inverted input signal (Vin-), and a reception circuit (everything in Fig. 1 except 105) configured to connect a first supply node (the node between the transistor M107 and the supply voltage Vdd) to a power supply voltage terminal (Vdd) through a first PMOS transistor (M107) which is turned on by a first control voltage (the control voltage applying to the gate terminal of the transistor M107) and to connect a second supply node (the node between the transistor M113 and the ground voltage Vss) to a ground voltage terminal (Vss) through a first NMOS transistor that is turned on by a second control voltage (the control voltage applying to the gate terminal of the transistor M113) and wherein the reception circuit (everything in Fig. 1 except 105) is configured to directly receive a power supply voltage (Vdd) through the first supply node (the node between the transistor M107 and the supply voltage Vdd) and to directly receive a ground voltage (Vss) through the second supply node (the node between the transistor M113 and the ground voltage Vss) and to control a current input and output between the power supply voltage (Vdd) and ground voltage terminals (Vss) and internal nodes according to voltages of the input signal (Vin+) and the inverted input signal (Vin-), and to sense and amplify a voltage difference between the input signal (Vin+) and the inverted input signal (Vin-) to generate an internal clock (the clock signal generating at the output terminal of 101 or 102) and wherein the inverted input signal (Vin-) is at a voltage level (voltage level of the Vin-) opposite to a voltage level (voltage level of the Vin+) of the input signal (Vin+).
Allowable Subject Matter
Claims 6, 13, 14 and 19-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: Regarding claim 6, the closest prior art of record, Kato does not disclose the following limitation: the second current source further includes a transfer gate and control a voltage difference of the fifth internal node and the sixth internal node. Regarding claim 13, the closest prior art of record, Kato does not disclose the following limitation: an input unit configured ------------ sixth internal node to generate an internal clock. Regarding claim 14, the closest prior art of record, Kato does not disclose the following limitation: an input unit configured ------------ sixth internal node to generate an internal clock. Regarding claim 19, the closest prior art of record, Kato does not disclose the following limitation: an input unit configured ------------ sixth internal node to generate an internal clock. Regarding claim 22, the closest prior art of record, Kato does not disclose the following limitation: an input unit configured ------------ sixth internal node to generate an internal clock. Regarding claim 23, the closest prior art of record, Kato does not disclose the following limitation: an input unit configured ------------ sixth internal node to generate an internal clock.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-23 have been considered but are moot in view of the new grounds of rejection.
Applicant argues that Kato fails to teach or suggest “the inverted input signal is at a voltage level opposite to a voltage level of the input signal“ as set forth in claim 1 and claim 15 as amended. Applicant further argues that Kato teaches that the non-inverting input voltage Vin+ and the inverting input voltage Vin- in Fig. 1 are constant analog differential voltages, not signals at opposite voltage levels. Examiner totally disagrees with this statement. Inverting input voltage Vin- of Kato possess an equal amplitude of non-inverting signal Vin+ with the phase 180 degrees out of the Vin+ signal. Therefore, the signals (Vin+ and Vin-) carry equal and opposite voltage signals. They are indeed two complementary input signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HENRY CHOE/ Primary Examiner, Art Unit 2843
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