DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 1/2/26, which has been entered.
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 10/7/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugumar (US 11663130) in view of Gilbert (US 20140208039) and Osanai (US 20060271767).
With respect to claim 8, the Sugumar reference teaches a computer system, the computer system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage media, and program instructions stored on at least one of the one or more tangible storage media for execution by at least one of the one or more processors via at least one of the one or more memories, (see fig. 4; and corresponding specification text) wherein the computer system is capable of performing a method comprising:
identifying one or more prefetch streams; (column 3, line 48-64, where there is a buffer (e.g., a speculative fill buffer) for storing cache lines of data while the instruction that pulled them from the memory system is still being executed speculatively. FIG. 4 shows example of where the buffer may be located relative to a processor pipeline (e.g., next to the first level data cache))
saving a memory access instruction that created or advanced a selected prefetch stream from the one or more prefetch streams; (column 13, lines 21-33, where integrated circuit 400 includes a buffer 450 with entries that are each configured to store a cache line of data and a tag that includes an indication of a status of the cache line stored in the entry. The status can take values from a set that includes speculative, validated, and cancelled)
However, the Sugumar reference does not explicitly teach determining that a predicted branch was predicted incorrectly; in response to determining that the predicting branch was predicted incorrectly, detecting a pipeline flush prior to the saved memory access instruction; and stopping a portion of the selected prefetch stream that follows the saved memory access instruction based on the detected pipeline flush and on a type of the saved memory access instruction, wherein upon determining that the type of the memory access instruction is an advance type instruction selected from a load instruction or a store instruction, performing the stopping by pausing the selected prefetch stream.
The Gilbert reference teaches it is conventional to have:
determining that a predicted branch was predicted incorrectly; (paragraph 31, where upon reaching the execute stage 134, if the execute condition specified for the loop ending conditional branch instruction has evaluated opposite to its prediction, [i.e. the branch was predicted incorrectly] any pipeline speculative execution of instructions on the wrong instruction path are corrected, for example by flushing the pipeline, and such a correction may include canceling pending prefetches that are associated with the wrong instruction path)
in response to determining that the predicting branch was predicted incorrectly, detecting a pipeline flush prior to the saved memory access instruction; (paragraph 31, where upon reaching the execute stage 134, if the execute condition specified for the loop ending conditional branch instruction has evaluated opposite to its prediction, any pipeline speculative execution of instructions on the wrong instruction path are corrected, for example by flushing the pipeline, and such a correction may include canceling pending prefetches that are associated with the wrong instruction path) and
stopping a portion of the selected prefetch stream that follows the saved memory access instruction based on the detected pipeline flush and on a type of the saved memory access instruction. (paragraph 31, where upon reaching the execute stage 134, if the execute condition specified for the loop ending conditional branch instruction has evaluated opposite to its prediction, any pipeline speculative execution of instructions on the wrong instruction path are corrected, for example by flushing the pipeline, and such a correction may include canceling pending prefetches that are associated with the wrong instruction path)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Sugumar reference to have wherein determining that a predicted branch was predicted incorrectly; in response to determining that the predicting branch was predicted incorrectly, detecting a pipeline flush prior to the saved memory access instruction; and stopping a portion of the selected prefetch stream that follows the saved memory access instruction based on the detected pipeline flush and on a type of the saved memory access instruction, as taught by the Gilbert reference.
The suggestion/motivation for doing so would have been to have reducing of cache pollution by use of a prefetch logic that recognizes exits from software loops or function returns to cancel any pending prefetch request operations. (Gilbert, abstract)
However, the combination of the Sugumar and Gilbert references does not explicitly teach wherein upon determining that the type of the memory access instruction is an advance type instruction selected from a load instruction or a store instruction, performing the stopping by pausing the selected prefetch stream.
The Osanai reference teaches it is conventional to have wherein upon determining that the type of the memory access instruction is an advance type instruction selected from a load instruction or a store instruction, performing the stopping by pausing the selected prefetch stream. (paragraph 67, where in one embodiment, DL1 535 is configured to perform partial address comparisons on the addresses of instructions while the instructions are in pipeline 510, in load queue 515 (where load-type instructions are buffered), or in store queue 520 (where store-type instructions are stored). When a full comparison establishes a dependency for a suspended instruction, any level-2 data pre-fetch operations are cancelled [i.e. prefetching is cancelled when a ‘type’ of command, including loads and stores, establishes a dependency for a suspended instruction during comparisons])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Sugumar and Gilbert references to have wherein upon determining that the type of the memory access instruction is an advance type instruction selected from a load instruction or a store instruction, performing the stopping by pausing the selected prefetch stream, as taught by the Osanai reference.
The suggestion/motivation for doing so would have been to have prevent a dependent load instruction from loading "bad" data. (Osanai, paragraph 72)
Therefore it would have been obvious to combine the Sugumar, Gilbert, and Osanai references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 9, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 8, wherein a type of the saved memory access instruction includes a hardware type instruction and a software type instruction. (Sugumar, column 9, lines 52-59, where a prefetch request can be or can include a software prefetch request such that an explicit prefetch instruction that is inserted into the pipeline 104 includes a particular address to be prefetched. A prefetch request can be or can include a hardware prefetch that is performed by hardware within the processor (e.g., the processor core 102))
With respect to claim 10, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 8, wherein the type of the memory access instruction is a hardware advance type instruction, and the stopping includes pausing the selected prefetch stream. (Sugumar, column 9, lines 52-59, where a prefetch request can be or can include a software prefetch request such that an explicit prefetch instruction that is inserted into the pipeline 104 includes a particular address to be prefetched. A prefetch request can be or can include a hardware prefetch that is performed by hardware within the processor (e.g., the processor core 102)); and column 14, line 39 to column 15, line 5, where if the load instruction is determined to have resulted from a misprediction and is flushed from the processor pipeline, then the status of the entry 520 may be changed to cancelled by updating the indication of status 580 for the entry 520. Cancelled entries may be subject to deletion or release and overwritten with new data)
With respect to claim 11, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 10, wherein the type of the memory access instruction is, more specifically, a load instruction or a store instruction. (Sugumar, see fig. 6; and where FIG. 6 is a flow chart of an example of a technique 600 for executing a load instruction with cache replacement mechanisms for speculative execution)
With respect to claim 12, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 11, further comprising: upon determining that the type of the memory access instruction is a create type instruction, performing the stopping by cancelling the selected prefetch stream. (Sugumar, column 16, lines 25-35, where If (at step 645) the load instruction is flushed from the pipeline, then, responsive to the load instruction being flushed from the processor pipeline, updating 650 the tag of the first entry to indicate the status is cancelled. In some implementations, a context switch by a processor core including the processor pipeline may cause all entries in the buffer marked as speculative to be cancelled)
With respect to claim 13, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 8, further comprising: loading a prefetch stream from the one or more prefetch streams into a destination cache memory. (Sugumar, see fig. 4; and column 12, line 62 to column 13, line 13, where FIG. 4 is a block diagram of an example of an integrated circuit 400 for executing instructions with cache replacement mechanisms for speculative execution)
With respect to claim 14, the combination of the Sugumar, Gilbert, and Osanai references teaches the computer system of claim 13, wherein the detecting is performed by a dedicated prefetch flush detection module. (Sugumar, see fig. 4; and column 12, line 62 to column 13, line 13, where FIG. 4 is a block diagram of an example of an integrated circuit 400 for executing instructions with cache replacement mechanisms for speculative execution)
Claims 1-7 are processor-implemented method implementation of claims 8-14, and rejected under a similar rationale as shown above.
Claims 15-20 are computer program product implementation of claims 8-14, and rejected under a similar rationale as shown above.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 7-9 of the remarks) and amendments with respect to claims 1-20 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Osanai to teach the newly added limitations as shown in the rejections above.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights