DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/26 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first circuit includes “a first capacitor and a second capacitor wherein the first capacitor is coupled across the first current source, and the second capacitor is coupled across the second current source” as recited in claim 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 8, the recitation “wherein the signal generator is configurable to: enable the first transistor in response to the input of the signal generator being having a third state; and enable the second transistor in response to the input of the signal generator having a fourth state” is indefinite because the claim recited earlier that “the signal generator having an input coupled to the input of the first circuit” (see lines 8-9 of claim 7 which claim 8 depends on), and the claim also already recited that “the first circuit responsive to the input having a first state and a second state” (see lines 2-5 of claim 1 which claim 8 depends on), so it is not clear why claim 8 is now recited the input (of the signal generator which also is the input of the first circuit) being having “a third state” and “a fourth state”. It is suggested that “a third state” on lines 2-3 and “a fourth state” on lines 4-5 of claim 8 be changed to “the first state” and “the second state”, respectively. Clarification and/or appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-12, and 23-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishino (US 2022/0302839).
For claim 1, Figures 2-7 of Ishino teaches a driver, comprising: a first circuit (410, 420) having an input (HIN), a first output (OUT1), and a second output (OUT2), the first circuit (410, 420) configurable to provide a first current (I1) at the first output (OUT1) of the first circuit (410, 420) responsive to the input (HIN) having a first state, and provide a second current (I2) at the second output (OUT2) of the first circuit (410, 420) responsive to the input (HIN) having a second state, in which each of the first and second currents (I1 and I2) has a first non-zero level within a first time (see Figure 3, each of I1 and I2 has a first non-zero level at a first time where Sp1 and Sp2 respectively having logic H, i.e., at a first period of signal HIN) and a second non-zero level within a second time (each of I1 and I2 should have a second non-zero level at a second time where Sp1 and Sp2 respectively having logic H, i.e., at the next period of signal HIN); a second circuit (430, 432, 440) having a first input (I1), a second input (I2), a first output (Q), and a second output (/Q), the first input (I1) of the second circuit (430, 432, 440) coupled to the first output (OUT1) of the first circuit (410, 420), and the second input (I2) of the second circuit (430, 432, 440) coupled to the second output (OUT2) of the first circuit (410, 420), the second circuit (430, 432, 440) configurable to set voltages of the first and second outputs (Q and /Q) of the second circuit (430, 432, 440) responsive to a comparison between the first current (I1 which provides corresponding I3) and the second current (I2 which provides corresponding I4) (see [0057]-[0059] and [0063]); a logic circuit (450) having a reset input and a set input (inputs of 450 coupled to Q and Q/; or inputs of INV3 and INV4), the reset input (input of 450 coupled to Q) coupled to the first output (Q) of the second circuit (430, 432, 440), and the set input (input of 450 coupled to Q/) coupled to the second output (Q/) of the second circuit (430, 432, 440); and a gate control circuit (310) having an input (input of 310) coupled to an output (LVSFTOUT) of the logic circuit (450).
For claim 2, Figures 2-7 of Ishino teaches wherein the second circuit (430, 432, 440) is configurable to: set the first output of the second circuit (Q) at a first state responsive to the first current (I1 which provides corresponding I3) being greater than the second current (I2 which provides corresponding I4), (see [0057]-[0059] and [0063]); and set the second output (/Q) of the second circuit (440) at the first state responsive to the second current (I2 which provides corresponding I4) being greater than the first current (I1 which provides corresponding I3), (see [0057]-[0059] and [0063]).
For claim 3, Figures 2-7 of Ishino teaches wherein the logic circuit (450) includes a set-reset latch (INV3-INV4).
For claim 4, Figures 2-7 of Ishino teaches wherein the second circuit (430, 432, 440) comprises: a current-to-voltage (I2V) converter (430, 432) having a first I2V input (I1), a second I2V input (I2), a first I2V output (I3), and a second I2V output (I4), the first I2V input (I1) coupled to the first input (I1) of the second circuit (430, 432, 440), and the second I2V input (I2) coupled to the second input (I2) of the second circuit (430, 432, 440); a first inverter (INV1) having an input coupled to the first I2V output (I3); and a second inverter (INV2) having an input coupled to the second I2V output (I4).
For claim 7, Figure 5 of Ishino teaches wherein the first circuit (410, 420) includes a first transistor (M1) having a control input (gate) and first (drain) and second (source) terminals, the first terminal (drain) of the first transistor (M1) coupled to the first output (OUT1); a second transistor (M2) having a control input (gate) and first (drain) and second (source) terminals, the first terminal (drain) of the second transistor (M2) coupled to the second output (OUT2); a first current source circuit (M3) coupled to the second terminal (source) of the first transistor (M1); a second current source circuit (M4) coupled to the second terminal (source) of the second transistor (M2); and a signal generator (410) having: an input (Input) coupled to the input (HIN) of the first circuit (410) a first output (Sp1) coupled to the control input (gate) of the first transistor (M1); and a second output (Sp2) coupled to the control input (gate) of the second transistor (M2).
Insofar as understood in claim 8, Figure 5 of Ishino teaches wherein the signal generator (410) is configurable to: enable the first transistor (M1) in response to the input (Input) of the signal generator (410) being having the first state (or a third state); and enable the second transistor (M2) in response to the input (Input) of the signal generator (410) having the second state (or a fourth state).
For claim 9, Figures 2-7 of Ishino teaches an apparatus, comprising: a controller (circuitry that generates HIN) having a controller output (HIN); a current generator (410, 420) having an input (Input), a first output (OUT1), and a second output (OUT2), the input (Input) of the current generator (410, 420) coupled to the controller output (HIN), the current generator (410, 420) configurable to generate a first current (I1) at the first output (OUT1) responsive to the input (Input) having a first state, and generate a second current (I2) at the second output (Out2) responsive to the input (Input) having a second state in which each of the first and second currents (I1 and I2) has a first non-zero level within a first time (see Figure 3, each of I1 and I2 has a first non-zero level at a first time where Sp1 and Sp2 respectively having logic H, i.e., at a first period of signal HIN) and a second non-zero level within a second time (each of I1 and I2 should have a second non-zero level at a second time where Sp1 and Sp2 respectively having logic H, i.e., at the next period of signal HIN); a comparator (430, 432, 440) having a first comparator input (I1), a second comparator input (I2), a first comparator output (Q), and a second comparator output (/Q), the first comparator input (I1) coupled to the first output (OUT1), the second comparator input (/Q) coupled to the second output (OUT2), the comparator (430, 432, 440) configurable to set states of the first and second comparator outputs (Q and /Q) responsive to a comparison between the first current (I1 which provides corresponding I3) and the second current (I2 which provides corresponding I4) (see [0057]-[0059] and [0063]); a logic circuit (450) having inputs (inputs of 450) coupled to the first and second comparator outputs (Q and /Q); a gate control circuit (310) having an input and an output (input and output of 310), the input of the gate control circuit (310) coupled to an output (LVSFTOUT) of the logic circuit (450); and a transistor (MH) having a control input coupled to the output of the gate control circuit (310).
For claim 10, Figures 2-7 of Ishino teaches wherein the transistor (MH) is a first transistor (MH) having first and second terminals, and the gate control circuit (310) is a first gate control circuit (310), and the apparatus further comprises: a second gate control circuit (110, see Figure 2) having an output; and a second transistor (ML) having a control input and first and second terminals, the first terminal of the second transistor (ML) coupled to the second terminal of the first transistor (MH), and the control input of the second transistor (ML) coupled to the output of the second gate control circuit (110, see Figure 2).
For claim 11, Figures 2-7 of Ishino teaches wherein the comparator is configurable to: set the first comparator output (Q) at a first state responsive to the first current (I1 which provides corresponding I3) being greater than the second current (I2 which provides corresponding I4) (see [0057]-[0059] and [0063]); and set the second comparator output (/Q) at the first state responsive to the second current (I2 which provides corresponding I4) being greater than the first current (I1 which provides corresponding I3) (see [0057]-[0059] and [0063]).
For claim 12, Figures 2-7 of Ishino teaches wherein the comparator (430, 432, 440) comprises: a current-to-voltage (I2V) converter (430, 432) having a first I2V input (I1), a second I2V input (I2), a first I2V output (I3), and a second I2V output (I4), the first I2V input (I1) coupled to the first comparator input (I1), and the second I2V input (I2) coupled to the second comparator input (I2); a first inverter (INV1) having an input coupled to the first I2V output (I3); and a second inverter (INV2) having an input coupled to the second I2V output (I4).
For claim 23, Figures 2-7 of Ishino teaches wherein the first circuit (410, 420) is configurable to provide the first current (I1) at the first output (Out1) responsive to the input (Input) transitioning from the second state to the first state (see [0057]-[0059] and [0063]), and provide the second current (I2) at the second output (Out2) responsive to the input (Input) transitioning from the first state to the second state (see [0057]-[0059] and [0063]).
For claim 24, Figures 5 and 7 of Ishino teaches wherein the first circuit (410, 420) includes a first switch (M1), a first current source (M3), and a first capacitor (Cp1, see Figure 7) coupled between the first output (OUT1) and a ground terminal, and a second switch (M2), a second current source (M4), and a second capacitor (Cp2, see Figure 7) coupled between the second output (OUT2) and the ground terminal, wherein the first capacitor (Cp1, see Figure 7) is coupled across the first current source (M3), and the second capacitor (Cp2, see Figure 7) is coupled across the second current source (M4).
Allowable Subject Matter
Claims 5-6, 13-14 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 03/16/26 have been fully considered but they are not persuasive.
Applicant argues that, for claims 1 and 9, Amended claims 1 and 9 recite "each of the first and second currents has a first non-zero level within a first time and a second non-zero level within a second time." Ishino fails to disclose at least these claim elements, at least because in Ishino, the currents 13 and 14 (the alleged first and second currents) are generated from currents Il and 12. As best understood by Applicant, when transistor M1 is turned on, current I1 has one value, and when transistor M1 is turned off, current I1 is zero. Accordingly, current I1 does not have a first non-zero level and a second non-zero level. In contrast, claim 1 recites "each of the first and second currents has a first non-zero level within a first time and a second non- zero level within a second time”.
However, the above argument is not persuasive because Ishino teaches each of the first and second currents (I1 and I2) has a first non-zero level within a first time (see Figure 3, each of I1 and I2 has a first non-zero level at a first time where Sp1 and Sp2 respectively having logic H, i.e., at a first period of signal HIN) and a second non-zero level within a second time (each of I1 and I2 should have a second non-zero level at a second time where Sp1 and Sp2 respectively having logic H, i.e., at the next period of signal HIN). Thus, for broadest reasonable interpretation, amended claims 1 and 9 are met by Ishino.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-8101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842