DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/22/2026 has been entered.
Response to Amendments
Applicant's response of 09/04/2026 has been acknowledged. Claims 1, 9, and 15 have been amended.
This office action considers claims 1-13, 15-18, and 20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 09/04/2026 with respect to the rejection of claim 1-13, 15-18, and 20 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210183780 A1 – hereinafter Kim-780) in view of Chang et al. (US 20200006290 A1 – hereinafter Chang), Kim (US 20210028096 A1 – hereinafter Kim-096), Jin et al. (US 20120139097 A1 – hereinafter Jin), Kouda (US 5818105 A), and (Han et al. (US 20140346667 A1 - hereinafter Han).
Regarding independent claim 1, Kim-780 teaches:
(Currently Amended) A semiconductor (10a – Fig. 1 – [0021] –
“semiconductor package 10a”) comprising:
a first redistribution structure comprising a first redistribution layer and a first
redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”), the first redistribution bonding pad (114) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer);
a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’), the first semiconductor chip (120) including at least two side surfaces (Fig. 1 shows this);
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120), the second redistribution structure comprising a second redistribution insulating layer and a second redistribution bonding pad, the second redistribution bonding pad electrically connected to the second redistribution layer;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) and the first redistribution bonding pad (114) to each other (Fig. 1 shows this) the bonding wire having a height of 10 µm to 100 µm from an upper surface of the second redistribution structure (200);
a first chip connection terminal (122 – Fig. 1 – [0025] – “terminals 122 (e.g., solder balls or solder bumps)”) arranged on a lower portion of the first semiconductor chip (120); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS),
wherein the molding layer comprises a first molding layer on each of the at least two side surfaces of the first semiconductor chip, side surfaces of the first molding layer being coplanar with side surfaces of the second redistribution structure, and
wherein the molding layer comprises a second molding layer covering at least a portion of the first semiconductor chip, the first molding layer, the second redistribution structure (200), the bonding wire (220), and the first chip connection terminal (111 – Fig. 2B – [0029] – “The lower molding layer 117 may substantially, if not fully fill between each of the chip bumps 111”) on the first redistribution structure (FRS).
Kim-780 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) comprising a first redistribution (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”) and a second redistribution bonding pad (chang (114b – Fig. 1G - [0030] – “plurality of conductive elements 114b” – this is a bonding pad), the second redistribution bonding pad (114b) electrically connected to the second redistribution layer (114a – [0030] – “plurality of conductive elements 114b embedded in the dielectric layers 114a”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result of [0006] – “the simplicity of the manufacturing process of the package structure may be realized, thereby reducing the manufacturing cost.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Kim-780 and Chang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim-096 teaches
wherein the molding layer (170 – Fig. 1 – [0028] – “The molding layer 170”) comprises a first molding layer (170 – Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”) on each of the at least two side surfaces of the first semiconductor chip (110 - Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”), side surfaces of the first molding layer (170) being coplanar with side surfaces of the second redistribution structure (120 – Fig. 1 – [0029] – “redistribution line structure 120 may be arranged on the semiconductor chip 110 and the molding layer 170” – Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Kim-096 into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Kim-096 in the manner set forth above to produce the predictable result [0004] – “provides semiconductor packages and semiconductor modules having increased reliability.” This provides protection to the chip and its connecting structure.
Kim-780, Chang, and Kim-096 do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Jin teaches
wherein the molding layer ([0030] – “a first molding portion 136, a second molding portion 144” – hereinafter ‘MDL’) comprises a second molding layer (144b – Fig. 4B – [0048] – “the second molding portion 144b completely covers the top surface of the first molding portion 136 and of the semiconductor chip 130”) covering at least a portion of the first semiconductor chip (130), the first molding layer (144 – Fig. 4B – [0030] – “a first molding portion 136”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Jin into Kim-780, Chang, and Kim-096.
An ordinary artisan would have been motivated to use the known technique of Jin in the manner set forth above to produce the predictable result [0003] – “a first molding portion protecting a chip package interaction and a semiconductor chip, a second molding portion protecting the chip package interaction.”
Kim-780, Chang, Kim-096, and Jin do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kouda teaches
the bonding wire (16 – Fig. 12 – [16:7-9] – “the maximum loop height of the bonding wire pieces 16 from the bottom surface of the semiconductor chip 14 was practically limited to 120 microns or less”) having a height of 10 µm to 100 µm (16 – Fig. 12 – [16:7-9] – “the maximum loop height of the bonding wire pieces 16 from the bottom surface of the semiconductor chip 14 was practically limited to 120 microns or less” – the height includes the thickness of the semiconductor chip 14 that corresponds to the second redistribution structure, therefor the height above the upper surface of the chip is less than 120 microns or less).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bonding wire structure as taught by Kouda into Kim-780, Chang, Kim-096, and Jin.
An ordinary artisan would have been motivated to use the known technique of Kouda in the manner set forth above to produce the predictable result [1:34-35] – “To reduce thermal resistance and thickness or height of the package body.”
Kim-780, Chang, Kim-096, Jin, and Kouda do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Han teaches
the first chip connection terminal (111 – Fig. 2B – [0029] – “The lower molding layer 117 may substantially, if not fully fill between each of the chip bumps 111”) on the first redistribution structure.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection terminal structure as taught by Han into Kim-780, Chang, Kim-096, Jin, and Kouda.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result of [0004] – “A package on package (PoP) technology where a package is stacked on the other package was proposed to laminate a plurality of semiconductor chips on each other and to realize a high density chip lamination. In the PoP technology, each of the semiconductor chips may pass a test. As a result, a defect rate for the final products may decrease. These PoP type semiconductor packages may be used to satisfy miniaturization of electronic portable devices and functional diversification of mobile products.”
Regarding claim 2, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 2 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 1, wherein a second
width of the second redistribution structure (200) is less than a first width of the first redistribution structure (110 – Fig. 1 shows this).
Regarding claim 3, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 3 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 1, wherein
the first redistribution bonding pad (114) is at an upper portion of the first
redistribution structure (110 – Fig. 1 shows this), and
the second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) is at an upper portion of the second redistribution structure (200 – Fig. 1 shows this).
Regarding claim 4, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 4 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 1,
wherein the bonding wire (220) is electrically and continuously connecting ([0026] – “The interposer substrate 200 and the first package substrate 110 may be electrically connected to each other through one or more connection terminals included in the semiconductor package 10a. For example, the interposer substrate 200 may be mounted on the first package substrate 110 in a wire bonding manner. In other words, the connection terminal included in the semiconductor package 10a may include the bonding wire 220 that connects the interposer substrate 200 to the first package substrate 110, and the interposer substrate 200 may be electrically connected to the first package substrate 110 through a bonding wire 220”) the second redistribution bonding pad (204) and the first redistribution bonding pad to each other (114 – Fig. 1 – [0026] – “The bonding wire 220 may connect the fourth substrate pads 204 of the interposer substrate 200 to the second substrate pads 114 of the first package substrate 110”).
Regarding claim 5, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 5 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 1,
wherein the second redistribution structure (200) is on an upper surface of the first molding layer (40) and an upper surface of the first semiconductor chip (120).
Regarding claim 6, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 6 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 1, further
comprising a first connection pad (112 – Fig. 1 – [0023] – “first substrate pads 112”) at an upper portion of the first redistribution structure (110 – Fig. 1 shows this), and a second connection pad at a lower portion of the first redistribution structure, wherein,
the first connection pad (112) is connected to the first chip connection terminal (122), and
the second connection pad is connected to a first external connection terminal.
Kim-780, Chang, Kim-096, Jin, and Kouda do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Han teaches
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) at a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}),
the second connection pad (108) is connected to a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108” – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection pad structure as taught by Han into Kim-780, Chang, Kim-096, Jin, and Kouda.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 7, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 7 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 1, further comprising:
a third connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) at an
upper portion of the second redistribution structure (200); and
a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) in the molding layer (130), the connection hole (OP) exposing the third connection pad (202).
Regarding claim 8, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, and Han, teaches claim 1 from which claim 8 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 1,
wherein the first chip connection terminal (122) is connected to the first redistribution structure (110 – Fig. 1 shows this).
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-780 in view of Chang, Kim-096, Jin, Han, and Liao et al. (US 20180315706 A1 – hereinafter Liao).
Regarding independent claim 9, Kim-780 teaches:
(Currently Amended) A semiconductor package (10a – Fig. 1 – [0021]
– “semiconductor package 10a”) comprising:
a first redistribution structure including a fan-in region and a fan-out region, the
fan-in region including at least two sides, and the fan-out region on each of the at least two sides of the fan-in region, the first redistribution structure comprising a first redistribution insulating layer, a first redistribution layer insulated by the first redistribution insulating layer, and a first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer), the first redistribution bonding pad (114) on an upper portion of the first redistribution insulating layer (110) in the fan-out region (kim (Fig. 1 annotated, see below – hereinafter ‘FO’);
a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’) in the fan-in (FI) region, the first semiconductor chip (120) including at least two side surfaces (200a – Fig. 1 annotated, see below – [0040] – “side surfaces 200a of the first semiconductor chip 120”) in the fan-out region (kim (FO – Fig. 1 annotated shows this);
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120) in the fan-in (FI) region and the fan-out region (FO), the second redistribution structure comprising a second redistribution insulating layer, a second redistribution layer insulated by the second redistribution insulating layer, and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) electrically connected to the second redistribution layer, the second redistribution layer on an upper portion of the second redistribution insulating layer in the fan-out region;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204) in the fan-out (FO) region and the first redistribution bonding pad (114) in the fan-out (FO) region to each other (Fig. 1 shows this);
a first chip connection terminal (122) arranged on a lower portion of the first semiconductor chip (120), the first chip connection terminal (122) connected to the first redistribution structure (110 – Fig. 1 shows this);
an underfill layer (124 – Fig. 1 – [0025] – “flux 124” – this corresponds to an underfill layer) arranged on the lower portion of the first semiconductor chip (120 – Fig. 1 shows this), the underfill layer (124) supporting the first chip connection terminal (112 – Fig. 1 shows this); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (110) in the fan-in (FI) region and the fan-out (FO) region,
wherein the molding layer comprises a first molding layer on each of the at least two side surfaces of the first semiconductor chip in the fan-out region (FO), side surfaces of the first molding layer being coplanar with side surfaces of the second redistribution structure, and
wherein the molding layer comprises a second molding layer covering at least a portion of the first semiconductor chip, the first molding layer, the second redistribution structure (200), the bonding wire (220), and the first chip connection terminal on the first redistribution structure (FRS) in the fan-out region (FO), the second molding layer having a height of 20 µm to 500 µm from an upper surface of the second redistribution structure (200).
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Kim-780 does not expressly disclose the other limitations of claim 9.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) including a fan-in region (Fig. 1O annotated, see below – hereinafter ‘FI’) and a fan-out (Fig. 1O annotated, see below – hereinafter ‘FO’) region, the fan-in (FI) region including at least two sides, and the fan-out region on each of the at least two sides of the fan-in (FI) region, the first redistribution structure (100) comprising a first redistribution insulating layer (106a – Fig. 1B – [0015] – “plurality of dielectric layers 106a”), a first redistribution layer (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”) insulated by the first redistribution insulating layer (106a),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”), a second redistribution layer (114b – Fig. 1G – [0030] – “plurality of conductive elements 114b”) insulated by the second redistribution insulating layer (114a), and a second redistribution bonding pad electrically connected to the second redistribution layer (114b), the second redistribution layer (114b) on an upper portion of the second redistribution insulating layer (114a – Fig. 1G shows this) in the fan-out region (FO).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780 and Chang do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Kim-096 teaches
wherein the molding layer (170 – Fig. 1 – [0028] – “The molding layer 170”) comprises a first molding layer (170 – Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”) on each of the at least two side surfaces of the first semiconductor chip (110 - Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”) in the fan-out region, side surfaces of the first molding layer (170) being coplanar with side surfaces of the second redistribution structure (120 – Fig. 1 – [0029] – “redistribution line structure 120 may be arranged on the semiconductor chip 110 and the molding layer 170” – Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Kim-096 into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Kim-096 in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, and Kim-096 do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Jin teaches
wherein the molding layer ([0030] – “a first molding portion 136, a second molding portion 144” – hereinafter ‘MDL’) comprises a second molding layer (144b – Fig. 4B – [0048] – “the second molding portion 144b completely covers the top surface of the first molding portion 136 and of the semiconductor chip 130”) covering at least a portion of the first semiconductor chip (130), the first molding layer (144 – Fig. 4B – [0030] – “a first molding portion 136”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Jin into Kim-780, Chang, and Kim-096.
An ordinary artisan would have been motivated to use the known technique of Jin in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, Kim-096, and Jin do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Han teaches
the first chip connection terminal (111 – Fig. 2B – [0029] – “The lower molding layer 117 may substantially, if not fully fill between each of the chip bumps 111”) on the first redistribution structure.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection terminal structure as taught by Han into Kim-780, Chang, Kim-096, and Jin.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, Kim-096, Jin, and Han do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Liao teaches
the second molding layer (328 – Fig. 3J – [0067] – “molding material (or molding compound) 328 can be formed over and around exposed surfaces of the die 320”) having a height ([0067] – “The thickness of the molding material 328 may be provided at any desired thickness, e.g., in the range of about 25 microns in thickness above the upper surface of the die 320 to about 500 microns in thickness above the upper surface of the die 320” – the die corresponds to the second redistribution layer) of 20 µm to 500 µm.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Liao into Kim-780, Chang, Kim-096, Jin, and Han.
An ordinary artisan would have been motivated to use the known technique of Liao in the manner set forth above to produce the predictable result of forming a protective feature around the semiconductor components.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 10, Kim-780 as modified by Chang, Kim-096, Jin, Han, and Liao, teaches claim 9 from which claim 10 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 9, wherein
a second width of the second redistribution structure (200) is less than a
first width of the first redistribution structure (110 – Fig. 1 shows this),
the first redistribution bonding pad (114) is at an upper portion of the first
redistribution structure (110 – Fig. 1 shows this), and
the second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) is at an upper portion of the second redistribution structure (200 – Fig. 1 shows this).
Regarding claim 11, Kim-780 as modified by Chang, Kim-096, Jin, Han, and Liao, teaches claim 9 from which claim 11 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 9,
wherein the bonding wire (220) is electrically and continuously connecting ([0026] – “The interposer substrate 200 and the first package substrate 110 may be electrically connected to each other through one or more connection terminals included in the semiconductor package 10a. For example, the interposer substrate 200 may be mounted on the first package substrate 110 in a wire bonding manner. In other words, the connection terminal included in the semiconductor package 10a may include the bonding wire 220 that connects the interposer substrate 200 to the first package substrate 110, and the interposer substrate 200 may be electrically connected to the first package substrate 110 through a bonding wire 220”) the second redistribution bonding pad (204) in the fan-out region (FO) and the first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) in the fan-out region (FO) to each other (114 – Fig. 1 – [0026] – “The bonding wire 220 may connect the fourth substrate pads 204 of the interposer substrate 200 to the second substrate pads 114 of the first package substrate 110”).
Regarding claim 12, Kim-780 as modified by Chang, Kim-096, Jin, Han, and Liao, teaches claim 9 from which claim 12 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim
9, wherein
the second redistribution structure (200) is on an upper surface of the first molding layer (40) and an upper surface of the first semiconductor chip (120),
the second redistribution structure (200) further comprises a third
connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) at an upper portion of the second redistribution structure (200), and
the molding layer (40) further comprises a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) exposing the third connection pad (202).
Regarding claim 13, Kim-780 as modified by Chang, Kim-096, Jin, Han, and Liao, teaches claim 9 from which claim 13 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 9,
further comprising a first connection pad (122 – Fig. 1 – [0025] – “terminals 122 (e.g., solder balls or solder bumps)”) at an upper portion of the first redistribution structure (110 – Fig. 1 shows this), and a second connection pad at a lower portion of the first redistribution structure, wherein,
the first connection pad (122) is connected to a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads 112”), and
the second connection pad is connected to a first external connection terminal.
However, in an analogous art, Han teaches
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) at a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}),
the second connection pad (108) is connected to a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108” – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection pad and first external connection terminal structures as taught by Han into Kim-780, Chang, Komatsu, Kim-096.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 6.
Claims 15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-780 in view of Chang, Kim-096, Jin, Kouda, Han, and Liao.
Regarding independent claim 15, Kim-780 teaches:
(Currently Amended) A semiconductor package (10a – Fig. 1 – [0021]
– “semiconductor package 10a”) comprising:
a first redistribution structure including a fan-in region and a fan-out
region, the fan-in region including at least two sides, and the fan-out region on each of the at least two sides of the fan-in region, the first redistribution structure comprising a first redistribution insulating layer, a first redistribution layer insulated by the first redistribution insulating layer, a first connection pad (112 – Fig. 1 – [0023] – “first substrate pads 112”) electrically connected to the first redistribution layer in the fan-in (Fig. 1 annotated, see below – hereinafter ‘FI’) region, and a first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer) in the fan-out region (Fig. 1 annotated, see below – hereinafter ‘FO’);
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a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’) in the fan-in (FI) region, the first semiconductor chip (120) electrically connected to the first connection pad (112) through a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads 112”), the first semiconductor chip (120) including at least two side surfaces (200a – Fig. 1 annotated, see below – [0040] – “side surfaces 200a of the first semiconductor chip 120”);
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120) in the fan-in (FI) region and the fan-out region (FO), the second redistribution structure comprising a second redistribution insulating layer, a second redistribution layer insulated by the second redistribution insulating layer, a third connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) electrically connected to the second redistribution layer in the fan-in (FI) region, and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) electrically connected to the second redistribution layer in the fan-out (FO) region;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204) in the fan-out (FO) region and the first redistribution bonding pad (114) in the fan-out (FO) region to each other (Fig. 1 shows this); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS) in the fan-in (FI) region and the fan-out (FO) region, the molding layer (130) having a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) exposing the third connection pad (202), wherein,
an upper width (Fig. 2 annotated, see below – hereinafter ‘OPW1’) of the connection hole (OP) is greater than a lower width (Fig. 2 annotated, see below – hereinafter ‘OPW2’) of the connection hole (OP),
the connection hole (OP) includes at least two sidewalls (Fig. 2 annotated, see below – hereinafter ‘SL1’ and ‘SL2’), and
the at least two sidewalls (SL1 and SL2) of the connection hole (OP) are inclined (Fig. 2 annotated shows this),
wherein the molding layer comprises a first molding layer on each of the at least two side surfaces of the first semiconductor chip in the fan-out region (FO), side surfaces of the first molding layer being coplanar with side surfaces of the second redistribution structure, and
wherein the molding layer comprises a second molding layer covering at least a portion of the first semiconductor chip, the first molding layer, the second redistribution structure (200), the bonding wire (220), and the first chip connection terminal on the first redistribution structure (FRS) in the fan-out region (FO), the second molding layer having a height of 20 µm to 500 µm from an upper surface of the second redistribution structure (200), and
wherein the height of the second molding layer from the upper surface of the second redistribution structure (200) is between 2 and 5 times a height of the bonding wire from the upper surface of the second redistribution structure (200).
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Kim-780 does not expressly disclose the other limitations of claim 15.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) including a fan-in region (Fig. 1O annotated, see below – hereinafter ‘FI’) and a fan-out (Fig. 1O annotated, see below – hereinafter ‘FO’) region, the fan-in (FI) region including at least two sides, and the fan-out (FO) region on each of the at least two sides of the fan-in (FI) region, the first redistribution structure (100) comprising a first redistribution insulating layer (106a – Fig. 1B – [0015] – “plurality of dielectric layers 106a”), a first redistribution layer (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”) insulated by the first redistribution insulating layer (106a),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”), a second redistribution layer (114b – Fig. 1G – [0030] – “plurality of conductive elements 114b”) insulated by the second redistribution insulating layer (114a),
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780 and Chang do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Kim-096 teaches
wherein the molding layer (170 – Fig. 1 – [0028] – “The molding layer 170”) comprises a first molding layer (170 – Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”) on each of the at least two side surfaces of the first semiconductor chip (110 - Fig. 1 – [0028] – “The molding layer 170 may cover a side surface of the semiconductor chip 110 and expose a bottom surface of the semiconductor chip 110”) in the fan-out region, side surfaces of the first molding layer (170) being coplanar with side surfaces of the second redistribution structure (120 – Fig. 1 – [0029] – “redistribution line structure 120 may be arranged on the semiconductor chip 110 and the molding layer 170” – Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Kim-096 into Kim-780, Chang, and Komatsu.
An ordinary artisan would have been motivated to use the known technique of Kim-096 in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, and Kim-096 do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Jin teaches
wherein the molding layer ([0030] – “a first molding portion 136, a second molding portion 144” – hereinafter ‘MDL’) comprises a second molding layer (144b – Fig. 4B – [0048] – “the second molding portion 144b completely covers the top surface of the first molding portion 136 and of the semiconductor chip 130”) covering at least a portion of the first semiconductor chip (130), the first molding layer (144 – Fig. 4B – [0030] – “a first molding portion 136”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Jin into Kim-780, Chang, and Kim-096.
An ordinary artisan would have been motivated to use the known technique of Jin in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, Kim-096, and Jin do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Kouda teaches
between 2 and 5 times a height of the bonding wire (16 – Fig. 12 – [16:7-9] – “the maximum loop height of the bonding wire pieces 16 from the bottom surface of the semiconductor chip 14 was practically limited to 120 microns or less” – the height includes the thickness of the semiconductor chip 14 that corresponds to the second redistribution structure, therefor the height above the upper surface of the chip is less than 120 microns or less).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bonding wire structure as taught by Kouda into Kim-780, Chang, Kim-096, and Jin.
An ordinary artisan would have been motivated to use the known technique of Kouda in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, Kim-096, Jin, and Kouda do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Han teaches
the first chip connection terminal (111 – Fig. 2B – [0029] – “The lower molding layer 117 may substantially, if not fully fill between each of the chip bumps 111”) on the first redistribution structure.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection terminal structure as taught by Han into Kim-780, Chang, Kim-096, Jin, and Kouda.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim-780, Chang, Kim-096, Jin, Kouda, and Han do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Liao teaches
the second molding layer (328 – Fig. 3J – [0067] – “molding material (or molding compound) 328 can be formed over and around exposed surfaces of the die 320”) having a height ([0067] – “The thickness of the molding material 328 may be provided at any desired thickness, e.g., in the range of about 25 microns in thickness above the upper surface of the die 320 to about 500 microns in thickness above the upper surface of the die 320” – the die corresponds to the second redistribution layer) of 20 µm to 500 µm.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Liao into Kim-780, Chang, Kim-096, Jin, Kouda, and Han.
An ordinary artisan would have been motivated to use the known technique of Liao in the manner set forth above to produce the predictable result as stated above in claim 9.
Regarding claim 17, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, Han, and Liao, teaches claim 15 from which claim 17 depends. Kim-780 further teaches
(Previously Presented) The semiconductor package of claim 15,
wherein the bonding wire (220) is electrically and continuously connecting ([0026] – “The interposer substrate 200 and the first package substrate 110 may be electrically connected to each other through one or more connection terminals included in the semiconductor package 10a. For example, the interposer substrate 200 may be mounted on the first package substrate 110 in a wire bonding manner. In other words, the connection terminal included in the semiconductor package 10a may include the bonding wire 220 that connects the interposer substrate 200 to the first package substrate 110, and the interposer substrate 200 may be electrically connected to the first package substrate 110 through a bonding wire 220”) the second redistribution bonding pad (204) in the fan-out region (FO) and the first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) in the fan-out region (FO) to each other (114 – Fig. 1 – [0026] – “The bonding wire 220 may connect the fourth substrate pads 204 of the interposer substrate 200 to the second substrate pads 114 of the first package substrate 110”).
Regarding claim 18, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, Han, and Liao, teaches claim 15 from which claim 18 depends. Kim-780, Kim-096, Jin, Kouda, and Liao, do not expressly disclose the limitations of claim 18.
However, in an analogous art, Han teaches
(Original) The semiconductor package of claim 15, further comprising:
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) arranged
on a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}) in the fan-in (Fig. 1B annotated, see below – hereinafter ‘FI’) region and the fan-out (Fig. 1B annotated, see below – hereinafter ‘FO’) region, the second connection pad (108) electrically connected to the first redistribution layer (101); and
a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108”) connected to the second connection pad (108 – Fig. 1B shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection pad structure as taught by Han into Kim-780, Kim-096, Jin, Kouda, and Liao.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 6.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-780 in view of Chang, Kim-096, Jin, Kouda, Han, Liao, and Kim et al. (US 20160086834 A1 – hereinafter Kim-834).
Regarding claim 16, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, Han, and Liao, teaches claim 15 from which claim 16 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 15, further
comprising a plurality of third connection pads (202 – Fig. 1 shows a plurality),
wherein the connection hole is configured to expose the plurality of third connection pads.
Kim-780, Chang, Kim-096, Jin, Kouda, Han, and Liao do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Kim-834 teaches
wherein the connection hole (150 – Fig. 2D – [0056] – “one stack hole 150” – configured for one hole to receive multiple connection terminals)) is configured to expose the plurality of third connection pads (12 – Fig. 2D – [0060] – “solder balls 22”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection hole and pad structures as taught by Kim-834 into Kim-780, Chang, Kim-096, Jin, Kouda, Han, and Liao.
An ordinary artisan would have been motivated to use the known technique of Kim-834 in the manner set forth above to produce the predictable result to connect [0056] – “the first and second semiconductor packages 10 and 20 so the first and second semiconductor packages 10 and 20 may be vertically stacked in a single stack hole 150.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 20, Kim-780 as modified by Chang, Kim-096, Jin, Kouda, Han, and Liao, teaches claim 15 from which claim 20 depends. Kim-780 further teaches
(Original) The semiconductor package of claim 15, wherein the first
redistribution structure (FRS), the first semiconductor chip (120), the second redistribution structure (200), the bonding wire (220), and the molding layer (40) define a lower semiconductor package (100 – Fig. 1 – [0044] – “lower package 100”),
the semiconductor package (10a) further comprises an upper semiconductor package (300 – Fig. 1 – [0044] – “upper package 300”) on the molding layer (40), wherein the upper semiconductor package (300) comprises a wire substrate (310 – Fig. 1 – {[0044] – “upper package 300 may include a second package substrate 310”}, {[0045] – “second package substrate 310 may be a printed circuit board (PCB) provided with signal patterns. In some example embodiments, the second package substrate 310 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked”}), a second semiconductor chip (320 – Fig. 1 – [0044] – “second semiconductor chip 320”) on the wire substrate (310), an upper molding layer (330 – Fig.1 – [0044] – “second molding portion 330”) covering at least a portion of the second semiconductor chip (320) on the wire substrate (310), and a second external connection terminal (305 – Fig. 1 – [0046] – “connection terminals 305”) on a lower portion of the wire substrate (310), and
the second external connection terminal (305) is in the connection hole and electrically connected to the third connection pad (202 – Fig. 1 shows this).
Kim-780, Chang, Kim-096, Jin, Kouda, Liao, and Han do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Kim-834 teaches
the connection hole (150 – configured for one hole to receive multiple connection terminals).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection hole structures as taught by Kim-834 into Kim-780, Chang, Kim-096, Jin, Kouda, Liao, and Han.
An ordinary artisan would have been motivated to use the known technique of Kim-834 in the manner set forth above to produce the predictable result as stated above in claim 16.
Pertinent Art
For the benefits of the Applicant, US 20180122731 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the molding layer structure.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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