DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5, 7-13, 14-15, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210183780 A1 – hereinafter Kim-780) in view of Chang et al. (US 20200006290 A1 – hereinafter Chang).
Regarding independent claim 1, Kim-780 teaches:
A semiconductor package (10a – Fig. 1 – [0021] – “semiconductor
package 10a”) comprising:
a first redistribution structure comprising a first redistribution layer and a first
redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”), the first redistribution bonding pad (114) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer);
a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’);
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120), the second redistribution structure comprising a second redistribution insulating layer and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”), the second redistribution layer electrically connected to the second redistribution layer;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204) and the first redistribution bonding pad (114) to each other (Fig. 1 shows this); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS).
Kim-780 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) comprising a first redistribution layer (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”),
the second redistribution layer (114a) electrically connected to the second redistribution layer (114b).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result of [0006] – “the simplicity of the manufacturing process of the package structure may be realized, thereby reducing the manufacturing cost.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, Kim-780 as modified by Chang, teaches claim 1 from which claim 2 depends. Kim-780 further teaches
wherein a second width of the
second redistribution structure (200) is less than a first width of the first redistribution structure (110 – Fig. 1 shows this).
Regarding claim 3, Kim-780 as modified by Chang, teaches claim 1 from which claim 3 depends. Kim-780 further teaches
wherein
the first redistribution bonding pad (114) is at an upper portion of the first
redistribution structure (110 – Fig. 1 shows this), and
the second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) is at an upper portion of the second redistribution structure (200 – Fig. 1 shows this).
Regarding claim 4, Kim-780 as modified by Chang, teaches claim 1 from which claim 4 depends. Kim-780 further teaches
wherein
the first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip
120”) includes at least two side surfaces (200a – Fig. 1 annotated, see below – [0040] – “side surfaces 200a of the first semiconductor chip 120”), and
the molding layer (Fig. 1 annotated, see below – hereinafter ‘40’) comprises a
first molding layer (40) on each of the at least two side surfaces (200a) of the first semiconductor chip (120), and a second molding layer (130) covering at least a portion of the first semiconductor chip (120), and
the first molding layer (40), the second redistribution structure (200), and the bonding wire (220) are on the first redistribution structure (110).
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Regarding claim 5, Kim-780 as modified by Chang, teaches claim 4 from which claim 5 depends. Kim-780 further teaches
wherein the second redistribution structure (200) is on an upper
surface of the first molding layer (40) and an upper surface of the first semiconductor chip (120).
Regarding claim 7, Kim-780 as modified by Chang, teaches claim 1 from which claim 7 depends. Kim-780 further teaches
further comprising:
a third connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) at an
upper portion of the second redistribution structure (200); and
a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) in the molding layer (130), the connection hole (OP) exposing the third connection pad (202).
Regarding claim 8, Kim-780 as modified by Chang, teaches claim 1 from which claim 8 depends. Kim-780 further teaches
further comprising:
a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads
112”) arranged on a lower portion of the first
semiconductor chip (ch1) (kim (120) , the first chip connection terminal (22 – fig 1) (kim (112) connected to the first redistribution structure (kim (110 – Fig. 1 shows this); and
an underfill layer (24) (kim (124 – Fig. 1 – [0025] – “flux 124” – this corresponds to an underfill layer) supporting the first chip connection terminal (22) (kim (112 – Fig. 1 shows this), the underfill layer (kim (124) on the lower portion of the first semiconductor chip (kim (120 – Fig. 1 shows this).
Regarding independent claim 9, Kim-780 teaches:
A semiconductor package (10a – Fig. 1 – [0021] – “semiconductor
package 10a”) comprising:
a first redistribution structure including a fan-in region and a fan-out region, the
fan-in region including at least two sides, and the fan-out region on each of the at least two sides of the fan-in region, the first redistribution structure comprising a first redistribution insulating layer, a first redistribution layer insulated by the first redistribution insulating layer, and a first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer), the first redistribution bonding pad (114) on an upper portion of the first redistribution insulating layer (110) in the fan-out region (Fig. 1 annotated, see below – hereinafter ‘FO’);
a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’) in the fan-in (FI) region;
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120) in the fan-in (FI) region and the fan-out region (FO), the second redistribution structure comprising a second redistribution insulating layer, a second redistribution layer insulated by the second redistribution insulating layer, and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) electrically connected to the second redistribution layer, the second redistribution layer on an upper portion of the second redistribution insulating layer in the fan-out region;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204) in the fan-out (FO) region and the first redistribution bonding pad (114) in the fan-out (FO) region to each other (Fig. 1 shows this); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (110) in the fan-in (FI) region and the fan-out (FO) region.
Kim-780 does not expressly disclose the other limitations of claim 9.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) including a fan-in region (Fig. 1O annotated, see below – hereinafter ‘FI’) and a fan-out (Fig. 1O annotated, see below – hereinafter ‘FO’) region, the fan-in (FI) region including at least two sides, and the fan-out (FO) region on each of the at least two sides of the fan-in (FI) region, the first redistribution structure (100) comprising a first redistribution insulating layer (106a – Fig. 1B – [0015] – “plurality of dielectric layers 106a”), a first redistribution layer (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”) insulated by the first redistribution insulating layer (106a),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”), a second redistribution layer (114b – Fig. 1G – [0030] – “plurality of conductive elements 114b”) insulated by the second redistribution insulating layer (114a), and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) electrically connected to the second redistribution layer (114b), the second redistribution layer (114b) on an upper portion of the second redistribution insulating layer (114a – Fig. 1G shows this) in the fan-out region (FO).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 10, Kim-780 as modified by Chang, teaches claim 9 from which claim 10 depends. Kim-780 further teaches
wherein
a second width of the second redistribution structure (200) is less than a
first width of the first redistribution structure (110 – Fig. 1 shows this),
the first redistribution bonding pad (114) is at an upper portion of the first
redistribution structure (110 – Fig. 1 shows this), and
the second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) is at an upper portion of the second redistribution structure (200 – Fig. 1 shows this).
Regarding claim 11, Kim-780 as modified by Chang, teaches claim 9 from which claim 11 depends. Kim-780 further teaches
wherein
the first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip
120”) includes at least two side surfaces (200a – Fig. 1 annotated, see below – [0040] – “side surfaces 200a of the first semiconductor chip 120”),
the molding layer (Fig. 1 annotated, see below – hereinafter ‘40’) comprises a first molding layer (40) on each of the at least two side surfaces (200a) of
the first semiconductor chip (120) in the fan-out (FO) region, and
the molding layer (40) comprises a second molding layer (130) covering at least a portion of the first semiconductor chip (120), the first molding layer (40), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS) in the fan-in (FI) region and the fan-out (FO) region.
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Regarding claim 12, Kim-780 as modified by Chang, teaches claim 11 from which claim 12 depends. Kim-780 further teaches
wherein
the second redistribution structure (200) is on an upper surface of the first
molding layer (40) and an upper surface of the first semiconductor chip (120),
the second redistribution structure (200) further comprises a third
connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) at an upper portion of the second redistribution structure (200), and
the molding layer (40) further comprises a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) exposing the third connection pad (202).
Regarding claim 14, Kim-780 as modified by Chang, teaches claim 9 from which claim 14 depends. Kim-780 further teaches
further comprising:
a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads
112”) arranged on a lower portion of the first semiconductor chip (120), the first chip connection terminal (112) connected to the first redistribution structure (110 – Fig. 1 shows this); and
an underfill layer (124 – Fig. 1 – [0025] – “flux 124” – this corresponds to an
underfill layer) arranged on the lower portion of the first semiconductor chip (120 – Fig. 1 shows this), the underfill layer (124) supporting the first chip connection terminal (112 – Fig. 1 shows this).
Regarding independent claim 15, Kim-780 teaches:
A semiconductor package (10a – Fig. 1 – [0021] – “semiconductor
package 10a”) comprising:
a first redistribution structure including a fan-in region and a fan-out region, the
fan-in region including at least two sides, and the fan-out region on each of the at least two sides of the fan-in region, the first redistribution structure comprising a first redistribution insulating layer, a first redistribution insulated by the first redistribution insulating layer, a first connection pad (122 – Fig. 1 – [0025] – “terminals 122 (e.g., solder balls or solder bumps)”) electrically connected to the first redistribution layer in the fan-in (Fig. 1 annotated, see below – hereinafter ‘FI’) region, and a first redistribution bonding pad (114 – Fig. 1 – [0053] – “pads 114”) electrically connected to the first redistribution layer (110 – Fig. 1 – [0023] – “first package substrate 110 may have a multi-layered structure including insulating and interconnection layers, which are alternatingly stacked” – this describes a redistribution layer) in the fan-out region (Fig. 1 annotated, see below – hereinafter ‘FO’);
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a first semiconductor chip (120 – Fig. 1 – [0025] – “first semiconductor chip 120”) on the first redistribution structure (Fig. 1 – [0022] – “lower package 100” – this describes a first redistribution structure, hereinafter ‘FRS’) in the fan-in (FI) region, the first semiconductor chip (120) electrically connected to the first connection pad (122) through a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads 112”);
a second redistribution structure (200 – Fig. 1 – [0026] – “substrate 200 may include a printed circuit board (PCB). The interposer substrate 200 may be formed of the same material (e.g., a same insulating material) as the first package substrate 110” – this describes a redistribution structure) on the first semiconductor chip (120) in the fan-in (FI) region and the fan-out region (FO), the second redistribution structure comprising a second redistribution insulating layer, a second redistribution layer insulated by the second redistribution insulating layer, a third connection pad (202 – Fig. 1 – [0026] – “substrate pads 202”) electrically connected to the second redistribution layer in the fan-in (FI) region, and a second redistribution bonding pad (204 – Fig. 1 – [0026] – “substrate pads 204”) electrically connected to the second redistribution layer in the fan-out (FO) region;
a bonding wire (220 – Fig. 1 – [0026] – “bonding wire 220”) electrically connecting the second redistribution bonding pad (204) in the fan-out (FO) region and the first redistribution bonding pad (114) in the fan-out (FO) region to each other (Fig. 1 shows this); and
a molding layer (130 – Fig. 1 – [0022] – “first molding portion 130”) covering at least a portion of the first semiconductor chip (120), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS) in the fan-in (FI) region and the fan-out (FO) region, the molding layer (130) having a connection hole (OP – fig. 1 – [0043] – “a plurality of openings OP”) exposing the third connection pad (202), wherein,
an upper width (Fig. 2 annotated, see below – hereinafter ‘OPW1’) of the connection hole (OP) is greater than a lower width (Fig. 2 annotated, see below – hereinafter ‘OPW2’) of the connection hole (OP),
the connection hole (OP) includes at least two sidewalls (Fig. 2 annotated, see below – hereinafter ‘SL1’ and ‘SL2’), and
the at least two sidewalls (SL1 and SL2) of the connection hole (OP) are inclined (Fig. 2 annotated shows this).
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Kim-780 does not expressly disclose the other limitations of claim 15.
However, in an analogous art, Chang teaches
a first redistribution structure (100 – Fig. 1O – [0039] – “first package 100” –
this is a redistribution structure) including a fan-in region (Fig. 1O annotated, see below – hereinafter ‘FI’) and a fan-out (Fig. 1O annotated, see below – hereinafter ‘FO’) region, the fan-in (FI) region including at least two sides, and the fan-out (FO) region on each of the at least two sides of the fan-in (FI) region, the first redistribution structure (100) comprising a first redistribution insulating layer (106a – Fig. 1B – [0015] – “plurality of dielectric layers 106a”), a first redistribution layer (106B – Fig. 1B – [0015] – “plurality of conductive elements 106b”) insulated by the first redistribution insulating layer (106a),
the second redistribution structure (114 – Fig. 1O – [0029] – “second redistribution layer 114”) comprising a second redistribution insulating layer (114a – Fig. 1G – [0030] – “plurality of dielectric layers 114a”), a second redistribution layer (114b – Fig. 1G – [0030] – “plurality of conductive elements 114b”) insulated by the second redistribution insulating layer (114a).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second redistribution structures as taught by Chang into Kim-780.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 17, Kim-780 as modified by Chang, teaches claim 15 from which claim 17 depends. Kim-780 further teaches
further comprising an underfill layer (124 – Fig. 1 – [0025] – “flux 124”
– this corresponds to an underfill layer) arranged on a lower portion of the first semiconductor chip (120), the underfill layer (124) supporting the first chip connection terminal (112 – Fig. 1 shows this).
Regarding claim 19, Kim-780 as modified by Chang, teaches claim 15 from which claim 19 depends. Kim-780 further teaches
wherein
the first semiconductor chip (120) includes at least two side surfaces (200a
– Fig. 1 annotated, see below – [0040] – “side surfaces 200a of the first semiconductor chip 120”), and
the molding layer (Fig. 1 annotated, see below – hereinafter ‘40’) comprises a
first molding layer (40) on each of the at least two side surfaces (200a) of the first semiconductor chip (120) in the fan-out (FO) region, and a second molding layer (130) covering at least a portion of the first semiconductor chip (120), the first molding layer (40), the second redistribution structure (200), and the bonding wire (220) on the first redistribution structure (FRS) in the fan-in (FI) region and the fan-out (FO) region.
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Claims 6, 7, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-780 in view of Chang and Han et al. (US 20140346667 A1 – hereinafter Han).
Regarding claim 6, Kim-780 as modified by Chang, teaches claim 1 from which claim 6 depends. Kim-780 further teaches
further comprising a first
connection pad (122 – Fig. 1 – [0025] – “terminals 122 (e.g., solder balls or solder bumps)”) at an upper portion of the first redistribution structure (110 – Fig. 1 shows this), and a second connection pad at a lower portion of the first redistribution structure, wherein,
the first connection pad (122) is connected to a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads 112”), and
the second connection pad is connected to a first external connection terminal.
Kim-780 and Chang does not expressly disclose the other limitations of claim 6.
However, in an analogous art, Han teaches
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) at a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}),
the second connection pad (108) is connected to a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108” – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection pad and first external connection terminal structures as taught by Han into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result of [0004] – “A package on package (PoP) technology where a package is stacked on the other package was proposed to laminate a plurality of semiconductor chips on each other and to realize a high density chip lamination. In the PoP technology, each of the semiconductor chips may pass a test. As a result, a defect rate for the final products may decrease. These PoP type semiconductor packages may be used to satisfy miniaturization of electronic portable devices and functional diversification of mobile products.”
Regarding claim 13, Kim-780 as modified by Chang, teaches claim 9 from which claim 13 depends. Kim-780 further teaches
further comprising a first
connection pad (122 – Fig. 1 – [0025] – “terminals 122 (e.g., solder balls or solder bumps)”) at an upper portion of the first redistribution structure (110 – Fig. 1 shows this), and a second connection pad at a lower portion of the first redistribution structure, wherein,
the first connection pad (122) is connected to a first chip connection terminal (112 – Fig. 1 – [0023] – “first substrate pads 112”), and
the second connection pad is connected to a first external connection terminal.
Kim-780 and Chang does not expressly disclose the other limitations of claim 13.
However, in an analogous art, Han teaches
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) at a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}),
the second connection pad (108) is connected to a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108” – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection pad and first external connection terminal structures as taught by Han into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 6.
Regarding claim 18, Kim-780 as modified by Chang, teaches claim 5 from which claim 18 depends. Kim-780 and Chang does not expressly disclose the limitations of claim 18.
However, in an analogous art, Han teaches
further comprising:
a second connection pad (108 – Fig. 1B – [0028] – “Ball lands 108”) arranged
on a lower portion of the first redistribution structure (101 – Fig. 1B – {[0028] – “Ball lands 108 may be disposed at a bottom surface of the lower package substrate 101”}, {[0028] – “The lower package substrate 101 may be a printed circuit board (PCB) including multiple layers. The lower package substrate 101 may include multiple insulating layers 103. An inner interconnection 105 may be disposed between the insulating layers 103”}) in the fan-in (Fig. 1B annotated, see below – hereinafter ‘FI’) region and the fan-out (Fig. 1B annotated, see below – hereinafter ‘FO’) region, the second connection pad (108) electrically connected to the first redistribution layer (101); and
a first external connection terminal (121 – Fig. 1B – [0028] – “External terminals 121 may be attached to the ball lands 108”) connected to the second connection pad (108 – Fig. 1B shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection pad and first external connection terminal structures as taught by Han into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Han in the manner set forth above to produce the predictable result as stated above in claim 6.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-780 in view of Chang and Kim et al. (US 20160086834 A1 – hereinafter Kim-834).
Regarding claim 16, Kim-780 as modified by Chang, teaches claim 15 from which claim 16 depends. Kim-780 further teaches
further comprising a plurality of third connection pads (202 – Fig. 1
shows a plurality),
wherein the connection hole (150 – Fig. – [0056] – “one stack hole 150” – configured for one hole to receive multiple connection terminals)) is configured to expose the plurality of third connection pads (12 – Fig. 2D – [0060] – “solder balls 22”).
Kim-780 and Chang does not expressly disclose the other limitations of claim 13.
However, in an analogous art, Kim-834 teaches
wherein the connection hole (150 – Fig. 2D – [0056] – “one stack hole 150” – configured for one hole to receive multiple connection terminals)) is configured to expose the plurality of third connection pads (12 – Fig. 2D – [0060] – “solder balls 22”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection hole and pad structures as taught by Kim-834 into Kim-780 and Chang.
An ordinary artisan would have been motivated to use the known technique of Kim-834 in the manner set forth above to produce the predictable result to connect [0056] – “the first and second semiconductor packages 10 and 20 so the first and second semiconductor packages 10 and 20 may be vertically stacked in a single stack hole 150.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897