Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 20th, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-15 are objected to because of the following informalities:
Claims 1 and 15 recite “a second time delay, different to the first time delay,” which should be changed to “a second time delay, different from the first time delay.”
Claim 5 recites “the first and the second resistive elements,” which should be changed to “the first and the second resistive memory elements.”
Claim 12 should be changed from “the first capacitor being configured to be discharged based on the first input signal of on one or more outputs of the first shift register” to “…based on the first input signal of [[on]] one or more outputs of the first shift register”
Claim 11 should be changed from "the second synapse circuit further comprises… the second comparator" to “the second synapse circuit further comprises… the second comparator circuit".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 15 recite that “a second synapse circuit configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal,” and further recites “generat[ing] a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal” in lines 7-10. There is insufficient antecedent basis for this limitation in the claim. It is unclear which signal is weighted to produce the second output signal, rendering the claim indefinite. The “delayed second input signal" is interpreted as the signal that is delayed by the second synapse circuit (i.e., whichever of the first input signal or the second input signal is applied to and delayed by the second synapse circuit), and the second output signal is interpreted as being generated by applying the second weight to that delayed signal.
The terms "high resistance state" and "low resistance state" in claims 5-6 are relative terms which renders the claim indefinite. The terms "high resistance state" and "low resistance state" are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The terms are not defined by the claims, and the specification does not provide any standard (e.g., a resistance value, range, or threshold) for ascertaining the requisite degree that distinguishes a "high" resistance state from a "low" resistance state. While the specification refers generally to a high resistive state (HRS) and a low resistive state (LRS) (paragraphs 20, 88, and 91), it sets forth no measurable boundary separating the two. Accordingly, one of ordinary skill in the art would not be reasonably able to interpret the scope of the claims, rendering them indefinite. The term "high resistance state" is interpreted as a resistance state higher than another resistance state of the same or a comparable resistive element, and "low resistance state" is interpreted as a resistance state lower than another resistance state.
Claims 6 and 8 recite the limitations "the third and the fourth resistive elements" in lines 1-2. There is insufficient antecedent basis for these limitations in the claims. Claims 6 and 8 depend on claim 1, which does not recite a third or a fourth resistive element. The “third and the fourth resistive elements" are interpreted as the resistive memory elements that store/apply the first and second weights.
Claim 12 recites the limitation "the second input signal." There is insufficient antecedent basis for this limitation in the claim. See Claims 1 and 15 indefiniteness for the same reasoning. The “second input signal" is interpreted as the input signal applied to the second synapse circuit.
Claims 2-14 are rejected under 35 U.S.C. 112(b) due to their dependence, either directly or indirectly, on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (US 20170221558 A1).
Regarding claim 1,
Hu teaches [a] neural network comprising (Paragraph 13 of Hu, "…the memristor apparatuses disclosed herein may provide a hardware platform to implement an artificial neural network, such as the spiking neural network"
Hu teaches a hardware spiking neural network formed from a plurality of memristor apparatuses.):
a first synapse circuit (Fig. 3A, memristor apparatus 300) configured to apply a first time delay to a first input signal using a first resistive memory (Fig. 3A, first memristor 302) element (Paragraphs 27-29, “With reference first to FIG. 3A, the apparatus 300 is depicted as including a first memristor 302, a second memristor 304, a transistor 306, and a capacitor 308… a first input voltage 310 may be supplied to an input of the first memristor 302… The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308.”
Hu's apparatus 300 of Fig. 3A applies the first input voltage 310 to its first memristor 302, and the time for that voltage to reach the transistor gate is set by the resistance of the first memristor 302. Apparatus 300 corresponds to the first synapse circuit and first memristor 302 corresponds to the first resistive memory element that applies the first-time delay.)
and to generate a first output signal (Fig. 3A, output signal 314) at an output of the first synapse circuit by applying a first weight to the delayed first input signal (Paragraphs 51-52, “an output signal 314 corresponding to the supply voltage following transmission of the supply voltage through the second memristor 304 may also be provided to the reader 408. The reader 408 may also be provided with the voltage level of the supply voltage supplied to the supply of the transistor 306… the reader 408 may determine the start of the time window of the application of the input voltage based upon a time at which the input signal 410 supplied into the first memristor 302 was received… the output signal 314 may correspond to the resistance level of the first memristor 302 because that resistance level delays the time at which the supply voltage is provided to the second memristor 304.”, Paragraphs 29-30, “The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308… the higher the resistance level of the first memristor 302 , the longer it will take for the capacitor 308 to be charged… the voltage level of the reading signal may be reduced by the resistance level of the second memristor 304. In this regard, the resistance level of the second memristor 304 may apply a weight to the reading signal…”, Paragraph 58, “the second memristor 304 may output an output signal 314 that includes a delayed and weighted signal 712.”
Hu teaches that once the delayed voltage turns on transistor 306, the resulting reading signal passes through the second memristor 304, whose resistance applies a weight, producing delayed and weighted output signal 314. Output signal 314 corresponds to the first output signal generated by applying the first weight to the delayed first input signal.),
the first synapse circuit further comprises a first capacitor coupled to the first resistive memory element and configured to introduce the first time delay (Paragraph 11, "Each of the memristor apparatuses includes a first memristor and a second memristor, with a transistor positioned between the first memristor and the second memristor, and with a capacitor position between the first memristor and the transistor.”, Paragraphs 28-29, "the output of the first memristor 302 may be connected to the capacitor 308 and the gate of the transistor 306…The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308… the higher the resistance level of the first memristor 302, the longer it will take for the capacitor 308 to be charged."
Hu teaches that the output of first memristor 302 is connected to capacitor 308, and that the higher the resistance of first memristor 302, the longer it takes capacitor 308 to charge and release charge to the gate. Capacitor 308 is coupled to the first memristor 302 and sets the charge interval. This corresponds to the first capacitor introducing the first-time delay.);
and a second synapse circuit (Fig. 4A, a second one of the apparatuses 300 of crossbar array 400) configured to apply a second time delay, different to the first time delay to the first input signal, or to a second input signal, using a second resistive memory element (Paragraphs 36 and 38-39, “FIGS. 4A and 4B, there are respectively shown diagrams of crossbar arrays 400, 400′ that each includes the apparatuses 300, 300′ formed at junctions of the crossbar arrays 400… the crossbar array 400 includes a plurality of apparatuses 300, a plurality of first input lines 402, a plurality of second input lines 404, and a plurality of third input lines 406… The first input lines 402 are… connected to the inputs of the first memristors 302 and the second input lines 404 are … connected to the inputs (sources) of the transistors 306… the third input lines 406 are … connected to the outputs of the second memristors 304… each of the apparatuses 300 may be individually addressed by applying voltage to selected ones of the first and second input lines 402, 404.”, Paragraph 49, “for the same capacitance level, the higher the resistance level to which the first memristor 302 has been set, the longer the delay.”, Paragraphs 27-29, “With reference first to FIG. 3A, the apparatus 300 is depicted as including a first memristor 302, a second memristor 304, a transistor 306, and a capacitor 308… a first input voltage 310 may be supplied to an input of the first memristor 302… The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308.”
Hu discloses that crossbar array 400 is formed of a plurality of individually addressable apparatuses 300 where each is structurally identical to each other and operates in the same manner as the apparatus of Fig. 3A. A second apparatus 300 of the plurality of apparatuses therefore corresponds to the second synapse circuit and its first memristor 302 corresponds to the second resistive memory element. Since each first memristor 302 is independently programmable to one of a plurality of available delay levels and each apparatus produces its own output, the second apparatus is programmed to a different resistance level and thereby produces a second time delay different from the other synapse circuits (apparatuses 300).)
and to generate a second output signal (Fig. 3A, output signal 314) at an output of the second synapse circuit by applying a second weight to the delayed second input signal, (Paragraph 36, “With reference now to FIGS. 4A and 4B, there are respectively shown diagrams of crossbar arrays 400, 400′ that each includes the apparatuses 300, 300′ formed at junctions of the crossbar arrays 400…”, Paragraph 30, “the voltage level of the reading signal may be reduced by the resistance level of the second memristor 304. In this regard, the resistance level of the second memristor 304 may apply a weight to the reading signal…”, Paragraph 58, “the second memristor 304 may output an output signal 314 that includes a delayed and weighted signal 712.”
As set forth above for the first synapse circuit, each apparatus 300 generates its output signal 314 by passing the delayed reading signal through its second memristor 304 where the resistance applies a weight to that signal. Hu's crossbar array 400 is formed of a plurality of structurally identical apparatuses 300 arranged at the junctions of the array (Paragraph 36), and the second apparatus operates in the identical manner as the first apparatus described above. It applies through its own second memristor 304 and its second weight to its own delayed second input signal to produce its own delayed and weighted output signal 314.)
the second synapse circuit further comprises a second capacitor coupled to the second resistive memory element and configured to introduce the second time delay. (Paragraph 38, "the crossbar array 400 may include any number of apparatuses 300, first input lines 402, second input lines 404, and third input lines 406. The first input lines 402 are depicted as being connected to the inputs of the first memristors 302 and the second input lines 404 are depicted as being connected to the inputs (sources) of the transistors 306. In addition, the third input lines 406 are depicted as being connected to the outputs of the second memristors 304." Paragraph 11, "Each of the memristor apparatuses includes a first memristor and a second memristor, with a transistor positioned between the first memristor and the second memristor, and with a capacitor position between the first memristor and the transistor.", Paragraph 49, "for the same capacitance level, the higher the resistance level to which the first memristor 302 has been set, the longer the delay."
Since each apparatus 300 is identical, the second apparatus includes its own capacitor 308 coupled to its first memristor 302. The delay is set by that memristor's resistance and the capacitance. This capacitor corresponds to the second capacitor introducing the second time delay.)
Regarding claim 2,
Hu teaches the first weight is a function of the resistance of a third resistive memory element; (Paragraph 30 of Hu, "the voltage level of the reading signal may be reduced by the resistance level of the second memristor 304. In this regard, the resistance level of the second memristor 304 may apply a weight to the reading signal…", Paragraph 12, "the second memristor may be programmed to have a predetermined resistance level, in which the resistance level corresponds to a data."
The weight applied within the first apparatus is a function of the resistance of that apparatus's second memristor. The second memristor of the first apparatus corresponds to the third resistive memory element.)
and the second weight is a function of the resistance of a fourth resistive memory element. (Paragraph 30, "the resistance level of the second memristor 304 may apply a weight to the reading signal…" Paragraph 39, "…to program the first memristors 302 and the second memristors 304 in selected ones of the apparatuses 300."
The weight applied within the second apparatus is a function of the resistance of that apparatus's second memristor. The second memristor of the second apparatus corresponds to the fourth resistive memory element.)
Regarding claim 5,
Hu teaches wherein the first and the second resistive elements are programmed to have a high resistance state (Paragraph 24 of Hu, “the memristor 200 may be programmed to have one of a plurality of distinct resistance levels… the switching element 206 may be programmed to have a higher resistance level through application of an earlier current or voltage level.", Paragraph 29, “the higher the resistance level of the first memristor 302 , the longer it will take for the capacitor 308 to be charged and thus, the longer it will take for the capacitor 308 to release a charge to the gate of the transistor 306.”
Under the relative-term interpretation, "high resistance state" reads as a resistance higher than another available state of the same element, which is what Hu discloses.)
Regarding claim 6,
Hu teaches wherein the third and the fourth resistive elements are programmed to have a low resistance state (Paragraph 24 of Hu, “the memristor 200 may be programmed to have one of a plurality of distinct resistance levels.”, Paragraph 11, “the capacitor may reach the certain level of capacitance relatively faster when the resistance level of the first memristor is lower as compared to when the resistance level of the first memristor is higher.”
Under the relative-term interpretation, "low resistance state" reads as a resistance lower than another available state, which is what Hu discloses.)
Regarding claim 15,
Hu teaches [a] method comprising: applying, by a first synapse circuit (Fig. 3A, memristor apparatus 300), a first time delay to a first input signal using first resistive memory (Fig. 3A, first memristor 302) element (Paragraphs 27-29, “With reference first to FIG. 3A, the apparatus 300 is depicted as including a first memristor 302, a second memristor 304, a transistor 306, and a capacitor 308… a first input voltage 310 may be supplied to an input of the first memristor 302… The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308.”
Hu's apparatus 300 of Fig. 3A applies the first input voltage 310 to its first memristor 302, and the time for that voltage to reach the transistor gate is set by the resistance of the first memristor 302. Apparatus 300 corresponds to the first synapse circuit and first memristor 302 corresponds to the first resistive memory element that applies the first time delay.),
the first synapse circuit comprising a first capacitor coupled to the first resistive memory element and configured to introduce the first time delay (Paragraph 11, "Each of the memristor apparatuses includes a first memristor and a second memristor, with a transistor positioned between the first memristor and the second memristor, and with a capacitor position between the first memristor and the transistor.”, Paragraphs 28-29, "the output of the first memristor 302 may be connected to the capacitor 308 and the gate of the transistor 306…The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308… the higher the resistance level of the first memristor 302, the longer it will take for the capacitor 308 to be charged."
Hu teaches that the output of first memristor 302 is connected to capacitor 308, and that the higher the resistance of first memristor 302, the longer it takes capacitor 308 to charge and release charge to the gate. Capacitor 308 is coupled to the first memristor 302 and sets the charge interval. This corresponds to the first capacitor introducing the first time delay),
generating a first output signal (Fig. 3A, output signal 314) at an output of the first synapse circuit by applying a first weight to the delayed first input signal (Paragraphs 51-52, “an output signal 314 corresponding to the supply voltage following transmission of the supply voltage through the second memristor 304 may also be provided to the reader 408. The reader 408 may also be provided with the voltage level of the supply voltage supplied to the supply of the transistor 306… the reader 408 may determine the start of the time window of the application of the input voltage based upon a time at which the input signal 410 supplied into the first memristor 302 was received… the output signal 314 may correspond to the resistance level of the first memristor 302 because that resistance level delays the time at which the supply voltage is provided to the second memristor 304.”, Paragraphs 29-30, “The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308… the higher the resistance level of the first memristor 302 , the longer it will take for the capacitor 308 to be charged… the voltage level of the reading signal may be reduced by the resistance level of the second memristor 304. In this regard, the resistance level of the second memristor 304 may apply a weight to the reading signal…”, Paragraph 58, “the second memristor 304 may output an output signal 314 that includes a delayed and weighted signal 712.”
Hu teaches that once the delayed voltage turns on transistor 306, the resulting reading signal passes through the second memristor 304, whose resistance applies a weight, producing delayed and weighted output signal 314. Output signal 314 corresponds to the first output signal generated by applying the first weight to the delayed first input signal.),
applying, by a second synapse circuit (Fig. 4A, a second one of the apparatuses 300 of crossbar array 400), a second time delay a second time delay, different to the first time delay to the first input signal, or to a second input signal, using a second resistive memory element (Paragraphs 36 and 38-39, “FIGS. 4A and 4B, there are respectively shown diagrams of crossbar arrays 400, 400′ that each includes the apparatuses 300, 300′ formed at junctions of the crossbar arrays 400… the crossbar array 400 includes a plurality of apparatuses 300, a plurality of first input lines 402, a plurality of second input lines 404, and a plurality of third input lines 406… The first input lines 402 are… connected to the inputs of the first memristors 302 and the second input lines 404 are … connected to the inputs (sources) of the transistors 306… the third input lines 406 are … connected to the outputs of the second memristors 304… each of the apparatuses 300 may be individually addressed by applying voltage to selected ones of the first and second input lines 402, 404.”, Paragraph 49, “for the same capacitance level, the higher the resistance level to which the first memristor 302 has been set, the longer the delay.”, Paragraphs 27-29, “With reference first to FIG. 3A, the apparatus 300 is depicted as including a first memristor 302, a second memristor 304, a transistor 306, and a capacitor 308… a first input voltage 310 may be supplied to an input of the first memristor 302… The amount of time it takes for the first input voltage 310 to reach the gate of the transistor 306 may depend upon the resistance level at which the first memristor 302 has been set or programmed and the capacitance level of the capacitor 308.”
Hu discloses that crossbar array 400 is formed of a plurality of individually addressable apparatuses 300 where each is structurally identical to each other and operates in the same manner as the apparatus of Fig. 3A. A second apparatus 300 of the plurality of apparatuses therefore corresponds to the second synapse circuit and its first memristor 302 corresponds to the second resistive memory element. Since each first memristor 302 is independently programmable to one of a plurality of available delay levels and each apparatus produces its own output, the second apparatus is programmed to a different resistance level and thereby produces a second time delay different from the other synapse circuits (apparatuses 300).),
the second synapse circuit comprising a second capacitor coupled to the second resistive memory element and configured to introduce the second time delay (Paragraph 38, "the crossbar array 400 may include any number of apparatuses 300, first input lines 402, second input lines 404, and third input lines 406. The first input lines 402 are depicted as being connected to the inputs of the first memristors 302 and the second input lines 404 are depicted as being connected to the inputs (sources) of the transistors 306. In addition, the third input lines 406 are depicted as being connected to the outputs of the second memristors 304." Paragraph 11, "Each of the memristor apparatuses includes a first memristor and a second memristor, with a transistor positioned between the first memristor and the second memristor, and with a capacitor position between the first memristor and the transistor.", Paragraph 49, "for the same capacitance level, the higher the resistance level to which the first memristor 302 has been set, the longer the delay."
Since each apparatus 300 is identical, the second apparatus includes its own capacitor 308 coupled to its first memristor 302. The delay is set by that memristor's resistance and the capacitance. This capacitor corresponds to the second capacitor introducing the second time delay.);
and generating a second output signal (Fig. 3A, output signal 314) at an output of the second synapse circuit by applying a second weight to the delayed second input signal. (Paragraph 36, “With reference now to FIGS. 4A and 4B, there are respectively shown diagrams of crossbar arrays 400, 400′ that each includes the apparatuses 300, 300′ formed at junctions of the crossbar arrays 400…”, Paragraph 30, “the voltage level of the reading signal may be reduced by the resistance level of the second memristor 304. In this regard, the resistance level of the second memristor 304 may apply a weight to the reading signal…”, Paragraph 58, “the second memristor 304 may output an output signal 314 that includes a delayed and weighted signal 712.”
As set forth above for the first synapse circuit, each apparatus 300 generates its output signal 314 by passing the delayed reading signal through its second memristor 304 where the resistance applies a weight to that signal. Hu's crossbar array 400 is formed of a plurality of structurally identical apparatuses 300 arranged at the junctions of the array (Paragraph 36), and the second apparatus operates in the identical manner as the first apparatus described above. It applies through its own second memristor 304 and its second weight to its own delayed second input signal to produce its own delayed and weighted output signal 314.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1), in view of Lee (US 20180285721 A1), and in further view of Dalgaty (US 20230125074 A1).
Regarding claim 3,
Hu does not teach a first dendritic circuit comprising the first synapse circuit and second synapse circuit and a first output line coupled to the outputs of the first synapse circuit and second synapse circuit the first output line being coupled to an input of a first neuron circuit of the neural network.
Lee, in the same field of endeavor, teaches a first dendritic circuit comprising the first and the second synapse circuits and a first output line coupled to the outputs of the first and second synapse circuits (Paragraph 42 of Lee, "the synapse array of the neuromorphic device in accordance with the present disclosure may include a plurality of pre-synaptic neurons 10, a plurality of post-synaptic neurons 20, a plurality of synapses 30, a plurality of row lines R, a plurality of column lines C… Each of the plurality of column lines C... may connect one of the plurality of post-synaptic neurons 20 to one of the plurality of synapses 30.", Paragraph 46, “A second electrode of the memristor 35 may electrically connected with the post-synaptic neuron 20 through the column line C.”, Paragraph 50, "An output node of a synapse 30, e.g., a column line C, may be electrically connected with an input terminal of the summation circuit 21.", Paragraph 52, "The summation circuit 21 may sum synapse weights of a plurality of synapses 30 on the same column line C, and may provide the summation of the synapse weights to the variable resistor 22,"
Lee teaches that multiple synapses 30 are connected to a common column line C which is connected to the input terminal of the summation circuit 21 of a post-synaptic neuron 20.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s teaching with Lee's common column line that sums the synaptic outputs and feeds a post-synaptic neuron in order to integrate the delayed synaptic outputs and produce a neuron firing decision (Paragraph 52 of Lee).
Hu in view of Lee does not teach the first output line being coupled to an input of a first neuron circuit of the neural network.
Dalgaty, in the same field of endeavor, teaches the first output line being coupled to an input of a first neuron circuit of the neural network (Paragraph 59 of Dalgaty, “The output current i.sub.out of the synapse circuit 202 is for example provided, on the output line 312, which is also the input of the destination neuron. In particular, the output line 312 is coupled to the common neuron input line 210 providing the summed currents, from each synapse circuit of the row, to the destination neuron.”, Paragraph 50, “FIG. 2 schematically illustrates a cross-point memory array 200 implementing a synaptic weight probability distribution matrix between the layers L1 and L2 of the neural network of FIG. 1... Each synapse S.sub.i,j between source neuron i and destination neuron j is implemented by a corresponding synapse circuit 202...The synapse circuits 202 of a same column are for example coupled to a common neuron output line 204 of each column, this line 204 for example being an output line of the source neuron of the synapse circuits 202 of the column...The synapse circuits 202 of a same row are for example coupled to a common neuron input line 210 of each row, this line 210 for example being coupled to an input of the destination neuron of the synapse circuits 202 of the row. For example, each synapse circuit 202 of each row generates an output current on the corresponding common neuron input line 210,”
The output line 312 of the first synapse circuit 202 corresponds to the first output line and the destination neuron (with neuron-sampling circuit 314) corresponds to the first neuron circuit.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu in view of Lee’s teaching with Dalgaty’s array of synapse circuits where each synapse circuit’s output line is coupled to a common neuron input line providing an input to a destination neuron circuit in order to route and sum the delayed output signals of the synapse circuits (Paragraphs 50 and 59 of Dalgaty).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Dalgaty (US 20230125074 A1).
Regarding claim 4,
Hu does not teach comprising: a first dendritic circuit comprising the first synapse circuit and second synapse circuit and a first output line coupled to the output of the first synapse circuit and second synapse circuit; and a second dendritic circuit comprising the first synapse circuit and second synapse circuit and a second output line coupled to the output of the first synapse circuit and second synapse circuit, the first output line being coupled to an input of a first neuron circuit of the neural network and the second output line being coupled to an input of a second neuron circuit of the neural network.
Dalgaty, in the same field of endeavor, teaches a first dendritic circuit comprising the first synapse circuit and a first output line coupled to the output of the first synapse circuit (Paragraph 50 of Dalgaty, “FIG. 2 schematically illustrates a cross-point memory array 200 implementing a synaptic weight probability distribution matrix between the layers L1 and L2 of the neural network of FIG. 1. Each synapse S.sub.i,j between source neuron i and destination neuron j is implemented by a corresponding synapse circuit 202… The synapse circuits 202 of a same row are for example coupled to a common neuron input line 210 of each row, this line 210 for example being coupled to an input of the destination neuron of the synapse circuits 202 of the row. For example, each synapse circuit 202 of each row generates an output current on the corresponding common neuron input line 210, and the sum of these currents provides an input current i.sub.outj to the corresponding destination neuron Nj′.”, Paragraph 58, “The resistive memory device 304 is for example coupled in series with a selection switch 310… between the common neuron output line 204 and an output line 312 of the synapse circuit 202”, Paragraph 59, “The output current i.sub.out of the synapse circuit 202 is for example provided, on the output line 312, which is also the input of the destination neuron. In particular, the output line 312 is coupled to the common neuron input line 210 providing the summed currents, from each synapse circuit of the row, to the destination neuron.”, See Figure 3.
The output line 312 is coupled to the output of the synapse circuit 202, and corresponds to the first output line coupled to the output of the first synapse circuit.)
and a second dendritic circuit comprising the second synapse circuit and a second output line coupled to the output of the second synapse circuit (Paragraph 50 of Dalgaty, “There are thus 16 synapse circuits 202 in the example of FIG. 2, one coupling each of the four source neurons N1 to N4 to each of the four destination neurons N1′ to N4′. The synapse circuits 202 are for example arranged in columns and rows… The synapse circuits 202 of a same row are for example coupled to a common neuron input line 210 of each row, this line 210 for example being coupled to an input of the destination neuron of the synapse circuits 202 of the row. For example, each synapse circuit 202 of each row generates an output current on the corresponding common neuron input line 210…”, Paragraph 72, “As illustrated in FIG. 6, the output lines 312 of the M synapse circuits are coupled together to form the common output line 210 of the row…”, Paragraph 59, “The output current i.sub.out of the synapse circuit 202 is for example provided, on the output line 312, which is also the input of the destination neuron.”
Dalgaty’s array includes a plurality of synapse circuits 202 arranged in rows and columns, each having its own output line 312. Each synapse circuit 202 in Dalgaty’s array has its own output line 312 in which its output current is provided.)
the first output line being coupled to an input of a first neuron circuit of the neural network (Paragraph 59, “The output current i.sub.out of the synapse circuit 202 is for example provided, on the output line 312, which is also the input of the destination neuron.”, Paragraph 50, “For example, each synapse circuit 202 of each row generates an output current on the corresponding common neuron input line 210, and the sum of these currents provides an input current i.sub.outj to the corresponding destination neuron Nj′.”, See Figure 2.
The output line 312 of the first synapse circuit is coupled to the input of the destination neuron of the first row (e.g., N1′), which corresponds to the first neuron circuit.)
and the second output line being coupled to an input of a second neuron circuit of the neural network (Paragraph 50, “For example, each synapse circuit 202 of each row generates an output current on the corresponding common neuron input line 210, and the sum of these currents provides an input current i.sub.outj to the corresponding destination neuron Nj′.”, Paragraph 47, “…the outputs of each of the neurons N1 to N4 being coupled to inputs of each of the neurons N1′ to N4′.”, Paragraph 72, “the parallel arrangement 600 corresponds to one row of synapse circuits 202… coupled to the sampling circuit (NEURON SAMPLING) 314 of the destination neuron.”
Each row of synapse circuits feeds its own common neuron input line 210, and thus its own destination neuron Nj′ (neuron-sampling circuit 314).)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s teaching with Dalgaty’s array of synapse circuits where each synapse circuit’s output line is coupled to a common neuron input line providing an input to a destination neuron circuit in order to route and sum the delayed output signals of the synapse circuits (Paragraphs 50 and 59 of Dalgaty).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Berdan ("Low-power linear computation using nonlinear ferroelectric tunnel junction memristors", 2020).
Regarding claim 7,
Hu does not teach wherein the first and the second resistive memory elements are Ferro-Tunnel Junction elements.
Berdan, in the same field of endeavor, teaches wherein the first and the second resistive memory elements are Ferro-Tunnel Junction elements (Page 259 of Berdan, “A relatively unexplored category of memristors is represented by ferroelectric tunnel junctions (FTJ)… Its bidirectional electric programmability provides memristive characteristics, whereas the tunneling transport mechanism allows for ultralow operating currents resulting in programmable conductances in the nanosiemens range.”, Page 259 Sectorless FTJ memristors, "Our FTJ device consists of a 4 nm Si-doped HfOx (HfSiO) layer and a 1 nm SiO2 layer between a top electrode and a bottom electrode as shown in Fig. 1a."
Berdan's programmable ferroelectric tunnel junction (FTJ) memristor used as the resistive device of a neuromorphic crossbar corresponds to the claimed Ferro-Tunnel Junction element.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s delay resistive memory elements with Berdan's ferroelectric tunnel junction memristors in order to obtain devices programmable to the high ultralow-current resistances for long time delays (Page 259 Introduction and Page 261 Linearizing the I-V characteristic of FTJ memristors of Berdan).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Esmanhotto ("High-Density 3D Monolithically Integrated Multiple 1T1R Multi Level-Cell for Neural Networks", 2020).
Regarding claim 8,
Hu does not teach wherein the third and fourth resistive memory elements are OxRAM elements.
Esmanhotto, in the same field of endeavor, teaches wherein the third and fourth resistive memory elements are OxRAM elements (Page 1 Introduction, "Neuromorphic hardware using 1T1R Resistive RAM (RRAM) has been demonstrated... showing improved energy efficiency and lower latency for AI edge devices.", Page 1 Section II of Esmanhotto, "MLC is achieved experimentally using a computer-in-the-loop with a fabricated array of 4,096 HfO2 based RRAM 1T1R planar structures…" Page 2 Section IV, "The HfO2 based RRAM cells were fabricated into the BEOL of the top tier…"
Esmanhotto implements its weight-storing 1T1R cells using HfO2-based oxide RRAM. Paragraph 66 of the instant specification states that “[e]ach of the programmable resistive element 110 is for example an element based on a metal-insulator-metal (MIM) structure, such as an OxRAM element, where the insulator is for example an oxide, for example comprising HfO2, Ta2O5, or SiO2.”, which Esmanhotto's HfO2-based RRAM weight cells teaches.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s weight-storing resistive memory elements with Esmanhotto's HfO2-based (OxRAM) 1T1R cells in order to provide improved energy efficiency and lower latency for the neural network hardware (Introduction and Section IV of Esmanhotto).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Yung (US 8975935 B1).
Regarding claim 9,
Hu does not teach the first synapse circuit further comprises a first comparator circuit coupled to the first resistive memory element and configured to generate an output pulse after the first time delay; and the second synapse circuit further comprises a second comparator circuit coupled to the second resistive memory element and configured to generate an output pulse after the second time delay.
Yung, in the same field of endeavor, teaches the first synapse circuit further comprises a first comparator circuit coupled to the first resistive memory element and configured to generate an output pulse after the first time delay; (Col. 3 Lines 1-25 of Yung, “a first resistor capacitor circuit coupled to the drain and source of the first FET, and between a voltage and a ground, a first comparator connected to an output of the first resistor capacitor circuit and to a first voltage reference for comparing the output of the first resistor capacitor circuit and the first voltage reference, the first comparator having an output…”, Col. 5 Lines 50-55, “The input 220 to comparator 222 has an exponentially varying waveform, such as waveform 224 shown in FIG. 4 … when input 220 is less than Vref 226, the comparator 222 output 228 goes high.”, Col. 6 Lines 24-36“The resulting output pulse 260 on output 230 has the same pulse width as the input pulse 204, as shown in FIG. 4… The amount of delay of the output pulse 260 from the input pulse 204 may be set by adjusting the Vref voltage 218 … The output pulse 260 may be delayed beyond the duration of the input pulse 204 as required in a neural circuit.”, Col. 1 Lines 62-65, “The delay is associated with the time for a spike to be transmitted across an axon. An axon connects a neuron core producing a spike to target synapses that receive delayed versions of that spike.”
As set forth above, Hu teaches the first resistive memory element (first memristor 302) that together with the capacitor, forms the delay-setting node of the first synapse circuit. Yung teaches a first comparator that receives the waveform at the output of the first RC delay node and drives its output high once that waveform falls below the reference voltage Vref. The threshold crossing is what produces the delayed output pulse.)
and the second synapse circuit further comprises a second comparator circuit coupled to the second resistive memory element and configured to generate an output pulse after the second time delay (Col. 3 Lines 18-25 of Yung, “a second comparator connected to an output of the second resistor capacitor circuit and to the first voltage reference for comparing the output of the second resistor capacitor circuit and the first voltage reference, the second comparator having an output, and the output of the second comparator connected to the reset input of the first flip flop and an inverted output of the second comparator connected to the second input of the AND gate.”, Col. 5 Lines 50-55, “The input 220 to comparator 222 has an exponentially varying waveform, such as waveform 224 shown in FIG. 4 … when input 220 is less than Vref 226, the comparator 222 output 228 goes high.”)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s teaching with Yung’s comparators that each receives a waveform in order to generate an output pulse at the end of the time delay (Col. 3 Lines 18-25 of Yung).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Yung (US 8975935 B1), and in further view of Sharifshazileh ("An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG", 2020).
Regarding claim 10,
Hu in view of Yung does not teach wherein the first and the second comparator circuits are implemented by fall-edge detectors or by rising edge detectors.
Sharifshazileh, in the same field of endeavor, teaches wherein the first and the second comparator circuits are implemented by fall-edge detectors or by rising edge detectors (Page 6 Section 2.1 of Sharifshazileh, "The Ve signal is then sent as input to a pair of comparators that produce either “UP” or “DN” digital pulses depending if Ve is greater than Vtu or lower than Vtd," Page 12 Section 5.4, "…whenever the amplitude variation of the input waveform exceeds an upper threshold Vtu a positive spike on the UP channel is generated; if the change in the amplitude is lower than a threshold Vtd, a negative spike in the DN channel is produced."
Sharifshazileh's pair of comparators emit an UP pulse on a rising threshold crossing and a DN pulse on a falling threshold crossing. The UP comparator corresponds to a rising-edge detector and the DN comparator corresponds to a fall-edge detector, which implements the comparator circuits as edge detectors.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s teaching with Sharifshazileh's UP/DN comparators that fire on rising and falling threshold crossings in order to implement the comparator circuits as edge detectors that emit a pulse upon a signal transition (Page 1 Introduction and Fig. 3d Caption of Sharifshazileh).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Yung (US 8975935 B1), and in further view of Cruz-Albrecht (US 20140032460 A1).
Regarding claim 12,
Hu in view of Yung does not teach wherein the first synapse circuit further comprises a first shift register configured to delay the first input signal, the first capacitor being configured to be discharged based on the first input signal of on one or more outputs of the first shift register, and wherein the second synapse circuit further comprises a second shift register configured to delay the second input signal, the second capacitor being configured to be discharged based on the second input signal and on one or more outputs of the second shift register.
Cruz-Albrecht, in the same field of endeavor, teaches wherein the first synapse circuit further comprises a first shift register configured to delay the first input signal, the first capacitor being configured to be discharged based on the first input signal of on one or more outputs of the first shift register, and (Paragraph 34, "The delay stages 40 are connected to the output of the neuron core 36 and implement axonal delays." Paragraph 47, "FIG. 9A shows a circuit for the delay stages block 40... which has as an input, y38, a series of delay stages 90, 92, 94, and 96, and a selector 98." Paragraph 47 further teaches "the selector... selects the output y38, the output of delay stage 90, the output of delay stage 92, the output of delay stage 94, or the output of delay stage 96." Paragraph 48, "Each delay stage may have a flip flop 100, a transconductance amplifier 102, a capacitor 110, and a comparator 106... When the capacitor is charged to the level of reference_d 108, the switch 112 is closed and the capacitor 110 is discharged and the flip flop is reset to again let an input voltage charge the capacitor 110."
The series of flip-flop delay stages sequentially propagates the input spike through multiple stages, with each stage representing a delayed version of the input signal before it is selected as an output. A person of ordinary skill in the art would have understood these sequential flip-flop stages to correspond to a shift register because they store and successively propagate the input signal to produce delayed outputs. Further, the delayed input signal controls charging of capacitor 110 until the reference level is reached, at which point the capacitor is discharged and the flip flop is reset. Thus, the capacitor is discharged based on the delayed input signal represented by one of the outputs of the sequential flip-flop stages, corresponding to the claimed capacitor being discharged based on the first input signal and one or more outputs of the first shift register.)
wherein the second synapse circuit further comprises a second shift register configured to delay the second input signal, the second capacitor being configured to be discharged based on the second input signal and on one or more outputs of the second shift register (Paragraph 34, "The delay stages 40 are connected to the output of the neuron core 36 and implement axonal delays." Paragraph 47, "FIG. 9A shows a circuit for the delay stages block 40... which has as an input, y 38, a series of delay stages 90, 92, 94, and 96, and a selector 98… The selector 98... selects the output y 38, the output of delay stage 90, the output of delay stage 92, the output of delay stage 94, or the output of delay stage 96." Paragraph 48, "Each delay stage may have a flip flop 100, a transconductance amplifier 102, a capacitor 110, and a comparator 106... When the capacitor is charged to the level of reference_d 108, the switch 112 is closed and the capacitor 110 is discharged and the flip flop is reset to again let an input voltage charge the capacitor 110."
Hu’s crossbar array 400 contains identical apparatuses 300 replicated at the array junctions of the same synapse circuit where when combined with Cruz-Albrecht's series of flip-flop delay stages, provides the claimed second circuit. The capacitor is discharged based on the delayed input signal represented by one of the outputs of the sequential flip-flop stages. Hu provides the multiple synapse circuits in Figure 4A with the plurality of apparatuses 300 which in combination with Cruz-Albrecht’s flip-flop delay stages producing a delayed input signal.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu’s delay synapse with Cruz-Albrecht's series of flip-flop delay stages and their associated capacitor charge-and-discharge timing in order to enable programmable synaptic transmission delays with multiple delayed outputs while utilizing the capacitor charge-and-discharge timing (Paragraphs 47 and 49 of Cruz-Albrecht).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20170221558 A1) in view of Hunzinger (US 20130073501 A1).
Regarding claim 13,
Hu does not teach wherein the first and the second weights are adjusted during a training phase.
Hunzinger, in the same field of endeavor, teaches wherein the first and the second weights are adjusted during a training phase (Paragraph 44 of Hunzinger, “With spike timing dependent plasticity, learning (adaptation) effects typically occur based on the timing relation between pre-synaptic (neuron's input) and post-synaptic events (neuron's output) (spikes). With spike timing dependent plasticity, weights may be adjusted as a function of this time difference.", Paragraph 31 of Hunzinger, “Adaptation of synaptic delays may be accompanied by adaptation of synaptic weights (strength or importance). The latter is often referred to as synaptic plasticity.”, Paragraph 27 of Hunzinger, “The synapses 104 may receive output signals (i.e., spikes) from the level 102 neurons, scale those signals according to adjustable synaptic weights w1 (i,i+1) , . . . , wP (i,i+1) (where P is a total number of synaptic connections between the neurons of levels”
Hunzinger discloses using spike timing dependent plasticity where the adjustable synaptic weights are adjusted as a function of the spike time difference (synaptic plasticity) during learning.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu's resistively-set delay element with Hunzinger's spike-timing-based delay adaptation in order to tune each synapse circuit's time delay during a training phase and improve pattern matching (Paragraph 80 of Hunzinger).
Regarding claim 14,
Hu does not teach wherein the first and the second time delays are adjusted during a training phase.
Hunzinger, in the same field of endeavor, teaches wherein the first and the second time delays are adjusted during a training phase (Paragraph 6 of Hunzinger, "adapting a delay of a synapse connection between a pre-synaptic neuron circuit and a post-synaptic neuron circuit of a neural network, wherein the adaptation is based on a time between a first spike of the post-synaptic neuron circuit and a second spike of the pre-synaptic neuron circuit," Paragraph 31, "Certain aspects of the present disclosure support a method of learning (adapting) synaptic delays.", Paragraph 44, "With spike timing dependent plasticity, learning (adaptation) effects typically occur based on the timing relation between pre-synaptic (neuron's input) and post-synaptic events (neuron's output) (spikes)."
Hunzinger discloses a method of learning synaptic delays in which the delay of a synapse connection is adapted based on the timing between pre- and post-synaptic spikes. This spike timing-based delay learning is applied to Hu's two delay synapse circuits that produces the first and second time delays.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hu's resistively-set delay element with Hunzinger's spike-timing-based delay adaptation in order to tune each synapse circuit's time delay during a training phase and improve pattern matching (Paragraph 80 of Hunzinger).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAJD MAHER HADDAD whose telephone number is (571)272-2265. The examiner can normally be reached Mon-Friday 8-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar, can be reached at (571) 272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.M.H./Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
Prosecution Insights