Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Regarding Claims 4, 13, 21 and 25, the term “shadow” is interpreted to mean a “vertical projection” as evidenced by paragraph [0043] of the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-13, 16, 21-25 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini (US 20200364600 A1).
Regarding Claim 1, Elsherbini teaches a device (100, shown Fig. 1) comprising:
a substrate (102) comprising:
a first layer stack (see annotated below) comprising multiple metal layers interspersed with multiple dielectric layers (see [0045]), wherein a first metal layer (shown annotated below) of the first layer stack comprises:
first contacts (see annotated) disposed in a first region of the first metal layer and configured to electrically connect to a first integrated circuit (IC) device (114-1);
via pads disposed in a second region of the first metal layer (see annotated), the second region offset along a first direction (horizontal direction) from the first region; and
traces (see annotated) electrically connected to the first contacts and to the via pads (shown Fig. 1), wherein one or more of the traces extend between a pair of the via pads (as viewed in plan-view); and
a second layer stack (see annotated) disposed on the second region of the first metal layer and defining a plateau relative to the first region of the first metal layer (shown Fig. 1), the second layer stack comprising:
a dielectric layer (see [0041] describing multiple dielectric layers being implemented and “one or more conductive pathways through the dielectric material” as shown in Fig. 1);
a second metal layer (see annotated) disposed on the dielectric layer opposite the first layer stack, the second metal layer defining second contacts (146) configured to electrically connect to one or more second IC devices (114-2 and 114-4); and
conductive vias (see annotated) extending between the via pads and the second contacts.
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Regarding Claim 2, Elsherbini teaches the device of claim 1, wherein the first IC device includes first circuitry forming one or more processor cores (see [0037-0039]) and the second IC device includes second circuitry forming one or more memory cells (see [0037-0039] which describes that each die may be a QP die including circuitry for performing quantum computations, which are known in the art as including processing logic and memory functions).
Regarding Claim 3, Elsherbini teaches the device of claim 1, wherein the first layer stack further comprises external contacts (140), and wherein the external contacts are electrically connected, by conductive paths of the multiple metal layers, to the first contacts, the second contacts, or both, to provide off-package connections (shown Fig. 1, wherein the package is connected to circuit board 133).
Regarding Claim 4, Elsherbini teaches the device of claim 1, wherein one or more of the traces intersect a shadow of one or more of the second contacts (shown Fig. 1, wherein at least some second contacts partially overlap the traces below).
Regarding Claim 9, Elsherbini teaches the device of claim 1, further comprising:
the first IC device electrically connected, via a first array of interconnects (150-1), to the first contacts; and
the second IC device electrically connected, via a second array of interconnects (150-2), to the second contacts (shown Fig. 1).
Regarding Claim 10, Elsherbini teaches the device of claim 9, wherein the first IC device comprises a semiconductor die (see [0044]) and the one or more second IC devices comprise a surface-mountable package (shown Fig. 1).
Regarding Claim 11, Elsherbini teaches the device of claim 1.
Elsherbini further describes in paragraph [0076] that any of the arrangements of dies may be part of a repeating pattern (for example, the pattern in Fig. 10 is repeated in Fig. 11 to accommodate a plurality of dies). Repeating the pattern shown in Fig. 1 would further teach a third die matching the configuration of the first die, wherein the first metal layer further comprises third contacts disposed in a third region of the first metal layer, wherein the third contacts are configured to electrically connect to a third IC device, and wherein the second region is between the first region and the third region.
Regarding Claim 12, Elsherbini teaches the device of claim 11, wherein the first metal layer further comprises second via pads in the second region and second traces electrically connected to the third contacts and to the second via pads (matching the pattern of the first contacts and the first via pads), and wherein the second layer stack further comprises fourth contacts and second conductive vias extending between the second via pads and the fourth contacts to form conductive paths between the third IC device and the second IC device (matching the configuration of the second contacts and the first conductive vias, see also [0076]).
Regarding Claim 13, Elsherbini teaches the device of claim 12, wherein one or more of the second traces extends between a pair of the second via pads and intersects a shadow of one or more of the fourth contacts (matching the configuration of the first traces, see also [0076]).
Regarding Claim 16, Elsherbini teaches a method for fabricating a device, the method comprising:
forming a first layer stack (see annotated below) comprising multiple metal layers interspersed with multiple dielectric layers, wherein forming the first layer stack includes forming a first metal layer that includes:
first contacts disposed in a first region of the first metal layer and configured to electrically connect to a first integrated circuit (IC) device (114-1);
via pads (see annotated below) disposed in a second region of the first metal layer that is laterally offset from the first region; and
traces (see annotated below) electrically connected to the first contacts and to the via pads, wherein one or more of the traces extend between a pair of the via pads (as viewed in plan-view);
forming a dielectric layer of a second layer stack (see annotated below) on the second region of the first metal layer to define a plateau relative to the first region of the first metal layer (shown Fig. 1);
forming conductive vias (see annotated below) electrically connected to the via pads through openings of the dielectric layer; and
forming a second metal layer (see annotated below) on the dielectric layer, the second metal layer defining second contacts (146) electrically connected to the conductive vias, the second contacts configured to electrically connect to one or more second IC devices (114-2).
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Regarding Claim 21, Elsherbini teaches the method of claim 16, wherein at least one contact of the second contacts is formed such that one or more of the traces intersects a shadow of the at least one contact (shown Fig. 1).
Regarding Claim 22, Elsherbini teaches a device (shown Fig. 1) comprising:
one or more first integrated circuit (IC) devices (114-1);
one or more second IC devices (114-2); and
a substrate (102) coupled to the one or more first IC devices and the second IC devices and defining conductive paths therebetween (see annotated below), the substrate comprising:
a first layer stack (see annotated below) comprising multiple metal layers interspersed with multiple dielectric layers, wherein a first metal layer of the first layer stack comprises:
first contacts (see annotated below) disposed in a first region of the first metal layer and electrically connected to the one or more first IC devices (shown Fig. 1);
via pads (see annotated below) disposed in a second region of the first metal layer, the second region offset along a first direction from the first region; and
traces (see annotated below) electrically connected to the first contacts and to the via pads, wherein one or more of the traces extend between a pair of the via pads (as viewed in plan-view); and
a second layer stack (see annotated below) disposed on the second region of the first metal layer and defining a plateau relative to the first region of the first metal layer, the second layer stack comprising:
a dielectric layer (see [0041] describing multiple dielectric layers being implemented and “one or more conductive pathways through the dielectric material” as shown in Fig. 1);
a second metal layer (see annotated below) disposed on the dielectric layer opposite the first layer stack, the second metal layer defining second contacts (146, see annotated below) electrically connected to the one or more second IC devices; and
conductive vias extending between the via pads and the second contacts (shown Fig. 1).
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Regarding Claim 23, Elsherbini teaches the device of claim 22, wherein the one or more first IC devices include one or more processor cores and the one or more second IC devices include one or more memory cells (see [0037-0039] which describes that each die may be a QP die including circuitry for performing quantum computations, which are known in the art as including processing logic and memory functions).
Regarding Claim 24, Elsherbini teaches the device of claim 22, wherein the first layer stack further comprises external contacts (140), and wherein the external contacts are electrically connected to the first contacts, the second contacts, or both, to provide off-package connections (shown Fig. 1).
Regarding Claim 25, Elsherbini teaches the device of claim 22, wherein one or more of the traces intersect a shadow of one or more of the second contacts (see annotated above).
Regarding Claim 30, Elsherbini teaches the device of claim 22, further comprising a heat sink (131) coupled to an upper surface of at least one of the one or more first IC devices, at least one of the one or more second IC devices, or both (shown Fig. 1, see also [0058]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (US 20200364600 A1).
Regarding Claim 14, Elsherbini teaches the device of claim 11.
Elsherbini further teaches that the conductive traces within the device may connect any of the conductive contacts “in any suitable matter” (see [0044]) and the first die may bridge to other dies (see also [0076]). Elsherbini does not explicitly describe a third trace configured to electrically connect the third IC device and the first IC device.
However, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to electrically connect any plurality of dies in a repeating pattern as suggested by paragraph [0076] to accommodate a desirable assembly. More specifically, it would be obvious to implement at least one metal layer of the multiple metal layers to comprise third traces configured to electrically connect the third IC device and the first IC device as this would be an obvious design choice (see also MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47).
Regarding Claim 15, Elsherbini teaches the device of claim 1.
Elsherbini further describes in paragraph [0076] that any of the arrangements of dies may be part of a repeating pattern (for example, the pattern in Fig. 10 is repeated in Fig. 11 to accommodate a plurality of dies). Repeating the pattern shown in Fig. 1 would further teach a third die matching the configuration of the first die, wherein the first metal layer further comprises third contacts disposed in a third region of the first metal layer, wherein the third contacts are configured to electrically connect to a third IC device, and wherein the second region is between the first region and the third region.
Specifically, this repeating pattern would further teach that the first metal layer further comprises second via pads and second traces electrically connected to the first contacts and to the second via pads;
the second metal layer comprises fourth contacts configured to couple to a third IC device.
Elsherbini does not explicitly teach a conductive pathway in the second layer stack being formed to connect the third IC device and the first IC device.
However, Elsherbini further teaches that the conductive traces within the device may connect any of the conductive contacts “in any suitable matter” (see [0044]) and the first die may bridge to other dies (see also [0076]). Elsherbini does not explicitly describe a third trace configured to electrically connect the third IC device and the first IC device.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to electrically connect any plurality of dies in a repeating pattern as suggested by paragraph [0076] to accommodate a desirable assembly. More specifically, it would be obvious to configure the second layer stack to comprise second conductive vias extending between the fourth contacts and the second via pads to form conductive paths between the third IC device and the first IC device as this would be an obvious design choice (see also MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47).
Claim(s) 5-8, 17-20 and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (US 20200364600 A1) in further view of Lei (US 20140117533 A1).
Regarding Claim 5, Elsherbini teaches the device of claim 1, but is silent regarding a “characteristic dimension” of the second contacts relative to the via pads.
Lei teaches a semiconductor package comprising a contact (134 and 128) and a via pad (106, shown Fig. 17) wherein a characteristic dimension (interpreted as a contact area between the contact and solder ball 168 shown in Fig. 18) is greater than a characteristic dimension of the via pad (interpreted as a contact area between the contact and via pad, shown Fig. 17).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to optimize the characteristic dimensions (interpreted as effective contact areas) of the second contacts and via pads of Elsherbini as this would improve electrical characteristics (see [0051]) while minimizing feature size (see also [0002] and [0050]).
Specifically, this modification would teach wherein a characteristic dimension of the second contacts is greater than a characteristic dimension of the via pads.
Regarding Claim 6, Elsherbini as modified by Lei teaches the device of claim 5.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that a characteristic dimension (a contact area) is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal characteristic dimension of the second contacts in relation to the via pads. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach that the characteristic dimension of the second contacts is at least three times the characteristic dimension of the via pads through routine optimization.
Regarding Claim 7, Elsherbini as modified by Lei teaches the device of claim 5.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that pitch and spacing between conductive features is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal pitch between adjacent via pads and adjacent second contacts Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach a pitch of the via pads is approximately equal to a pitch of the second contacts through routine optimization.
Regarding Claim 8, Elsherbini as modified by Lei teaches the device of claim 5.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that pitch and characteristic spacing between conductive features is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal pitch between adjacent via pads and adjacent second contacts Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach a characteristic spacing between adjacent via pads is greater than a characteristic spacing between adjacent second contacts by at least a factor of two through routine optimization.
Regarding Claim 17, Elsherbini teaches the method of claim 16, wherein forming the first layer stack comprises:
forming the multiple metal layers and the multiple dielectric layers on a carrier (see [0086] and Fig. 17C);
removing the carrier (shown Fig. 17C) to expose an upper surface of the first layer stack, wherein the upper surface of the first layer stack includes an upper surface of the first metal layer and an upper surface of a first dielectric layer of the first layer stack (shown Fig. 17D).
Elsherbini does not explicitly teach a step of etching the upper surface of the first metal layer to recess the first metal layer below the upper surface of the first dielectric layer of the first layer stack.
Lei teaches a method of forming a contact structure wherein a first metal layer (contact pad 106, shown Fig. 8) is recessed (see also [0025]) below an upper surface of a first dielectric layer (110, see also Fig. 9).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of Elsherbini to further recess a top surface of the first metal layer to below a top surface of a first dielectric layer as suggested by Lei as this would improve electrical performance through an easily implementable manufacturing process flow (see also [0051-0053]). More specifically, this modification would teach a step of etching the upper surface of the first metal layer to recess the first metal layer below the upper surface of the first dielectric layer of the first layer stack.
Regarding Claim 18, Elsherbini as modified by Lei teaches the method of claim 17, wherein forming the dielectric layer of the second layer stack comprises:
forming a photo-imageable dielectric (PID) layer coupled to the upper surface of the first dielectric layer of the first layer stack at least in the second region (see [0041] describing polyimide materials which are known to be photo-imageable and Fig. 23A which shows a second stack portion (151) being formed on a first stack portion (153)); and
forming openings in the PID layer to the via pads (shown Fig. 1).
Regarding Claim 19, Elsherbini as modified by Lei teaches the method of claim 18, wherein forming the conductive vias comprises depositing metal within the openings of the PID layer and electrically connected to the via pads (as is implicitly described by Figs. 23A and paragraph [0041]).
Regarding Claim 20, Elsherbini as modified by Lei teaches the method of claim 19, wherein forming the second metal layer comprises:
forming a resist layer on the PID layer (see described in [0067]); and
depositing metal, guided by the resist layer, to define the second contacts electrically connected to the conductive vias (as evidenced by the disposition of second contacts shown in Fig. 1).
Regarding Claim 26, Elsherbini teaches the device of claim 22, but is silent regarding a “characteristic dimension” of the second contacts relative to the via pads.
Lei teaches a semiconductor package comprising a contact (134 and 128) and a via pad (106, shown Fig. 17) wherein a characteristic dimension (interpreted as a contact area between the contact and solder ball 168 shown in Fig. 18) is greater than a characteristic dimension of the via pad (interpreted as a contact area between the contact and via pad, shown Fig. 17).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to optimize the characteristic dimensions (interpreted as effective contact areas) of the second contacts and via pads of Elsherbini as this would improve electrical characteristics (see [0051]) while minimizing feature size (see also [0002] and [0050]).
Specifically, this modification would teach wherein a characteristic dimension of the second contacts is greater than a characteristic dimension of the via pads.
Regarding Claim 27, Elsherbini as modified by Lei teaches the device of claim 26.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that a characteristic dimension (a contact area) is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal characteristic dimension of the second contacts in relation to the via pads. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach that the characteristic dimension of the second contacts is at least three times the characteristic dimension of the via pads through routine optimization.
Regarding Claim 28, Elsherbini as modified by Lei teaches the device of claim 26.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that pitch and spacing between conductive features is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal pitch between adjacent via pads and adjacent second contacts Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach a pitch of the via pads is approximately equal to a pitch of the second contacts through routine optimization.
Regarding Claim 29, Elsherbini as modified by Lei teaches the device of claim 26.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Lei shows that pitch and characteristic spacing between conductive features is a result-effective variable because it reveals that tuning these variables improves electrical performance while minimizing feature size (see also [0050-0051]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal pitch between adjacent via pads and adjacent second contacts Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, Elsherbini as modified by Lei would teach a characteristic spacing between adjacent via pads is greater than a characteristic spacing between adjacent second contacts by at least a factor of two through routine optimization.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Choi (US 20230114404 A1) teaches a method of forming an embedded trace substrate with embedded metal traces having different thicknesses to tune a package height.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
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/C.P.B./ Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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