DETAILED ACTION
This action is in response to the claims filed 10/20/2023 for Application number 18/491,251. Claims 1-2, 4-7, 9, 11-17, 21, and 23-27 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The claims are objected to because they include reference characters which are not enclosed within parentheses. See claim 21.
Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
Claims 2, 4-7, 9, 11-17, 21, 23-24, and 26 are objected to because of the following informalities: The claims recite "A method according to claim 1"/"A system . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 9, 17 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the pentagon equation". There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the gate type". There is insufficient antecedent basis for this limitation in the claim. Examiner notes gate type was recited in claim 5 however this claim refers back to independent claim 1 without any previous recitation of gate type.
Claim 9 recites the limitation "the pentagon equation". There is insufficient antecedent basis for this limitation in the claim. Examiner notes pentagon equation was recited in claim 7 however this claim refers back to independent claim 1 without any previous recitation of pentagon equation.
Claim 17 recites the limitation "the A gate and the evolution operator of the 1D Heisenberg model". There is insufficient antecedent basis for this limitation in the claim.
Claim 23 recites the limitation "the pentagon equation". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 4-7, 9, 11-17, 21, and 23-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1,
Step 1 Analysis: Claim 1 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 1 recites, in part, The limitations of:
determining whether the circuit section meets a compression criterion can be considered to be an evaluation in the human mind,
in response to determining that the circuit section meets the compression criterion, modifying the circuit definition to replace the first arrangement of quantum gates with the second arrangement of quantum gates can be considered to be an evaluation in the human mind
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers performance of the limitation in the mind or with the aid of pen and paper which falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements – “a quantum circuit”. Thus, this element that is recited is only generally linked to the judicial exception. Please see MPEP 2106.05(h). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites: receiving data defining a quantum circuit, the quantum circuit including at least one section that matches a predetermined first arrangement of quantum gates, the first arrangement including a non-local interaction and being associated with a predetermined second arrangement of quantum gates that does not include the non-local interaction and outputting the modified circuit definition. These limitations are mere data gathering and outputting steps and thus are insignificant extra-solution activities. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of utilizing a quantum circuit to perform the steps of the claimed process amount to generally linking the additional element to the judicial exception. Furthermore, the limitation of receiving data defining a quantum circuit, the quantum circuit including at least one section that matches a predetermined first arrangement of quantum gates, the first arrangement including a non-local interaction and being associated with a predetermined second arrangement of quantum gates that does not include the non-local interaction and outputting the modified circuit definition is well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to generally linking the additional element to the judicial exception and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
Regarding claim 2, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the non-local interaction comprises at least one of: a gate operating on non-adjacent qubits of the quantum circuit.; a non-local interaction implemented using at least one SWAP gate. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 4, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the circuit section comprises at least one SWAP gate for implementing the non- local interaction, and wherein the second arrangement does not include the at least one SWAP gate. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 5, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the first arrangement comprises one or more gates of a given gate type, wherein determining whether the circuit section meets the compression criterion comprises determining whether the one or more gates meet a gate criterion, the gate criterion determining an equivalence between the first arrangement of quantum gates and the second arrangement of quantum gates. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 6, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the equivalence is defined by an equivalence equation, and wherein determining whether the one or more gates meet the gate criterion comprises determining whether the one or more gates correspond to a solution of the equivalence equation.
This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 7, the rejection of claim 5 is further incorporated, and further, the claim recites: wherein determining whether the one or more gates meet the gate criterion comprises determining whether the one or more gates are fusion operators and/or wherein determining whether the circuit section meets a compression criterion comprises determining whether the one or more gates correspond to a valid solution of the pentagon equation. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 9, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the compression criterion comprises a predetermined set of evaluation criteria associated with a set of gates in the first arrangement and defined on parameters of the gates, the method comprising determining whether the parameters of the gates in the received circuit definition satisfy the evaluation criteria, comprising identifying the gate type of one or more gates in the circuit section matching the first gate arrangement, and selecting the evaluation criteria to be evaluated in dependence on the gate type.. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 11, the rejection of claim 9 is further incorporated, and further, the claim recites: wherein the set of evaluation criteria comprises a set of equations, the equations preferably derived from the pentagon equation. This claim recites additional mathematical steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 12, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the second arrangement comprises at least one of: an arrangement of gates having fewer gates than the first arrangement and/or having a shorter circuit depth; an arrangement of gates that is functionally equivalent to the first arrangement of gates. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 13, the rejection of claim 1 is further incorporated, and further, the claim recites: processing the received circuit definition to identify the section of the quantum circuit matching the first arrangement, preferably by identifying an arrangement of gates in the circuit that matches a circuit template specifying the first arrangement of gates. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 14, the rejection of claim 13 is further incorporated, and further, the claim recites: comprising repeating the processing, determining and modifying steps one or more times, until no further circuit sections matching the first arrangement are found. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 15, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the first arrangement comprises two gates implementing local interactions between respective adjacent pairs of qubits in a quantum system of at least three qubits and a third gate implementing the non-local interaction between a non-adjacent pair of the qubits. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 16, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the quantum circuit comprises at least three qubits, the first arrangement of gates comprising first and second SWAP gates arranged, respectively, before and after a further gate to implement an interaction between two non-adjacent ones of the three qubits, wherein the first arrangement of gates comprises a further gate prior to the first SWAP gate providing an input to the first SWAP gate and/or a further gate subsequent to the second SWAP gate utilising an output of the second SWAP gate. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 17, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the gates used in the first gate arrangement (other than SWAP gates) are of a common gate type T, wherein the common gate type T is one of: the A gate, and the evolution operator of the 1D Heisenberg model, and wherein the second arrangement comprises two gates of the gate type T operating on respective adjacent pairs of the qubits. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 21, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein at least one of: the first arrangement of quantum gates is a gate arrangement as shown in arrangement 220 of FIG. 2B or as shown in FIG. 3A; and the second arrangement of quantum gates is a gate arrangement as shown in arrangement 222 of FIG. 2B or as shown in FIG. 3B. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 23, the rejection of claim 1 is further incorporated, and further, the claim recites:
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This claim recites additional mathematical steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 24, the rejection of claim 1 is further incorporated, and further, the claim recites: outputting the modified circuit definition to a quantum transpiler for transpilation to a target quantum computer, This is an insignificant extra-solution activity.
wherein the transpiler outputs the compressed, transpiled circuit to a quantum controller for implementation on a quantum processing unit, and executing the circuit defined by the modified circuit definition by the quantum controller using the quantum processing unit. This limitation amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
The claim does not include any additional elements that amount to significantly more than the judicial exception. The limitation of “outputting the modified circuit definition to a quantum transpiler for transpilation to a target quantum computer” is just a nominal or tangential addition to the claim, and is also well-understood, routine and conventional as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. This limitation therefore remains insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, this additional element represents an insignificant extra-solution activity which cannot provide an inventive concept. The claim is not patent eligible.
Claim 25 recites features similar to claim 1 and is rejected for at least the same reasons therein. Claim 25 additionally requires analysis for “A system for compressing a quantum circuit, the system comprising a computer device having a processor with associated memory being configured to” however this is an additional element that amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
Regarding claim 26, the rejection of claim 1 is further incorporated, and further, the claim recites: further comprising a quantum computer coupled to the computer device. This limitation amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Claim 27 recites features similar to claim 1 and is rejected for at least the same reasons therein. Claim 27 additionally requires analysis for “A non-transitory computer readable medium comprising software code adapted, when executed by a data processing system, to perform operations comprising” however this is an additional element that amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
Allowable Subject Matter
Claims 1-2, 4-7, 9, 11-17, 21, and 23-27 are objected to as being allowable over prior art if all outstanding rejections were withdrawn. None of the prior art, either alone or in combination, fairly discloses limitations of claims 1, 25 and 27 in particular:
receiving data defining a quantum circuit, the quantum circuit including at least one section that matches a predetermined first arrangement of quantum gates, the first arrangement including a non-local interaction and being associated with a predetermined second arrangement of quantum gates that does not include the non-local interaction;
determining whether the circuit section meets a compression criterion;
in response to determining that the circuit section meets the compression criterion, modifying the circuit definition to replace the first arrangement of quantum gates with the second arrangement of quantum gates; and
outputting the modified circuit definition.
The closest prior art uncovered was Peng et al. (“Quantum time dynamics employing the Yang-Baxter equation for circuit compression” cited by Applicant in the IDS filed 10/20/2023) which discloses a quantum circuit compression method in the framework of Hamiltonian evolution of the 1D Heisenberg model however fails to explicitly disclose the quantum circuit including at least one section that matches a predetermined first arrangement of quantum gates, the first arrangement including a non-local interaction and being associated with a predetermined second arrangement of quantum gates that does not include the non-local interaction;
determining whether the circuit section meets a compression criterion;
in response to determining that the circuit section meets the compression criterion, modifying the circuit definition to replace the first arrangement of quantum gates with the second arrangement of quantum gates; and
outputting the modified circuit definition.
The reference does not explicitly disclose the first arrangement of quantum gate nor modifying the circuit definition to replace the first arrangement with the second arrangement of quantum gates.
Yamaguchi et al. (“US 20250348645 A1”) discloses a method for quantum circuit design using multiple qubits and quantum gates however fails to explicitly teach the first arrangement of quantum gate nor modifying the circuit definition to replace the first arrangement with the second arrangement of quantum gates as required by the claims.
Martiel et al. (“US 20200242295 A1”) discloses a method for optimizing a quantum circuit of an ordered series of quantum gates however fails to explicitly disclose the first arrangement of quantum gate nor modifying the circuit definition to replace the first arrangement with the second arrangement of quantum gates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL H HOANG whose telephone number is (571)272-8491. The examiner can normally be reached Mon-Fri 8:30AM-4:30PM.
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/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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