DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Summary Invention
The invention relates to a feedback amplifier—such as one used in a low-dropout (LDO) regulator—in which the amplifier stage operates from a higher supply voltage than the output stage, enabling a pre-driver to drive the gate or well of an output transistor to a voltage higher than the output supply rail to reduce leakage and improve standby performance. A feedback path from the output device adjusts the amplifier drive such that the channel field potential exceeds the lower supply voltage, thereby maintaining regulation and preventing output drift or unwanted conduction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-7, 9-11, 16, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Zhou (US 2023/0400872 Al, effectively filed on June 13, 2022, before the effective filing date of the current invention October 20, 2023).
Regarding claim 1 Zhou discloses, in Fig. 3 (annotated by the Examiner), a low-dropout regulator (LDO) architecture 300, which forms a regulated power supply circuit per claim 10, to provide regulated power supply output from the output device per claim 20, incorporating:
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Fig. 3 of Zhou annotated by the examiner for ease of reference.
An amplifier stage: Zhou’s first amplification stage 101 (Fig. 3; §0013-§0018) is an error amplifier receiving Vref and VFB, producing differential outputs VP and VN that drive the subsequent stage. Stage 101 is powered by VCC, expressly a first power-supply rail (§0021).
An output stage including a pre-driver and output transistor: Zhou’s buffer stage 104 functions as a pre-driver, and transistor 110 is the power/output device of the LDO (Fig. 3; §0013, §0019, §0020, §0022). The buffer stage 104 receives the output of amplifier stage 102 and drives the gate of the output transistor 110.The output stage is powered by VIN, which in Zhou’s embodiments is explicitly of lower magnitude than VCC (§0021): “first power supply VCC… second power supply VDD… VDD higher than VCC”; Fig. 3 shows VIN < VDD < VCC typical LDO operation).
A feedback connection from the output device: Zhou provides two feedback paths from the output:• VFB, via resistor network 120 (Fig. 3, §0013, §0017, §0019)• Vcf, via capacitor 103 providing feed-forward (Fig. 3, §0015, §0016, §0022)Both signals return to the amplifier stages 101 and 102.
Driving the channel potential above the output-stage supply: Zhou discloses that the amplifier stages—powered by VCC and VDD, both higher than VIN—drive the gate of the output transistor 110 to values necessary for regulation.Specifically, ¶ [0021] states: “the second amplification stage 102 and the buffer stage 104 are powered by a second power supply VDD… higher than the first power supply VCC.”Fig. 3 shows that node VA, output of stage 102, is level-shifted and buffered to the gate of transistor 110.This necessarily drives the channel region and gate potential of power transistor 110 to voltages exceeding VIN, precisely to regulate VO under varying load, satisfying the limitation that the channel field potential exceeds the second supply magnitude.
Accordingly, Zhou discloses every element of claim 1, arranged as claimed.
Claim 6 states that the amplifier forms an LDO, and the output device provides the regulated output, and in standby the gate is driven above the second rail to avoid turning on.
Zhou explicitly teaches an LDO (title, abstract, ¶¶ [0002]–[0004), while its power device 110 provides the LDO output VO. Gate-drive above VIN to hold the device off during soft-start/standby is inherent from Zhou’s description of high-voltage drive rails VCC and VDD.
Claim 7 focuses on coupling of the amplifier stage to the well of the output transistor and raising its potential above the second supply.
Zhou’s Fig. 3 depicts fully-integrated MOS devices with bulk ties (as typical).Stages 101 and 102 providing higher supply rails (VCC and VDD) necessarily raise the gate, the channel region, and by standard CMOS layout, the well bias during high-gain operation.
Although not explicitly mentioned, this is inherent in CMOS implementation where well is tied to the highest potential rail or driven through the gate structure. Thus claim 7 is anticipated by Zhou because driving the gate above VIN raises the channel field potential and the MOS body regions consistent with integrated operation.
Regarding claim 9, Zhou explicitly teaches the feedback compensates for voltage changes and adjusts the pass-device conduction to suppress leakage and transients (§0029–§0030).
Also, per claim 11, All steps—driving a power device, using a pre-driver, boosting gate/channel potential above VIN—are inherent in Zhou.
Further per claim 16, Standby/off-mode behavior using gate overdrive above VIN is inherent from Zhou’s high-voltage amplifier supply rails.
Claim 19 requires Feedback compensating for leakage, which is explicitly discussed by Zhou (§0029).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of generic MOS current-mirror teachings of Guo et. al. (CN113268102).
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Fig. 5 of Guo annotated by the examiner for ease of reference.
claims 2 and 12, recites that the output transistor and pre-driver form a current mirror. Zhou does not show transistor 104 and 110 arranged as a current mirror.
However, forming a pre-driver–power-transistor pair as a MOS current mirror is well-known and appears in many LDO prior arts (e.g., standard source-follower pass device with mirror-based biasing, as found in Fig. 4 of Guo.
Therefore, a person of ordinary skill in the art (POSITA) would have found it obvious to implement the pre-driver 104 and output transistor 110 as a mirror pair to reduce bias error, provide scalable drive strength, and simplify level shifting, i.e., the obvious benefits of current mirror biasing as a common knowledge in the art in Zhou’s advanced LDO circuit and thereby the modified Zhou LDO in view of Guo’s current mirror bias circuit of Figs. 4-5, would teach all limitations of claim 2.
Claims 3, 5 and 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Camacho et al. (“Fully on-chip switched capacitor NMOS low dropout voltage regulator”, published by Springer in Analog Integrated Circuits Signal Processing, Dec. 2009).
Regarding claims 3 and 13, Zhou although teaches the higher-voltage driving rails, does not disclose gate drive explicitly described as “one threshold above the second supply.” This is typical of gate-overdrive mirror topologies but not inherent in Zhou’s differential amplifier and buffer arrangement.
However, using an upstream amplifier (101/102) powered by higher rails (VCC/VDD) to overdrive the gate of a low-side NMOS pass transistor above VIN is standard practice in NMOS-based LDO regulators as shown in Fig. 2 as implemented in Fig. 4 of Camacho.
Thus, it would have been obvious to include standard NMOS LDO gate-boost techniques into Zhou’s advanced LDO to overdrive the gate of a low-side NMOS pass transistor above VIN in view of Camacho, and the modified Zhou LDO would thereby teach all limitations of claims 3 and 13.
Further per claims 5 and 15, Zhou also teaches a bipolar swing of the gate voltage of the output device to regulate V0 by sourcing and sinking current (see transistors N7 and N8 with respect to the output device N9 in annotated Fig. 3 of Zhou).
Claims 4 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over Zhou in view of Al-Shyoukh et al. (US 2009/0167266 A1).
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Fig. 1 of Al-Shyoukh reproduced by the examiner for ease of reference.
Regarding Claims 4 and 14, Zhou teaches a low dropout (LDO) regulator circuit comprising:
A power device (110) operating at a resistive region to convert an input voltage (VIN) to an output voltage (VO) (§0013, Figs. 1-3)
A first amplification stage (101) and second amplification stage (102) (§0013)
The first amplification stage is powered by a first power supply voltage (Vcc) and the second amplification stage is powered by a second power supply voltage (VDD) (§0021, claim 3)
The second power supply VDD has a voltage value higher than the first power supply Vcc (§0021]: "the first power supply Vcc may be lower than 3.6V, and the second power supply VDD may be higher than 5V")
However, Zhou does not explicitly teach:
NFETs with dual-gate structure (front gate and back gate) where the back gate receives a negative bias voltage
That a positive bias voltage applied to a gate of an NFET is higher than the positive power supply voltage feeding an output transformer in a power amplifier configuration with stacked transistor chains
In a similar field of endeavor, Al-Shyoukh teaches a power amplifier for radio frequency applications comprising:
Third NFETs (130a, 130b) having front gates (131a, 131b) and back gates (132a, 132b) in a stacked transistor configuration (§0023, Fig. 2)
The back gates receive a negative bias voltage (VBGN) (§0036, §0042)
The front gates receive a second positive bias voltage (VG2) (§0025, §0043)
Critically, VG2 ≥ VDD_APT, where VDD_APT is the positive power supply voltage to the output transformer (§0039: "VDD_APT≤VG2<VBAT")
§0045] explicitly states: "By increasing the VTs of third NFETs 130a, 130b, VG2 can be set at a relatively high voltage level (e.g., at or above VDD_APT) in order to increase the power output (Pout) of the power amplifier 10 without violating a TDDB off-state reliability specification for third NFETs 130a, 130b"
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Zhou's LDO regulator circuit to include the teaching of Al-Shyoukh that the positive bias voltage applied to the front gate of an NFET should be higher than the positive power supply voltage.
One of ordinary skill would have been motivated to make this modification for the following reasons:
Both Zhou and Al-Shyoukh relate to voltage regulator circuits using NFET devices that must operate reliably at high power levels.
Al-Shyoukh expressly teaches and provides motivation for setting the gate bias voltage (VG2) at or above the power supply voltage (VDD_APT) to "increase the power output" while maintaining reliability (§0045). This directly addresses a predictable design consideration in power management circuits - maximizing power output while maintaining device reliability.
The modification would yield predictable results. Al-Shyoukh demonstrates that by applying reverse back bias (negative voltage to back gate) to increase the threshold voltage, one can safely apply a higher positive bias voltage to the front gate - even exceeding the supply voltage - without violating time-dependent dielectric breakdown (TDDB) reliability specifications (§0045).
Using back-gate biasing to adjust threshold voltages and enable different operating voltages is a known technique in the semiconductor arts, as evidenced by Al-Shyoukh's detailed explanation of forward and reverse back biasing effects (§0032).
Claims 8, 17 and 18 are rejected under 35 U.S.C. § 103 as being unpatentable over Zhou.
Claims 8, 17 and 18 requires explicitly raising the well potential rather than the gate potential. Zhou does not describe active well-bias control independently from gate drive.
But raising the well potential to reduce leakage through body effect is a known leakage-control method in MOS LDO designs (e.g., bulk-switching LDO patents). Please see chapter on Optimum Reverse Body Biasing for Leakage Minimization, by Jayakumar et. al. of the book Minimizing and Exploiting Leakage in VLSI Design published online on 20 October 2009 by Springer, pp. 91-100. Also see page 20-22 of the lecture note of R. Saleh, “Leakage and Low-Power Design”, University of British Columbia as a teaching reference.
This technique is commonly used to minimize leakage current, which can contribute to power dissipation, especially at lower threshold voltages. By increasing the threshold voltage (VT) of the device, the body effect can be effectively managed, leading to a reduction in leakage current. This method is particularly useful in low-voltage and area-constrained LDO designs, where minimizing leakage is crucial for energy efficiency and performance.
A POSITA would find it obvious before the effective filing date of the invention to include standard well-bias control techniques in Zhou as is well-known in the art to reduce leakage through body effect and thereby teaching all limitations of claim 8, 17 and 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.