DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hatano (WO 2020071185 A1).
Regarding claim 1, Hatano teaches:
A semiconductor device [A1, paragraph [0013-0015], [0022], Fig. 1-11; A6, Fig. 27-28] comprising:
a conductive substrate [22, paragraph [0023-0033], Fig. 1-11, 27-28] including an obverse surface [221, paragraph [0030-0033], Fig. 1-11, 27-28] facing a first side in a thickness direction [z] and a reverse surface facing away from the obverse surface [221, Fig. 1-11, 27-28];
a plurality of first semiconductor elements [10B, paragraph [0022], [0024] Fig. 1-11, 27-28] electrically bonded to the obverse surface [221, paragraph [0031], Fig. 1-11, 27-28] and having a switching function;
a first terminal [422, paragraph [0046-0048], [0062-0063], Fig. 1-11, 27-28] disposed on a first side in a first direction [x] orthogonal to the thickness direction [z] with respect to the conductive substrate [22, Fig. 1-11, 27-28]; and
a first conductive member [421, paragraph [0046-0047], Fig. 1-11, 27-28] constituting a path for a main circuit current switched by the plurality of first semiconductor elements [10B, paragraph [0022], [0028], Fig. 1-11, 27-28] and connected to the plurality of first semiconductor elements [10B, paragraph [0047], [0061], [0104], Fig. 1-11, 27-28] and the first terminal [422, paragraph [0046-0047], Fig. 1-11, 27-28], wherein
the first conductive member [421, Fig. 1-11, 27-28] includes a first wiring portion [corresponds to 421, Fig. 1-11, 27-28] and a second wiring portion [421a, Fig. 1-11, 27-28],
the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] includes a first end connected to the first terminal [422, Fig. 1-11, 27-28] and a second end spaced apart from the first end in the first direction [x],
the second wiring portion [421a, Fig. 1-11, 27-28] is connected to the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] between the first end and the second end,
the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] includes a first part located between a first connecting part [where 421a connects to 421] at which the second wiring portion [421a, Fig. 1-11, 27-28] is connected to the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] and the first end, and a second part located between the first connecting part [where 421a connects to 421] and the second end, and [not given specific numbers, can be seen in Fig. 3, 27]
a first dimension [length of 421a in the y-direction is thicker than length of 421b in the y-direction, Fig. 1-11, 27-28] that is a size of the first part in a direction orthogonal to a flow direction of the main circuit current is larger than a second dimension that is a size of the second part in a direction orthogonal to the flow direction of the main circuit current.
Regarding claim 2, Hatano teaches:
The semiconductor device [A1, Fig. 1-11; A6, Fig. 27-28] according to claim 1, wherein the first conductive member [421, paragraph [0042], [0046], Fig. 1-11, 27-28] comprises a plate made of a metal,
the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] extends in the first direction [x], and
the second wiring portion [421a, Fig. 1-11, 27-28] includes a first band portion [421a, Fig. 1-11, 27-28] extending from the first connecting part [where 421a connects to 421] in a second direction [y] orthogonal to the thickness direction [z] and the first direction [x].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hatano (WO 2020071185 A1) as applied to claim 2 above, and further in view of Tani et al. (US 20210125903 A1).
Regarding claim 3, Hatano teaches the semiconductor device according to claim 2.
Hatano further teaches:
further comprising a second terminal [41, paragraph [0013], [0144-0147], Fig. 1-11, 27-28], wherein
the first wiring portion [corresponds to 421, Fig. 1-11, 27-28] is located on a first side in the second direction [y] with respect to the first band portion [421a, Fig. 1-11, 27-28], located on a second side in the second direction [y] with respect to the first band portion [421a, Fig. 1-11, 27-28] and extending in the first direction [x],
the second terminal [41, Fig. 1-11, 27-28] is disposed on the first side in the first direction [x] with respect to the conductive substrate [22, Fig. 1-11, 27-28].
Hatano does not teach:
a third wiring portion
the third wiring portion being connected to the second terminal, the third wiring portion includes a third end connected to the second terminal and a fourth end spaced apart from the third end in the first direction,
the first band portion is connected to the third wiring portion between the third end and the fourth end,
the third wiring portion includes a third part located between a second connecting part and the third end and a fourth part located between the second connecting part and the fourth end, the second connecting part being a part at which the first band portion is connected to the third wiring portion, and
a third dimension that is a size of the third part in a direction orthogonal to a flow direction of the main circuit current is larger than a fourth dimension that is a size of the fourth part in a direction orthogonal to the flow direction of the main circuit current.
Tani et al. teaches:
a third wiring portion [12, paragraph [0038-0040], Fig. 6]
the third wiring portion [12, Fig. 6] being connected to the second terminal [12a, 12b, paragraph [0038-0040], Fig. 6], the third wiring portion [12, Fig. 6] includes a third end connected to the second terminal [12a, 12b, Fig. 6] and a fourth end spaced apart from the third end in the first direction [left/right, Fig. 6],
the first band portion is connected to the third wiring portion [12, Fig. 6] between the third end and the fourth end,
the third wiring portion [12, Fig. 6] includes a third part located between a second connecting part [where the vertical extension of 12 connects to the horizontal extension connected to 12a, Fig. 6] and the third end and a fourth part located between the second connecting part [where the vertical extension of 12 connects to the horizontal extension connected to 12a, Fig. 6] and the fourth end, the second connecting part [where the vertical extension of 12 connects to the horizontal extension connected to 12a, Fig. 6] being a part at which the first band portion is connected to the third wiring portion [12, Fig. 6], and
a third dimension [in the vertical direction, length of vertical extension of 12 is thicker than the horizontal extension of 12 connected to 12a, Fig. 6] that is a size of the third part in a direction orthogonal to a flow direction of the main circuit current is larger than a fourth dimension [in the vertical direction, length of horizontal extension of 12 connected to 12a, Fig. 6] that is a size of the fourth part in a direction orthogonal to the flow direction of the main circuit current.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tani et al. into the teachings of Hatano to include the a third wiring portion, the third wiring portion being connected to the second terminal, the third wiring portion includes a third end connected to the second terminal and a fourth end spaced apart from the third end in the first direction, the first band portion is connected to the third wiring portion between the third end and the fourth end, the third wiring portion includes a third part located between a second connecting part and the third end and a fourth part located between the second connecting part and the fourth end, the second connecting part being a part at which the first band portion is connected to the third wiring portion, and a third dimension that is a size of the third part in a direction orthogonal to a flow direction of the main circuit current is larger than a fourth dimension that is a size of the fourth part in a direction orthogonal to the flow direction of the main circuit current, for the purpose of multiple input terminals for external connections, enables more complex operations, suppress variation in currents flowing through semiconductor elements, and thus to enable size reduction of the semiconductor elements, thereby to achieve size reduction and cost reduction of a semiconductor power module.
Regarding claim 4, Hatano and Tani et al. teach the semiconductor device according to claim 3.
Hatano further teaches:
wherein the second wiring portion [421a, Fig. 1-11, 27-28] includes at least one second band portion [421b, paragraph [0047], Fig. 1-11, 27-28] connected to the first band portion [421a, Fig. 1-11, 27-28] and extending from the first band portion [421a, Fig. 1-11, 27-28] toward a second side in the first direction [x].
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hatano (WO 2020071185 A1) in view of Tani et al. (US 20210125903 A1) as applied to claim 4 above, and further in view of Takahashi et al. (US 20100003585 A1).
Regarding claim 5, Hatano and Tani et al. teach the semiconductor device according to claim 4.
Hatano and Tani et al. do not teach:
wherein the first part includes a first main section located on a first side in the thickness direction with respect to the obverse surface and a first extension connected to the first main section on the first side in the second direction,
the first main section is parallel to the obverse surface and overlaps with the second part as viewed in the first direction,
the third part includes a second main section located on the first side in the thickness direction with respect to the obverse surface and a second extension connected to the second main section on the second side in the second direction, and
the second main section is parallel to the obverse surface and overlaps with the fourth part as viewed in the first direction.
Takahashi et al. teaches:
wherein the first part [61, paragraph [0094-0099], [0128], Fig. 10-12, 19, 23] includes a first main section [6102, paragraph [0096], Fig. 10-12, 19, 23] located on a first side in the thickness direction with respect to the obverse surface and a first extension [6104, paragraph [0096-0099], Fig. 10-12, 19, 23] connected to the first main section [6102, Fig. 10-12, 19, 23] on the first side in the second direction,
the first main section [6102, Fig. 10-12, 19, 23] is parallel to the obverse surface and overlaps with the second part [other end of 6102, Fig. 10-12, 19, 23] as viewed in the first direction,
the third part [65, paragraph [0113-0114], [0119-0124], [0128], Fig. 10-12, 19, 22] includes a second main section [6502, paragraph [0119], Fig. 10-12, 19, 22] located on the first side in the thickness direction with respect to the obverse surface and a second extension [6504, paragraph [0119-0121], Fig. 10-12, 19, 22] connected to the second main section [6502, Fig. 10-12, 19, 22] on the second side in the second direction, and
the second main section [6502, Fig. 10-12, 19, 22] is parallel to the obverse surface and overlaps with the fourth part [other end of 6502, Fig. 10-12, 19, 22] as viewed in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Takahashi et al. into the teachings of Hatano and Tani et al. to include wherein the first part includes a first main section located on a first side in the thickness direction with respect to the obverse surface and a first extension connected to the first main section on the first side in the second direction, the first main section is parallel to the obverse surface and overlaps with the second part as viewed in the first direction, the third part includes a second main section located on the first side in the thickness direction with respect to the obverse surface and a second extension connected to the second main section on the second side in the second direction, and the second main section is parallel to the obverse surface and overlaps with the fourth part as viewed in the first direction, for the purpose of electrically connect features within the device, increase density, and control input and output, voltage and current.
Regarding claim 6, Hatano, Tani et al. and Takahashi et al. teach the semiconductor device according to claim 5.
Hatano, Tani et al. and Takahashi et al. disclose the above claimed subject matter.
However, Hatano, and Takahashi et al. do not teach:
wherein the first part and the third part overlap with the first band portion as viewed in the second direction.
Tani et al. teaches:
wherein the first part [horizontal extension of 12 connected to 12b, Fig. 6] and the third part [horizontal extension of 12 connected to 12a, Fig. 6] overlap with the first band portion [vertical extension of 12 connected to horizontal extension of 12 connected to 12a and 12b, Fig. 6] as viewed in the second direction [vertical, Fig. 6].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tani et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include wherein the first part and the third part overlap with the first band portion as viewed in the second direction, for the purpose of multiple input terminals for external connections, enables more complex operations, suppress variation in currents flowing through semiconductor elements, and thus to enable size reduction of the semiconductor elements, thereby to achieve size reduction and cost reduction of a semiconductor power module.
Regarding claim 7, Hatano, Tani et al. and Takahashi et al. teach the semiconductor device according to claim 5.
Hatano, Tani et al. and Takahashi et al. disclose the above claimed subject matter.
However, Hatano, and Tani et al. do not teach:
wherein the first extension bends from the first main section and extends toward a second side in the thickness direction, and
the second extension bends from the second main section and extends toward the second side in the thickness direction.
Takahashi et al. teaches:
wherein the first extension [6104, Fig. 10-12, 19, 23] bends from the first main section [6102, Fig. 10-12, 19, 23] and extends toward a second side in the thickness direction, and
the second extension bends [6504, Fig. 10-12, 19, 22] from the second main section [6502, Fig. 10-12, 19, 22] and extends toward the second side in the thickness direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Takahashi et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include wherein the first extension bends from the first main section and extends toward a second side in the thickness direction, and the second extension bends from the second main section and extends toward the second side in the thickness direction, for the purpose of electrically connect features within the device, increase density, and control input and output, voltage and current.
Regarding claim 8, Hatano, Tani et al. and Takahashi et al. teach the semiconductor device according to claim 7.
Hatano, Tani et al. and Takahashi et al. disclose the above claimed subject matter.
However, Hatano, and Takahashi et al. do not teach:
wherein the first main section and the second main section overlap with the conductive substrate as viewed in the thickness direction.
Tani et al. teaches:
wherein the first main section [horizontal extension of 12 connected to 12a, Fig. 6-7] and the second main section [horizontal extension of 12 connected to 12b, Fig. 6-7] overlap with the conductive substrate [10, paragraph [0038-0039], [0044], Fig. 6-7] as viewed in the thickness direction [vertical, Fig. 7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tani et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include wherein the first main section and the second main section overlap with the conductive substrate as viewed in the thickness direction, for the purpose of increasing density, promoting symmetry, easier to manufacture.
Hatano, Tani et al. and Takahashi et al. disclose the above claimed subject matter.
However, Hatano, and Tani et al. do not teach:
the first extension and the second extension do not overlap with the conductive substrate as viewed in the thickness direction.
Takahashi et al. teaches:
the first extension [6104, Fig. 10-12, 19, 23] and the second extension [6504, Fig. 10-12, 19, 22] do not overlap with the conductive substrate [40A, 40B, Fig. 10-12, 19] as viewed in the thickness direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Takahashi et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include the first extension and the second extension do not overlap with the conductive substrate as viewed in the thickness direction, for the purpose of electrically connect features within the device, increase density, and control input and output, voltage and current.
Regarding claim 9, Hatano, Tani et al. and Takahashi et al. teach the semiconductor device according to claim 8.
Hatano, Tani et al. and Takahashi et al. disclose the above claimed subject matter.
However, Hatano, and Tani et al. do not teach:
wherein the first extension and the second extension overlap with the conductive substrate as viewed in the second direction.
Takahashi et al. teaches:
wherein the first extension [6104, Fig. 10-12, 19, 23] and the second extension [6504, Fig. 10-12, 19, 22] overlap with the conductive substrate [40A, 40B, Fig. 10-12, 19] as viewed in the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Takahashi et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include wherein the first extension and the second extension overlap with the conductive substrate as viewed in the second direction, for the purpose of electrically connecting features within the device, increase density, and control input and output, voltage and current.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hatano (WO 2020071185 A1) in view of Tani et al. (US 20210125903 A1) and Takahashi et al. (US 20100003585 A1) as applied to claim 8 above, and further in view of Wakimoto et al. (US 20160336580 A1).
Regarding claim 10, Hatano, Tani et al. and Takahashi et al. teach the semiconductor device according to claim 8.
Hatano further teaches:
a support substrate [20, paragraph [0013], [0023-0025], Fig. 1-11, 27-28] which includes a support surface [211, paragraph [0027-0028], [0030-0031], [0079], Fig. 1-11, 27-28] facing the first side in the thickness direction [z] and to which the conductive substrate [22, Fig. 1-11, 27-28] is bonded such that the reverse surface [bottom of 22, Fig. 1-11, 27-28] faces the support surface [211, Fig. 1-11, 27-28]; and
a sealing resin [7, paragraph [0027], [0047-0048], [0059], [0075], Fig. 1-11, 27-28] including a resin obverse surface [71, paragraph [0075-0076], Fig. 1-11, 27-28] facing a same side as the obverse surface [221, Fig. 1-11, 27-28] and a resin reverse surface [72, paragraph [0075-0077], Fig. 1-11, 27-28] facing away from the resin obverse surface [71, Fig. 1-11, 27-28], the sealing resin [7, Fig. 1-11, 27-28] covering at least a part of the support substrate [20, Fig. 1-11, 27-28], at least a part of the conductive substrate [22, Fig. 1-11, 27-28], the plurality of first semiconductor elements [10B, Fig. 1-11, 27-28], and the first conductive member [421, Fig. 1-11, 27-28].
Hatano, Tani et al. and Takahashi et al. do not teach:
the first main section includes a first opening located on the second side in the second direction with respect to the first extension as viewed in the thickness direction, and
the second main section includes a second opening located on the first side in the second direction with respect to the second extension as viewed in the thickness direction.
Wakimoto et al teaches:
the first main section [6b, paragraph [0067-0070], [0800-0082], [0086-0088], Fig. 13-16] includes a first opening [6z, paragraph [0068-0070], [0074-0076], Fig. 13-16] located on the second side [66a, Fig. 13-16] in the second direction with respect to the first extension [6c, paragraph [0067], Fig. 13-16] as viewed in the thickness direction, and
the second main section [6b, paragraph [0067-0070], [0800-0082], [0086-0088], Fig. 13-16] includes a second opening [6z, paragraph [0068-0070], [0074-0076], Fig. 13-16] located on the first side in the second direction with respect to the second extension as viewed in the thickness direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wakimoto et al. into the teachings of Hatano, Tani et al. and Takahashi et al. to include the first main section includes a first opening located on the second side in the second direction with respect to the first extension as viewed in the thickness direction, and the second main section includes a second opening located on the first side in the second direction with respect to the second extension as viewed in the thickness direction, for the purpose of fixing features to each other, preventing cracking and damage. See also, MPEP 2144.04 (IV)(A) Changes in Size/Proportion, MPEP 2144.04 (VI)(B) Duplication of Parts, and MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Regarding claim 11, Hatano, Tani et al., Takahashi et al. and Wakimoto et al. teach the semiconductor device according to claim 10.
Wakimoto et al. further teaches:
wherein the first opening [6z, paragraph [0068-0070], [0074-0076], Fig. 13-16] is an arcuate notch recessed in the first main section [6b, Fig. 13-16] from an end on the second side in the second direction toward the first side in the second direction,
the first extension [6c, paragraph [0067], Fig. 13-16] hangs out of the first side in the second direction of the first main section [6b, Fig. 13-16] to have an arcuate shape,
the second opening [6z, paragraph [0068-0070], [0074-0076], Fig. 13-16] is an arcuate notch recessed in the second main section [6b, Fig. 13-16] from an end on the first side in the second direction toward the second side in the second direction, and
the second extension [6c, paragraph [0067], Fig. 13-16] hangs out of the second side in the second direction of the second main section [6b, Fig. 13-16] to have an arcuate shape.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hatano (WO 2020071185 A1) in view of Tani et al. (US 20210125903 A1) as applied to claim 4 above, and further in view of Kanda (JP 2020080348 A).
Regarding claim 12, Hatano and Tani teach the semiconductor device according to claim 4.
Hatano further teaches:
wherein the plurality of first semiconductor elements [10B, Fig. 1-11, 27-28] are spaced apart from each other in the second direction [y].
Hatano and Tani et al. do not teach:
the first conductive member includes a fourth wiring portion connected to the second end and the fourth end and extending in the second direction,
the fourth wiring portion is connected to the plurality of first semiconductor elements, and
an end on the second side in the first direction of the second band portion is connected to the fourth wiring portion.
Kanda teaches:
the first conductive member [321, paragraph [0036-0037], [0057], [0107], Fig. 3, 17, 25, 27] includes a fourth wiring portion [72, paragraph [0106-0107], Fig. 25] connected to the second end and the fourth end and extending in the second direction [y],
the fourth wiring portion [72, Fig. 25] is connected to the plurality of first semiconductor elements [42, paragraph [0057], [0106-0107], Fig. 17, 25], and
an end on the second side in the first direction [x] of the second band portion [321b, paragraph [0057], [0107], Fig. 17, 25] is connected to the fourth wiring portion [72, Fig. 25].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kanda into the teachings of Hatano and Tani et al. to include the first conductive member includes a fourth wiring portion connected to the second end and the fourth end and extending in the second direction, the fourth wiring portion is connected to the plurality of first semiconductor elements, and an end on the second side in the first direction of the second band portion is connected to the fourth wiring portion, for the purpose of electrically connect features within the device, and improving heat dissipation.
Regarding claim 13, Hatano, Tani et al. and Kanda teach the semiconductor device according to claim 12.
Hatano further teaches:
wherein the conductive substrate [22, Fig. 1-11, 27-28] includes a first conductive portion [22B, paragraph [0023-0024], [0029-0032], Fig. 1-11, 27-28] and a second conductive portion [22A, paragraph [0023-0024], [0029-0032], Fig. 1-11, 27-28] disposed on the second side and on the first side, respectively, in the first direction [x] in a mutually spaced manner,
the plurality of first semiconductor elements [10B, Fig. 1-11, 27-28] are electrically bonded to the first conductive portion [22B, Fig. 1-11, 27-28], and
the semiconductor device [A1, Fig. 1-11; A6, Fig. 27-28] further includes: a third terminal [43, paragraph [0013], [0049-0052], [0093], Fig. 1-11, 27-28] connected to the first conductive portion [22B, Fig. 1-11, 27-28];
a plurality of second semiconductor elements [10A, paragraph [0022], Fig. 1-11, 27-28] electrically bonded to the second conductive portion [22A, Fig. 1-11, 27-28] and having a switching function;
a second conductive member [51, paragraph [0013], [0031], [0040], [0064-0069], Fig. 1-11, 27-28] connected to the plurality of second semiconductor elements [10A, Fig. 1-11, 27-28] and the first conductive portion [22B, Fig. 1-11, 27-28] and comprising a plate made of a metal; and
a fourth terminal [47A, Fig. 1-11, 27-28] connected to the second conductive portion [22A, Fig. 1-11, 27-28].
Regarding claim 14, Hatano, Tani et al. and Kanda teach the semiconductor device according to claim 13.
Hatano further teaches:
wherein the second conductive member [51, Fig. 28] overlaps with the second band portion [421b, Fig. 28] as viewed in the thickness direction [z].
Regarding claim 15, Hatano, Tani et al. and Kanda teach the semiconductor device according to claim 14,
Hatano further teaches:
wherein the plurality of second semiconductor element [10A, Fig. 1-11, 27-28] are spaced apart from each other in the second direction [y], and
the plurality of first semiconductor elements [10B, Fig. 1-11, 27-28] and the plurality of second semiconductor elements [10A, Fig. 1-11, 27-28].
Hatano, Tani et al. and Kanda disclose the above claimed subject matter.
However, Hatano and Kanda do not teach:
the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other as viewed in the first direction.
Tani et al. teaches:
the plurality of first semiconductor elements [22b(2b), 22c(2c), paragraph [0025-0027], [0038-0039], Fig. 2-6] and the plurality of second semiconductor elements [22a(2a), 22d(2d), paragraph [0025-0027], [0038-0039], Fig. 2-6] overlap with each other as viewed in the first direction [horizontal].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tani et al. into the teachings of Hatano, Tani et al. and Kanda to include the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other as viewed in the first direction, for the purpose of promoting symmetry, reducing the difference among the current path lengths, easier to manufacture, variation in currents at the time of current conduction in the forward direction of the device can be reduced, no electric resistance difference between the semiconductor elements, the electric resistance in the signal transmission path is reduced and the signal transmission speed increases, whereby control ability is improved.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 04/28/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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