DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the center of the channel being a line halfway between a boundary of the channel and the first connection portion and a boundary of the channel and the second connection portion” of amended dependent claim 6 and “the gate electrode comprises tapered edges that, from a cross-sectional view, define lines that converge above the gate electrode” and “the second active layer comprises tapered edges at distal ends of the channel that, from the cross-sectional view, define lines that diverge above the second active layer” of amended dependent claim 17 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the Examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6, 17, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Regarding dependent claim 6, Applicant has amended dependent claim 6 to include the recited limitation of “the center of the channel being a line halfway between a boundary of the channel and the first connection portion and a boundary of the channel and the second connection portion.” Page eight (8) of the “Amendment Under 37 C.F.R. §1.111” filed on April 7, 2026 (hereinafter the “Response”) states: “Support for the changes to the claims is found in the disclosure as originally filed including FIGS. 1A and 1B, and related portions of the specification.” However, the Examiner can find no discussion of the center of the channel being a line halfway between a boundary of the channel and the first connection portion and a boundary of the channel and the second connection portion in Applicant’s originally filed application. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention.
Regarding dependent claim 17, Applicant has amended dependent claim 17 to include the recited limitations of “the gate electrode comprises tapered edges that, from a cross-sectional view, define lines that converge above the gate electrode” and “the second active layer comprises tapered edges at distal ends of the channel that, from the cross-sectional view, define lines that diverge above the second active layer”. Page eight (8) of the “Amendment Under 37 C.F.R. §1.111” filed on April 7, 2026 (hereinafter the “Response”) states: “Support for the changes to the claims is found in the disclosure as originally filed including FIGS. 1A and 1B, and related portions of the specification.” However, the Examiner can find no discussion of tapered edges of the gate electrode that, from a cross-sectional view, define lines that converge above the gate electrode or tapered edges of the second active layer at distal ends of the channel that, from a cross-sectional view, define lines that diverge above the second active layer in Applicant’s originally filed application. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention.
Regarding independent claim 20, Applicant has amended independent claim 20 to include the recited limitation of “treating a first connection portion and a second connection portion of the active layer not overlapping the gate electrode to be conductive such that a channel of the active layer overlapped by the gate electrode remains between the first connection portion and the second connection portion”. Page eight (8) of the Response states: “Support for the changes to the claims is found in the disclosure as originally filed including FIGS. 1A and 1B, and related portions of the specification.” However, the Examiner can find no discussion of treating a first connection portion and a second connection portion of the active layer not overlapping the gate electrode to be conductive such that a channel of the active layer overlapped by the gate electrode remains between the first connection portion and the second connection portion in Applicant’s originally filed application. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, lines 3-5 recite: “the center of the channel being a line halfway between a boundary of the channel and the first connection portion and a boundary of the channel and the second connection portion.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meanings of the recitation of a “the center of the channel being a line” is unclear because they not defined by the claim, the specification (including the drawings) does not provide a standard for ascertaining the meaning of these recited limitations, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 3-5 of claim 6 as reciting: “and further wherein the center of the channel is halfway between a boundary of the channel and the first connection portion and a boundary of the channel and the second connection portion” because of this ambiguity.
Regarding claim 17, lines 1-5 recite: “wherein the gate electrode comprises tapered edges that, from a cross-sectional view, define lines that converge above the gate electrode, and wherein the second active layer comprises tapered edges at distal ends of the channel that, from the cross-sectional view, define lines that diverge above the second active layer.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meanings of the recitations of a “tapered edges that, from a across-sectional view, define lines that converge above the gate electrode” and “tapered edges at distal ends of the channel that, from the cross-sectional view, define lines that diverge above the second active layer” are unclear because they not defined by the claim, the specification (including the drawings) does not provide a standard for ascertaining the meaning of these recited limitations, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 1-5 of claim 17 as reciting: “wherein the gate electrode comprises tapered edges, and further wherein the second active layer comprises tapered edges at distal ends of the channel” because of this ambiguity.
Regarding claim 20, lines 5-8 recite: “treating a first connection portion and a second connection portion of the active layer not overlapping the gate electrode to be conductive such that a channel of the active layer overlapped by the gate electrode remains between the first connection portion and the second connection portion”. This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, it is unclear how the “first connection portion and a second connection portion of the active layer not overlapping the gate electrode” are treated “to be conductive such that a channel of the active layer overlapped by the gate electrode remains between the first connection portion and the second connection portion ” because this step is not defined by the claim, the specification (including the drawings) does not provide a standard for ascertaining the meaning of this recited limitation, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 5-8 of claim 20 as reciting: “forming a first connection portion and a second connection portion of the active layer that do not overlap the gate electrode, wherein a channel of the active layer overlapped by the gate electrode remains between the first connection portion and the second connection portion” because of this ambiguity.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d), as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 19 recites: A display apparatus comprising a pixel, the pixel including the thin film transistor of claim 1.
MPEP 608.01(n)(III) provides that “a claim in dependent form shall contain:
a reference to a claim previously set forth, and
then specify a further limitation of the subject matter claimed” (emphasis added).
Regarding claim 19, there is no further limitation of the subject matter claimed then specified after the reference to previously set forth claim 1. Rather, the further limitation of the subject matter claimed appears before the reference to claim 1. Therefore, claim 19 is not in correct form as required by MPEP 608.01(n)(III). Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8, 9, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148558 A1 (Suzuki) in view of US 2014/0103337 A1 (Yamazaki).
Regarding claim 1, Suzuki discloses, A thin film transistor (thin film transistor (203); FIG. 6; [0080]) comprising:
a substrate (substrate (101); FIG. 6; [0022]);
an active layer (active layer (107); FIG. 6; [0022]) on a main surface (first annotated FIG. 6, below) of the substrate (101), the active layer including a channel (channel (107A); FIG. 6; [0025]), a first connection portion (first connection portion (107d); FIG. 6; [0028]) and a second connection portion (second connection portion (107s); FIG. 6; [0028]) contacting opposite sides of the channel (107A) (FIG. 6); and
a gate electrode (gate electrode (103 and/or 112); FIG. 6; [0022]) overlapping the channel (107A) of the active layer (107),
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wherein the active layer (107) includes:
a first active layer (first active layer (107A); FIG. 6; [0025]);
a second active layer (second active layer (107i); FIG. 6; [0080]) on the first active layer (107A) in the first connection portion (107d) and the second connection portion (107s) of the active layer (107); and
a third active layer (third active layer (107B); FIG. 6; [0025]) contacting the first active layer (107A) in the channel (107A) and contacting the second active layer (107i) in the first connection portion (107d) and the second connection portion (107s),
wherein a bottom surface (first annotated FIG. 6, above) of the active layer (107) faces the main surface of the substrate (101).
But, Applicant may argue that Suzuki does not appear to explicitly disclose, wherein the channel of the active layer is thinner in a direction perpendicular to the main surface of the substrate than the first connection portion and the second connection portion.
However, in analogous art, Yamazaki discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a thin film transistor (FIG. 1B) may be predicably fabricated to include a substrate (substrate (400); FIG. 1B; [0134]) having a main surface (annotated FIG. 1B, below), an active layer (active layer (404); FIG. 1B; [0055]) that includes a channel (annotated FIG. 1B, below), a first connection portion (annotated FIG. 1B, below), and a second connection portion (annotated FIG. 1B, below) contacting opposite sides channel (annotated FIG. 1B, below). Yamazaki also discloses that the active layer (404) includes a first active layer (first active layer (404a; FIG. 1B; [0055]), a second active layer (second active layer (404c; FIG. 1B; [0055]), and a third active layer (third active layer (404b; FIG. 1B; [0055]). Yamazaki additionally discloses a gate electrode (gate electrode (412); FIG. 1B; [0134]) overlapping the channel (annotated FIG. 1B, below) of the active layer (404) and a gate insulating layer (gate insulating layer (410); FIG. 1B; [0134]). Yamazaki further discloses that the channel (annotated FIG. 1B, below) of the active layer (404) can be predicably fabricated to be thinner in a direction perpendicular to the main surface (annotated FIG. 1B, below) of the substrate (400) than the first connection portion (annotated FIG. 1B, below) and the second connection portion (annotated FIG. 1B, below) so that the channel (annotated FIG. 1B, below) is not in contact with gate insulating layer (410) ([0066]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Suzuki and Yamazaki before him/her that the channel (107A) of the active layer (107) of Suzuki can be predicably fabricated to be thinner in a direction perpendicular to the main surface (first annotated FIG. 6, above) of the substrate (101), as taught by Yamazaki, than the first connection portion (107d) and the second connection portion (107s) of Suzuki, as also taught by Yamazaki, with no change in the function of channel (107A) because it would continue to operate as the channel of thin film transistor (203) of Suzuki and/or so that the channel (107A) is not in contact with gate insulating layer (gate insulating layer (109); FIG. 6; [0022]) of Suzuki, as additionally taught by Yamazaki. Please see, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods To Yield Predicable Results. Please also see, MPEP 2144(IV)—The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.
Regarding claim 2, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the second active layer (107i) includes a plurality of portions (first annotated FIG. 6, above), each portion (first annotated FIG. 6, above) of the second active layer (107i) including a lower surface (first annotated FIG. 6, above) facing the substrate (101), an upper surface (first annotated FIG. 6, above) opposing the lower surface (first annotated FIG. 6, above), and a side surface (first annotated FIG. 6, above) connecting the lower surface (first annotated FIG. 6, above) and the upper surface (first annotated FIG. 6, above), and
wherein each portion (first annotated FIG. 6, above) of the second active layer (107i) is spaced apart (source electrode (113) and drain electrode (114);FIG. 6; [0022], all of Suzuki, provide such spacing)) from every other portion (first annotated FIG. 6, above) of the second active layer (107i).
Regarding claim 3, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the first active layer ((404a) of Yamazaki) and the third active layer ((404b) of Yamazaki) directly contact each other in an area of the channel (annotated FIG. 1B, above).
Regarding claim 4, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the first active layer (107A) and the third active layer (107B) contact each other at a first boundary (first annotated FIG. 6, above) between the channel (107A) and the first connection portion (107d) and at a second boundary (first annotated FIG. 6, above) between the channel (107A) and the second connection portion (107s).
Regarding claim 5, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein a thickness of the active layer (107) is reduced (second annotated FIG. 6, below) such that a topmost surface of the third active layer (107B) is inclined with respect to the main surface (second annotated FIG. 6, below) of the substrate (101) at a boundary between the channel (107A) and the first connection portion (107d).
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Regarding claim 6, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein a thickness of the active layer (404 of Yamazaki) in the direction perpendicular to the main surface (annotated FIG. 1B, above) of the substrate (400 of Yamazaki) is thinner at a center of the channel (annotated FIG. 1B, above) than the first connection portion (annotated FIG. 1B, above), the center of the channel (annotated FIG. 1B, above) being a line halfway between a boundary of the channel (annotated FIG. 1B, above) and the first connection portion (annotated FIG. 1B, above) and a boundary of the channel (annotated FIG. 1B, above) and the second connection portion (annotated FIG. 1B, above).1
Regarding claim 8, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the second active layer (107i) is disposed between the first active layer (107A) and the third active layer (107B) at a first boundary (first annotated FIG. 6, above) between the channel (107A) and the first connection portion (107d) (first annotated FIG. 6, above).
Regarding claim 9, Suzuki discloses in view of Yamazaki, The thin film transistor (203) of claim 8, wherein the second active layer (107i) is disposed between the first active layer (107A) and the third active layer (107B) at a second boundary (first annotated FIG. 6, above) between the channel (107A) and the second connection portion (107s) (first annotated FIG. 6, above).
Regarding claim 12, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the third active layer (107B) has a mobility smaller than a mobility of the second active layer (107i) ([0089] of Suzuki).
Regarding claim 14, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the second active layer includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material ([0091] of Suzuki), an IGZTO(InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, or a ZnON (Zn-Oxynitride)-based oxide semiconductor material, and when the oxide semiconductor material included in the second active layer includes gallium (Ga) and indium (In), a concentration of indium (In) is higher than that of gallium (Ga) based on the number of moles [Ga concentration < In concentration].
Regarding claim 15, Suzuki discloses in view of Yamazaki, The thin film transistor (203) of claim 1, wherein the third active layer (107B) includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material ([0115] of Suzuki), an IGZTO (InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, or a ZnON (Zn-Oxynitride)-based oxide semiconductor material, and when the oxide semiconductor material included in the third active layer includes gallium (Ga) and indium (In), a concentration of indium (In) is higher than that of gallium (Ga) based on the number of moles [Ga concentration < In concentration].
Regarding claim 16, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the third active layer (107B) includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material ([0026] of Suzuki), a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the third active layer (107B) includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration] ([0044] of Suzuki).
Regarding claim 17, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, wherein the gate electrode (103 and/or 112) comprises tapered edges (second annotated FIG. 6, above) that, from across-sectional view, define lines that converge above the gate electrode, and
wherein the second active layer (107i) comprises tapered edges at distal ends (second annotated FIG. 6., above) of the channel (107A) that, from the cross-sectional view, define lines that diverge above the second active layer (107i).2
Regarding claim 18, Suzuki in view of Yamazaki discloses, The thin film transistor (203) of claim 1, further comprising:
a buffer layer (buffer layer (105); FIG. 6; [0022], all of Suzuki) on the substrate (101); and
a gate insulation layer (gate insulation layer (109); FIG. 6; [0022], all of Suzuki) on the third active layer (107B) and the buffer layer (105).
Regarding claim 19, Suzuki in view of Yamazaki discloses, A display apparatus ([0018] of Suzuki) comprising a pixel ([0109] of Suzuki), the pixel ([0109] of Suzuki) including the thin film transistor (203) of claim 1.
Regarding claim 20, Suzuki discloses, A method for manufacturing a thin film transistor (thin film transistor (203); FIG. 6; [0080]), the method comprising:
forming an active layer (active layer (107); FIG. 6; [0022]) on a main surface (first annotated FIG. 6, above) of a substrate (substrate (101); FIG. 6; [0022]);
forming a gate electrode (gate electrode (103 and/or 112); FIG. 6; [0022]) at least partially overlapping the active layer (107) (FIG. 6); and
treating a first connection portion (first connection portion (107d); FIG. 6; [0028]) and a second connection portion (second connection portion (107s); FIG. 6; [0028]) of the active layer (107) not overlapping the gate electrode (103 and/or 107) to be conductive such that a channel (channel (107A); FIG. 6; [0025]) of the active layer (107) overlapped by the gate electrode (103 and/or 107) remains between the first connection portion (107d) and the second connection portion (107s),3
wherein the forming the active layer (107) includes:
forming a first active layer (first active layer (107A); FIG. 6; [0025]) on the substrate (101);
forming a second active layer (second active layer (107i); FIG. 6; [0080]) on the first active layer (107A) in the first connection portion (107d) and the second connection portion (107s) of the active layer (107); and
forming a third active layer (third active layer (107B); FIG. 6; [0025]) contacting the first active layer (107A) in the channel (107A) and contacting the second active layer (107i) in the first connection portion (107d) and the second connection portion (107s),
wherein a bottom surface (first annotated FIG. 6, above) of the active layer (107) faces the main surface (first annotated FIG. 6, above) of the substrate (101).
But Applicant may argue that Suzuki does not appear to explicitly disclose, wherein the channel of the active layer is thinner in a direction perpendicular to the main surface of the substrate than the first connection portion and the second connection portion.
However, in analogous art, Yamazaki discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a thin film transistor (FIG. 1B) may be predicably fabricated to include a substrate (substrate (400); FIG. 1B; [0134]) having a main surface (annotated FIG. 1B, above), an active layer (active layer (404); FIG. 1B; [0055]) that includes a channel (annotated FIG. 1b, above), a first connection portion (annotated FIG. 1B, above), and a second connection portion (annotated FIG. 1B, above) contacting opposite sides the channel. Yamazaki also discloses that the active layer (404) includes a first active layer (first active layer (404a; FIG. 1B; [0055]), a second active layer (second active layer (404c; FIG. 1B; [0055]), and a third active layer (third active layer (404b; FIG. 1B; [0055]). Yamazaki additionally discloses a gate electrode (gate electrode (412); FIG. 1B; [0134] overlapping the channel (annotated FIG. 1B, above) of the active layer (404) and a gate insulating layer (gate insulating layer (410); FIG. 1B; [0134]). Yamazaki further discloses that the channel (annotated FIG. 1B, above) of the active layer (404) can be predicably fabricated to be thinner in a direction perpendicular to the main surface (annotated FIG. 1B, above) of the substrate (400) than the first connection portion (annotated FIG. 1B, above) and the second connection portion (annotated FIG. 1B, above) so that the channel (annotated FIG. 1B, above) is not in contact with gate insulating layer (410) ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Suzuki and Yamazaki before him/her that the channel (107A) of the active layer (107) of Suzuki can be predicably fabricated to be thinner in a direction perpendicular to the main surface (first annotated FIG. 6, above) of the substrate (101), as taught by Yamazaki, than the first connection portion (107d) and the second connection portion (107s) of Suzuki, as also taught by Yamazaki, ) with no change in the function of channel (107A) because it would continue to operate as the channel of thin film transistor (203) of Suzuki and/or so that the channel (107A) is not in contact with gate insulating layer (gate insulating layer (109); FIG. 6; [0022]) of Suzuki, as additionally taught by Yamazaki. Please see, MPEP(A), above. Please also see, MPEP 2144(IV), above.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, in view of Yamazaki as applied to claim 1, above, and further in view of US 2016/0247934 A1 (Hanaoka).
Regarding claim 10, Suzuki in view of Yamazaki does not appear to explicitly disclose, wherein the second active layer has a mobility greater than a mobility of the first active layer.
However, in analogous art, Hanaoka discloses that it is well-known that a transistor (FIG. 1B) can be predicably fabricated to include an active layer (active layer (130); FIG. 1B; [0055]) having a first active layer (first active layer (131); FIG. 1B; [0053]), a second active layer (second active layer (132); FIG. 1B; [0053]) on the first active layer (131), and a third active layer (third active layer (133); FIG. 1B; [0053]) contacting first active layer (131) and second active layer (132). Hanaoka also discloses that it is well known that second active layer (132) can be predicably fabricated to have an increased carrier mobility relative to first active layer (131) and third active layer (133) through the addition of one or more chemical elements ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki, Yamazaki, and Hanaoka before him/her that it was well-known that the transistor (203) of Suzuki and Yamazaki can be predicably fabricated so that the second active layer (107i) of Suzuki and Yamazaki has a mobility greater than a mobility of the first active layer (107A) of Suzuki and Yamazaki, as taught by Hanaoka, through the addition of one or more chemical elements to increase the carrier mobility of second active layer (107i) of Suzuki and Yamazaki so that it is greater than the carrier mobility of first active layer (107A) of Suzuki and Yamazaki, as also taught by Hanaoka, with no change in the respective functions of first active layer (107A) or second active layer (107i) because they would continue to operate as the respective first and second active layers (107A and 107i) of active layer (107) of Suzuki and Yamazaki. See, MPEP 2143(A), above.
Regarding claim 13, Suzuki in view of Yamazaki does not appear to explicitly disclose, wherein the first active layer includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)- based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the first active layer includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration].4
However, in analogous art, Hanaoka discloses that it is well-known that a transistor (FIG. 1B) can be predicably fabricated to include an active layer (active layer (130); FIG. 1B; [0055]) having a first active layer (first active layer (131); FIG. 1B; [0053]), a second active layer (second active layer (132); FIG. 1B; [0053]) on the first active layer (131), and a third active layer (third active layer (133); FIG. 1B; [0053]) contacting first active layer (131) and second active layer (132). Hanaoka also discloses that it is well known that first active layer (131) can be predicably fabricated from an IGZO (InGaZnO)-based oxide semiconductor material whose atomic ratio of In to Ga and Zn can be 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4, or 1:9:6 ([0100]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki, Yamazaki, and Hanaoka before him/her that it was well-known that the transistor (203) of Suzuki and Yamazaki can be predicably fabricated so that the first active layer (107A) of Suzuki and Yamazaki includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, as taught by Hanaoka, a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)- based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the first active layer includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration], as also taught by Hanaoka, with no change in the respective function of first active layer (107A) because it would continue to operate as the first active layer (107A) of active layer (107) of Suzuki and Yamazaki. See, MPEP 2143(A), above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Yamazaki, as applied to claim 1, above, in view of US 2020/0052116 A1 (Kim).
Regarding claim 11, Suzuki in view of Yamazaki does not appear to explicitly disclose, wherein the third active layer has a mobility greater than a mobility of the first active layer.
However, in analogous art, Kim discloses that it is well-known that a semiconductor device (FIG. 6) can be predicably fabricated to include a first active layer (first active layer (110a); FIG. 6; [0034]), a second active layer (second active layer (110b); FIG. 6; [0053]), and a third active layer (third active layer (110c); FIG. 6; [0062]). Kim also discloses that first active layer (110a) may be fabricated of silicon ([0036]) and that second active layer (110b) may also be fabricated of silicon ([0055]). Kim additionally discloses that it is well known that third active layer (110c) can be predicably fabricated to have an increased carrier mobility relative to first active layer (110a) and second active layer (110b) through the addition of one or more chemical elements to silicon, such as germanium ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki, Yamazaki, and Kim before him/her that it was well-known that the transistor (203) of Suzuki and Yamazaki can be predicably fabricated so that the third active layer (107B) of Suzuki and Yamazaki has a mobility greater than a mobility of the first active layer (107A) of Suzuki and Yamazaki, as taught by Kim, through the addition of one or more chemical elements to increase the carrier mobility of third active layer (107B) of Suzuki and Yamazaki so that it is greater than the carrier mobility of first active layer (107A) of Suzuki and Yamazaki, with no change in the respective functions of first active layer (107A) or third active layer (107B) because they would continue to operate as the respective first and third active layers (107A and 107B) of active layer (107) of Suzuki and Yamazaki. See, MPEP 2143(A), above.
Response to Amendments and Arguments
The submission of the English abstract of KR 10-2023-0034837A has not been considered by the Examiner because it was not accompanied by an information disclosure statement in compliance with the provisions of 37 C.F.R. 1.97(c) and 1.98(a)(1) and (b). Applicant’s amendment of dependent claim 17 and remarks on page eight (8) of the Response have been fully considered, but they have not overcome the objection to the drawings, as detailed above in the Final Office Action.
Applicant’s amendments to the specification and remarks on page eight (8) of the Response have overcome the objection to the specification in the Office Action dated January 7, 2026 (hereinafter the “Office Action”). Also, Applicant’s amendment of independent claim 1 and dependent claim 17, as well as the remarks on page nine (9) of the Response, have overcome the objection to claims 17 and 18 in the Office Action.
Applicant’s amendments to claims 2, 17, and 20 and remarks on page nine (9) of the Response regarding the rejection thereof under 35 U.S.C. 112(b) in the Office Action have been fully considered and are persuasive with respect to amended dependent claim 2. However, they have not overcome the rejection of claims 17 and 20 under 35 U.S.C. 112(b), as detailed above in this Final Office Action. Also, Applicant’s amendment to dependent claim 19 and remarks on page nine (9) of the Response regarding the rejection of dependent claim 19 under 35 U.S.C. 112(d) in the Office Action have been fully considered, but they are not deemed persuasive, as detailed above in this Final Office Action.
Applicant’s amendment of independent claims 1 and 20 and remarks on pages nine (9)-eleven (11) of the Response regarding the rejection of claims 1-9, 12, and 14-20 under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0148558 A1 (Suzuki) in the Office Action have been fully considered, but are deemed moot based on the new grounds of rejection of claims 1-6, 8, 9, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of US 2014/0103337 A1 (Yamazaki), as detailed above in this Final Office Action. Also, Applicant’s amendment of dependent claims 2 and 3 and remarks on page 12 of the Response regarding the rejection of claims 2 and 3 under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki in the Office Action have been fully considered, but are not deemed persuasive, as detailed above in this Final Office Action.
Finally, Applicant’s amendment of dependent claims 6 and 17 and independent claim 20 has necessitated rejection thereof under 35 U.S.C. 112(a) in this Final Office Action. The Examiner respectfully requests that Applicant please indicate where the specification specifically contains statements providing support for these amended limitations or, alternatively which portions of the specification provide sufficient detail that one skilled in the art could reasonably conclude that the inventor had possession of the claimed invention as recited in amended dependent claims 6 and 17 and independent claim 20. The Examiner respectfully notes that merely referring to drawings (without annotating such drawings in Applicant’s written response) will be considered inadequate support for such amended limitations.
Notwithstanding the above, to advance prosecution, the Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to overcome rejection of the currently pending claims prior to submitting a written response to this Final Office Action. The Examiner would welcome such a discussion of these proposed claim amendments and is available at the number provided below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 6 under 35 U.S.C. 112(b) for how this recited language of claim 6 is being interpreted for purpose of examination.
2 Please see the rejection of claim 17 under 35 U.S.C. 112(b) for how this recited language of claim 17 is being interpreted for purpose of examination.
3 Please see the rejection of claim 20 under 35 U.S.C. 112(b) for how this recited language of claim 20 is being interpreted for purpose of examination.
4 However, Suzuki does disclose that the first active layer 107A may “contain, for example, an In—Ga—Zn—O-based semiconductor (such as indium gallium zinc oxide). The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions of In, Ga, and Zn (composition ratio) is not particularly limited” ([0113]).
Prosecution Insights