DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDSs) submitted on October 20, 2023; June 24, 2024; and October 28, 2025 were filed before the mailing date of this first Office Action. Except for the IDS submitted on October 20, 2023, the submissions are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the compliant IDSs are being considered by the Examiner. The IDS of October 20, 2023 is noncompliant because no concise explanation of relevance was provided for the non-English language KR 10-2023-0034837A reference. Please see, 37 CFR 1.98(a)(3) and MPEP 609.04(a)(III).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the gate electrodes comprises tapered edges tapering in a first direction” and “wherein the second active layer comprises tapered edges tapering in a second direction opposite to the first direction’’ of claim 17 must be shown or the features canceled from the claim. No new matter should be entered. Currently the drawings appear to show the edges of the gate electrode (150) (see e.g., annotated FIG. 1B, below) tapering in two different directions (first direction and second direction which are illustrated annotated FIG. 1B, below1) and the edges of patterns (132a) (see e.g., annotated FIG. 1B, below) and (132b) of second active layer (132) also tapering in two different directions in that same way as the edges of gate electrode (150), rather than a second direction opposite to the first direction, as recited in claim 17.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the Examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: in paragraphs [0077], [0079], and [0089], “cancan” should be “can”. Appropriate correction is required.
Claim Objections
Claim 17 is objected to because of the following informality: on line 1, “gate electrodes” should be “gate electrode” because independent claim 1, from which claim 17 depends, recites “a gate electrode”. Appropriate correction is required.
Claim 18 is objected to because of the following informality: on line 2, “the substrate” should be “a substrate”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, lines 1-2 recite: “wherein the second active layer includes a plurality of spaced apart island-shaped patterns.” This recited language is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meaning of the recitation of a “island-shaped patterns” is unclear. “Island-shaped patterns” is not defined by the claim, the specification does not provide a standard for ascertaining its meaning, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For example, an island can have any shape. What constitutes “island-shaped patterns” versus patterns that are not “island-shaped”? As another example, it is unclear what is a “pattern” versus what isn’t a “pattern”. Is a “pattern” a template for fabricating another item, a specific configuration, a relationship of component parts, or something else? For purpose of examination, the Examiner is interpreting lines 1-2 of claim 2 as reciting: “wherein the second active layer includes a plurality of spaced apart structures“ because of this ambiguity.
Regarding claim 17, lines 1-4 recite: “wherein the gate electrodes comprises tapered edges tapering in a first direction, and wherein the second active layer comprises tapered edges tapering in a second direction opposite to the first direction”. This recited language is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meanings of the recitations of a “tapered edges tapered in a first direction” and “tapered edges tapering in a second direction opposite to the first direction” are unclear because they not defined by the claim, the specification (including the drawings) does not provide a standard for ascertaining the meaning of these first and second directions (other than they are opposite one another), and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 1-4 of claim 17 as reciting: “wherein the gate electrode comprises tapered edges, and wherein the second active layer comprises tapered edges“ because of this ambiguity.
Regarding claim 20, lines 4-6 recite: “forming a first connection portion and a second connection portion by selectively conductorizing areas of the active layer not overlapping the gate electrode to form a channel by the selective conductorization”. This recited language is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meanings of the recitations of “conductorizing” and “conductorization” are unclear because they are not defined by the claim, the specification does not provide a standard for ascertaining their meanings, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For example, do “conductorizing” and “conductorization” mean adding electrical connectors, pads and/or vias? As another example, it is unclear how “a channel” is formed “by the selective conductorization”. Isn’t a semiconductor channel formed by application of a voltage to a gate rather than “selective conductorization”? For purpose of examination, the Examiner is interpreting lines 4-6 of claim 20 as reciting: “forming a first connection portion and a second connection portion not overlapping the gate electrode“ because of this ambiguity.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d), as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 19 recites: A display apparatus comprising the thin film transistor of claim 1.
MPEP 608.01(n)(III) provides that “a claim in dependent form shall contain:
a reference to a claim previously set forth, and
then specify a further limitation of the subject matter claimed” (emphasis added).
Regarding claim 19, there is no further limitation of the subject matter claimed then specified after the reference to previously set forth claim 1. Rather, the further limitation of the subject matter claimed appears before the reference to claim 1. Therefore, claim 19 is not in correct form as required by MPEP 608.01(n)(III). Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 12, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0148558 A1 (Suzuki).
Regarding claim 1, Suzuki discloses, A thin film transistor (thin film transistor (203); FIG. 6; [0080]) comprising:
an active layer (active layer (107); FIG. 6; [0022]) including a channel (channel (107A); FIG. 6; [0025]), a first connection portion (first connection portion (107d); FIG. 6; [0028]) and a second connection portion (second connection portion (107s); FIG. 6; [0028]) contacting opposite sides of the channel (107A) (FIG. 6); and
a gate electrode (gate electrode (103 and/or 112); FIG. 6; [0022]) overlapping the channel (107A) of the active layer (107),
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wherein the active layer(107) includes:
a first active layer (first active layer (107A); FIG. 6; [0025]);
a second active layer (second active layer (107i); FIG. 6; [0080]) on the first active layer (107A) in the first connection portion (107d) and the second connection portion (107s) of the active layer (107); and
a third active layer (third active layer (107B); FIG. 6; [0025]) contacting the first active layer (107A) in the channel (107A) and contacting the second active layer (107i) in the first connection portion (107d) and the second connection portion (107s).
Regarding claim 2, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the second active layer (107i) includes a plurality of spaced apart island-shaped patterns (first annotated FIG. 6, above).2
Regarding claim 3, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the first active layer (107A) and the third active layer (107B) contact each other in an area of the channel (107A).
Regarding claim 4, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the first active layer (107A) and the third active layer (107B) contact each other at a first boundary (first annotated FIG. 6, above) between the channel (107A) and the first connection portion (107d) and at a second boundary (first annotated FIG. 6, above) between the channel (107A) and the second connection portion (107s).
Regarding claim 5, Suzuki discloses, The thin film transistor (203) of claim 1, wherein a thickness of the active layer (107) is reduced along a direction (second annotated FIG. 6, below) from the first connection portion (107d) toward the channel (107A), centered on a boundary between the channel (107A) and the first connection portion (107d) (second annotated FIG. 6, below).
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Regarding claim 6, Suzuki discloses, The thin film transistor (203) of claim 1, wherein a thickness of the active layer (107) is increased along a direction (third annotated FIG. 6, below) from the channel (107A) toward the second connection portion (107s), centered on a boundary between the channel (107A) and the second connection portion (107s) (third annotated FIG. 6, below).
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Regarding claim 7, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the first active layer (107A) and the third active layer (107B) do not contact each other in at least a portion of the channel (107A) (fourth annotated FIG. 4, below).
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Regarding claim 8, Suzuki discloses, The thin film transistor (203) of claim 7, wherein the second active layer (107i) is disposed between the first active layer (107A) and the third active layer (107B) at a first boundary (first annotated FIG. 6, above) between the channel (107A) and the first connection portion (107d) (first annotated FIG. 6, above).
Regarding claim 9, Suzuki discloses, The thin film transistor (203) of claim 8, wherein the second active layer (107i) is disposed between the first active layer (107A) and the third active layer (107B) at a second boundary (first annotated FIG. 6, above) between the channel (107A) and the second connection portion (107s) (first annotated FIG. 6, above).
Regarding claim 12, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the third active layer (107B) has a mobility smaller than a mobility of the second active layer (107i) ([0089]).
Regarding claim 14, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the second active layer includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material ([0091]), an IGZTO(InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, or a ZnON (Zn-Oxynitride)-based oxide semiconductor material, and when the oxide semiconductor material included in the second active layer includes gallium (Ga) and indium (In), a concentration of indium (In) is higher than that of gallium (Ga) based on the number of moles [Ga concentration < In concentration].
Regarding claim 15, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the third active layer (107B) includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material ([0115]), an IGZTO (InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, or a ZnON (Zn-Oxynitride)-based oxide semiconductor material, and when the oxide semiconductor material included in the third active layer includes gallium (Ga) and indium (In), a concentration of indium (In) is higher than that of gallium (Ga) based on the number of moles [Ga concentration < In concentration].
Regarding claim 16, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the third active layer (107B) includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material ([0026]), a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the third active layer (107B) includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration] ([0044]).
Regarding claim 17, Suzuki discloses, The thin film transistor (203) of claim 1, wherein the gate electrodes (103 and/or 112) comprises tapered edges (fifth annotated FIG. 6, below) tapering in a first direction, and
wherein the second active layer (107i) comprises tapered edges (fifth annotated FIG. 6, below) tapering in a second direction opposite to the first direction. 3
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Regarding claim 18, Suzuki discloses, The thin film transistor (203) of claim 1, further comprising:
a buffer layer (buffer layer (105); FIG. 6; [0022]) on the substrate (substrate (101); FIG. 6; [0022]); and
a gate insulation layer (gate insulation layer (109); FIG. 6; [0022]) on the third active layer (107B) and the buffer layer (105).
Regarding claim 19, Suzuki discloses, A display apparatus ([0018]) comprising the thin film transistor (203) of claim 1.
Regarding claim 20, Suzuki discloses, A method for manufacturing a thin film transistor (thin film transistor (203); FIG. 6; [0080]), the method comprising:
forming an active layer (active layer (107); FIG. 6; [0022]) on a substrate (substrate (101); FIG. 6; [0022]);
forming a gate electrode (gate electrode (103 and/or 112); FIG. 6; [0022]) at least partially overlapping the active layer (107) (FIG. 6); and
forming a first connection portion (first connection portion (107d); FIG. 6; [0028]) and a second connection portion (second connection portion (107s); FIG. 6; [0028]) by selectively conductorizing areas of the active layer (107) not overlapping the gate electrode (103 and/or 112) to form a channel (channel (107A); FIG. 6; [0025]) by the selective conductorization,4
wherein the forming the active layer (107) includes:
forming a first active layer (first active layer (107A); FIG. 6; [0025]) on the substrate (101);
forming a second active layer (second active layer (107i); FIG. 6; [0080]) on the first active layer (107A) in the first connection portion (107d) and the second connection portion (107s) of the active layer (107); and
forming a third active layer (third active layer (107B); FIG. 6; [0025]) contacting the first active layer (107A) in the channel (107A) and contacting the second active layer (107i) in the first connection portion (107d) and the second connection portion (107s).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, as applied to claim 1, above, in view of US 2016/0247934 A1 (Hanaoka).
Regarding claim 10, Suzuki does not appear to explicitly disclose, wherein the second active layer has a mobility greater than a mobility of the first active layer.
However, in analogous art, Hanaoka discloses that it is well-known that a transistor (FIG. 1B) can be predicably fabricated to include an active layer (active layer (130); FIG. 1B; [0055]) having a first active layer (first active layer (131); FIG. 1B; [0053]), a second active layer (second active layer (132); FIG. 1B; [0053]) on the first active layer (131), and a third active layer (third active layer (133); FIG. 1B; [0053]) contacting first active layer (131) and second active layer (132). Hanaoka also discloses that it is well known that second active layer (132) can be predicably fabricated to have an increased carrier mobility relative to first active layer (131) and third active layer (133) through the addition of one or more chemical elements ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki and Hanaoka before him/her that it was well-known that the transistor (203) of Suzuki can be predicably fabricated so that the second active layer (107i) of Suzuki has a mobility greater than a mobility of the first active layer (107A) of Suzuki, as taught by Hanaoka, through the addition of one or more chemical elements to increase the carrier mobility of second active layer (107i) of Suzuki so that it is greater than the carrier mobility of first active layer (107A) of Suzuki, as also taught by Hanaoka, with no change in the respective functions of first active layer (107A) or second active layer (107i) because they would continue to operate as the respective first and second active layers (107A and 107i) of active layer (107) of Suzuki. See, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods To Yield Predicable Results.
Regarding claim 13, Suzuki does not appear to explicitly disclose, wherein the first active layer includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)- based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the first active layer includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration].5
However, in analogous art, Hanaoka discloses that it is well-known that a transistor (FIG. 1B) can be predicably fabricated to include an active layer (active layer (130); FIG. 1B; [0055]) having a first active layer (first active layer (131); FIG. 1B; [0053]), a second active layer (second active layer (132); FIG. 1B; [0053]) on the first active layer (131), and a third active layer (third active layer (133); FIG. 1B; [0053]) contacting first active layer (131) and second active layer (132). Hanaoka also discloses that it is well known that first active layer (131) can be predicably fabricated from an IGZO (InGaZnO)-based oxide semiconductor material whose atomic ratio of In to Ga and Zn can be 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4, or 1:9:6 ([0100]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki and Hanaoka before him/her that it was well-known that the transistor (203) of Suzuki can be predicably fabricated so that the first active layer (107A) of Suzuki includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material, as taught by Hanaoka, a GO (GaO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)- based oxide semiconductor material or a GZTO (GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material included in the first active layer includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is higher than that of indium (In) based on the number of moles [Ga concentration > In concentration], as also taught by Hanaoka, with no change in the respective function of first active layer (107A) because it would continue to operate as the first active layer (107A) of active layer (107) of Suzuki. See, MPEP 2143(A), above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, as applied to claim 1, above, in view of US 2020/0052116 A1 (Kim).
Regarding claim 11, Suzuki does not appear to explicitly disclose, The thin film transistor of claim 1, wherein the third active layer has a mobility greater than a mobility of the first active layer.
However, in analogous art, Kim discloses that it is well-known that a semiconductor device (FIG. 6) can be predicably fabricated to include a first active layer (first active layer (110a); FIG. 6; [0034]), a second active layer (second active layer (110b); FIG. 6; [0053]), and a third active layer (third active layer (110c); FIG. 6; [0062]). Kim also discloses that first active layer (110a) may be fabricated of silicon ([0036]) and that second active layer (110b) may also be fabricated of silicon ([0055]). Kim additionally discloses that it is well known that third active layer (110c) can be predicably fabricated to have an increased carrier mobility relative to first active layer (110a) and second active layer (110b) through the addition of one or more chemical elements to silicon, such as germanium ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Suzuki and Kim before him/her that it was well-known that the transistor (203) of Suzuki can be predicably fabricated so that the third active layer (107B) of Suzuki has a mobility greater than a mobility of the first active layer (107A) of Suzuki, as taught by Kim, through the addition of one or more chemical elements to increase the carrier mobility of third active layer (107B) of Suzuki so that it is greater than the carrier mobility of first active layer (107A) of Suzuki, with no change in the respective functions of first active layer (107A) or third active layer (107B) because they would continue to operate as the respective first and third active layers (107A and 107B) of active layer (107) of Suzuki. See, MPEP 2143(A), above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2020/0212076 A1 (Jang)—Discloses a thin-film transistor (200) that includes a gate electrode (140), an active layer (130) including a channel (131), a first connection portion (annotated FIG. 3, below), and a second connection portion (annotated FIG. 3, below) contacting opposite sides of channel (131).
[AltContent: connector][AltContent: textbox (Third Active Layer)][AltContent: connector][AltContent: textbox (Second Connection Portion)][AltContent: connector][AltContent: textbox (First Connection Portion)]
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Also discloses that active layer (130) includes a first active layer (130a), a second active layer (130b) on first active layer (130a) in the first connection portion (annotated FIG. 3, above) and the second connection portion (annotated FIG. 3, above), and a third active layer (annotated FIG. 3, above) contacting the first active layer (130a) and contacting the second active layer (130b) in the first connection portion (annotated FIG. 3, above) and the second connection portion (annotated FIG. 3, above).
US 2021/0119054 A1 (Yamazaki)—Discloses a transistor (FIG. 1B) that includes a gate electrode (260), a channel formation region ([0095]), and an active layer (230) having a first connection portion (242a) and a second connection portion (242b). Also discloses that active layer (230) includes a first active layer (230a), a second active layer (230b) on first active layer (230a) and in the first connection portion (242a) and second connection portion (242b), and a third active layer (230c) contacting first active layer (230a) in the channel formation region and second active layer (230b) in the first connection portion (242a) and second connection portion (242b).
US 2022/0005838 A1 (Yamanaka)—Discloses a thin-film transistor (400) that includes an active layer (42) that includes a plurality of spaced art separate structures (4Us) and (4Ud) (FIG. 8A).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 The Examiner respectfully notes that the first direction and second direction are illustrated in FIG. 1B for purpose of clarifying the objection to the drawings and may be one of many possible first and/or second directions. Please see the rejection of claim 17 under 35 U.S.C. 112(b), below.
2 Please see the rejection of claim 2 under 35 U.S.C. 112(b), above, for how this recited language is being interpreted for purpose of examination.
3 Please see the rejection of claim 17 under 35 U.S.C. 112(b), above, for how this recited language is being interpreted for purpose of examination.
4 Please see the rejection of claim 20 under 35 U.S.C. 112(b), above, for how this recited language is being interpreted for purpose of examination.
5 However, Suzuki does disclose that the first active layer 107A may “contain, for example, an In—Ga—Zn—O-based semiconductor (such as indium gallium zinc oxide). The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions of In, Ga, and Zn (composition ratio) is not particularly limited” ([0113]).