Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 10/20/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CN 115879408 A.
Regarding claims , 10, and 15, “408” discloses:
A method comprising (see page 1, The invention relates to physical design of integrated circuit, especially relates to a method for repairing antenna effect violation of integrated circuit….):
receiving a change to a netlist, wherein the netlist defines a design of an integrated circuit (IC) (see page 2, The number of added dummy diodes is output by loading the ASCII format file into the corresponding layout wiring data…. [wherein the ASCII format file into the corresponding layout wiring data is a netlist]);
identifying, using one or more computer processors, an excess antenna diode in the design of the IC, wherein the excess antenna diode is configured to remove charge buildup in a metal layer when the IC is being fabricated (see page 4, A method of eliminating antenna effect violations in the industry is by connecting a reverse bias diode to the conductor directly connected to the gate, to form a charge discharge loop …., see page 5, the area of the metal layer in the antenna effect report comprises effective area and invalid area….); and
removing or shrinking the excess antenna diode in a layout of the IC using the one or more computer processors (see page 3, by using software algorithm in the integrated circuit verification platform to determine eliminating antenna effect violation needed diode number, which can greatly shorten the iteration period, more quickly repairing the antenna effect violation of the integrated circuit ….., see page 9-10, The "lateral suppression" effect of method 400 allows for the selection of a minimum number of diodes capable of resolving the antenna effect violations…, [wherein minimum the number of the diodes which is shrinking the antenna diode]).
Regarding claims 2 and 16, “408” discloses:
wherein the excess antenna diode comprises a reverse biased diode (see page 4, A method of eliminating antenna effect violations in the industry is by connecting a reverse bias diode to the conductor directly connected to the gate….).
Regarding claims 3, 11, and 17, “408” discloses:
wherein a gate and a source or drain in the reverse biased diode are coupled to a same net in the netlist (see page 4, A method of eliminating antenna effect violations in the industry is by connecting a reverse bias diode to the conductor directly connected to the gate….).
Regarding claims 4, 12, and 18, “408” discloses:
wherein identifying the excess antenna diode comprises: prioritizing a plurality of antenna diodes in the layout; and iterating through the plurality of antenna diodes based on the prioritization to determine which of the plurality of antenna diodes can be removed or shrunk without resulting in an antenna violation (see page 7, by using the software algorithm in the integrated circuit verification platform to determine eliminating antenna effect violation needed diode number, can greatly shorten the iteration period,….., see page 10).
Regarding claims 5, 13, and 19, “408” discloses:
wherein the antenna violation is based on a metal-antenna ratio in the layout of the IC (see page 2, determines whether the gate node has antenna effect violation, comprising: calculating the accumulated antenna ratio of each layer of the effective ….).
Regarding claims 6, 14, and 20, “408” discloses:
wherein the excess antenna diode is configured to prevent harm to a gate oxide in the IC during the fabrication process (see page 4, A method of eliminating antenna effect violations in the industry is by connecting a reverse bias diode to the conductor directly connected to the gate, to form a charge discharge loop, so that the charge accumulated on the conductor will not cause damage to the gate oxide layer….).
Regarding claim 7, “408” discloses:
transmitting for displaying the identified excess antenna diode; and receiving instructions to remove or shrink the excess antenna diode via a user interface (UI) (see page 5, the data format can be directly loaded to the corresponding PR data of the EDA tool, so the user can intuitively see which gate node has antenna effect violation and eliminating the number information of the virtual diode…., see page 7).
Regarding claim 8, “408” discloses:
wherein removing or shrinking the excess antenna diode is performed automatically by a software tool, without user intervention (see page 5, it can use the electronic design automation (Electronic Design Automation, EDA) tool to perform the method 200….).
Regarding claim 9, “408” discloses:
receiving parameters for the software tool to use when removing or shrinking the excess antenna diode, the parameters comprises at least one of: designating an area of the layout of the IC where excess antenna diodes cannot be removed, or designating an area of the layout of the IC that has a higher priority when removing excess antenna diodes (see page 6, The antenna ratio refers to the ratio of the area of the effective conductor constituting the so-called "antenna" to the area of the gate to be connected….).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN NGO whose telephone number is (571)270-7011. The examiner can normally be reached M-F 7AM-4PM.
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/BRIAN NGO/ Primary Examiner, Art Unit 2851
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