CTNF 18/491,689 CTNF 80697 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 2-23 are pending in the application. Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." Information Disclosure Statement 06-52 AIA The information disclosure statement (IDS) submitted on 03/16/2026 was filed after the mailing date of the first office acti on. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 11, 20, 23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claims recite “ the first respective power control characteristic causes a time window to be used in the control of the power consumption of the first core when the first application is operated on the first core .” The specification fails to provide adequate written description support for the claimed “time window” and its use to controlling power consumption of a processor core. The specification merely states, in a conclusory manner, that “ The part S6 may represent a time window for the power information 211 .” However, the specification does not describe what the claimed “time window” is, what parameters define the temporal boundaries of the time window, how the time window is associated with a “power control characteristic”, how the time window is “used” in controlling power consumption etc., The disclosure amounts to a mere mention of a “time window for the power information” without sufficient descriptive detail to demonstrate possession of the claimed functionality. The originally-filled disclosure does not reasonably convey to one of ordinary skill in the art that applicant possessed the specific concept now claimed, namely, that a respective power control characteristic causes a time window to be used in controlling power consumption of a processor core. Accordingly, the specification fails to comply with the written description requirement of 35 U.S.C. 112(a). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 2, 6-10, 17-20, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ardanaz in view of Wang et al. US Pub. No. 2018/0232032 (“Wang”) . Regarding claim 2, Ardanaz teaches an apparatus, comprising: a plurality of cores [ Core 24 of CPU0 and Core 24 of CPU1 ]; and power control circuitry [ Power control 50 ] coupled to the plurality of cores, [0011] Turning now to the drawings in detail, FIG. 1 depicts a system 10 that includes multiple processors 20, a power control unit 50 , and a communication fabric 70 that facilitates communication between the processors 20 and the power control unit 50 . [0012] At the time a new workload such as an application is launched in the system 10, the application may be distributed as various threads that are sent to the processors 20. Each processor 20 may assign a thread to a processor core such as, for example, a processor core 24 . wherein the power control circuitry is to: receive a first power information [ Thread1.CLOS 40 ] associated with a first application [ Thread1 ] that is to be processed by a first core of the plurality of cores, wherein the first power information includes: a first priority information to indicate that the first application is associated with a first application class of a plurality of application classes; and a first indication of a first respective power control characteristic [ A thread with a high priority CLOS may be allocated more power ] of a plurality of power control characteristics; [0015] Each thread may subscribe to a class of service such as class of service (CLOS) 40 subscribed to by thread 1 . Various levels (e.g., four levels), may be provided for a class of service . The CLOS may determine power/performance decisions across threads . In one aspect, a CLOS may be a unit-less power-performance tuning policy value between 0 and 255. The smaller the CLOS 8-bit value, the higher the performance being requested . [0016] System-level machine specific registers (MSRs) may be provided in the power control unit (PCU) 50. For example, the various thread-level RMIDs may be aggregated into a system-level machine specific register 80 while the various thread-level CLOSs may be aggregated into a system level machine specific register 82. Having the system-level MSR and the core-level MSR 22 provides two different MSRs that may define a CLOS or RMID to which a particular thread may be associated . [0025] Illustrated processing block 230 associates a thread with a CLOS. Various levels may be provided for the CLOS indicating the priority of the thread and the comparative importance of resource allocation to the thread. A thread with a high priority CLOS may be allocated more power by the PCU 50 . Illustrated processing block 240 allocates power to be consumed by a processor core based on the class of service for the thread . While the PCU 50 may perform global allocation of power resources, the local PCL 60 may enforce the power allocation to a processor core . receive a second power information [ Thread3.CLOS ] associated with a second application [ Thread3 ] that is to be processed by a second core of the plurality of cores [ SEE CPU1 of fig. 1 ], wherein the second power information includes: a second priority information to indicate that the second application is associated with a second application class of the plurality of application classes; and a second indication of a second respective power control characteristic of the plurality of power control characteristics [ SEE discussed paragraph above ]; control a power consumption of the first core according to the first respective power control characteristic [ the PCL 60 may change the frequency of the core 24 in implementing the change of power – par. 0020 , 0040 ] of the plurality of power control characteristics when the first application is operated on the first core, wherein the control of the power consumption of the first core according to the first respective power control characteristic is based on the first priority information; and control a power consumption of the second core according to the second respective power control characteristic of the plurality of power control characteristics when the second application is operated on the second core, wherein the control of the power consumption of the second core according to the second respective power control characteristic is based on the second priority information. [0020] Power steering logic 96 may use CLOS information to allocate power resources to the various CPU cores 24. Each CPU core may include power control logic (PCL) 60 that implements that power policy determined by the PCU 50 . The PCL 60 may also include fixed-functionality logic hardware, configurable logic, logic instructions (e.g., software), etc., or any combination thereof In one aspect, the PCL 60 may change the frequency of the core 24 in implementing the change of power. As the overall power needs of the system change during processing of one or more applications, the PCU 50 may dynamically balance the power load among the processors/processor cores based on CLOS configuration to meet user demands. The PCL 60 may enforce the dynamic power balancing of the PCU 50 at the core or processor level . [0026] Example 1 may include a power control system comprising one or more processors, each processor having one or more cores, each core configured to process one or more application threads , each core including a machine specific register having logic, implemented in one or more of configurable logic or fixed functionality logic hardware, to facilitate thread association with a resource monitor and a class of service, a power control unit to a vary power allocation to a core according to the associated class of service , and communication fabric between the one or more processors and the power control unit . Ardanaz teaches control a power consumption of the first/second core according to the power control characteristic of the plurality of power control characteristics. Ardanaz does not expressly teach the plurality of application classes include a user experience application and a background application class. Wang teaches another power management method for selectively allocating power between plurality of application classes of an electronic apparatus. Specifically, Ardanaz teaches the plurality of application classes include a user experience application and a background application class. [0096] As mentioned above, before performing power budget allocation, the proposed power management mechanism may refer to the identified operating scenario to determine a heat source priority. Please refer to FIG. 8 again. In this embodiment, the priority classifier 833 may classify heat sources into different priority levels according requirements of an executed foreground application. For example, the priority classifier 833 may classify heat sources into a first priority level PC1, a second priority level PC2 and a third priority level PC3 , wherein a heat source having the first priority level PC1 is highly related to the foreground application , a heat source having the second priority level PC2 is related to at least one background application, and a heat source having the third priority level PC3 is not related to the foreground application and the at least one background application. Hence, in order to maintain a user experience of the executed foreground application (i.e. a primary user experience), the system power budget of the electronic apparatus 800 may be preferably allocated to a heat source having the first priority level PC1 , and the electronic apparatus 800 may preferably throttle a heat source having the third priority level PC3 (or a heat source having the second priority level PC2) to increase power allocated to other heat source(s) . [0062] Step 742: Construct a heat source priority table according to the current operating scenario. For example, the SPA circuit 130 may construct/generate a heat source priority table PR according to the operating scenario SR, wherein the heat source priority table PR may indicate a priority order of usage of one or multiple heat sources required to maintain the user experience with the application . [0066] In step 742, a high priority heat source in the heat source priority table PR may be a heat source highly related to the execution of the application . By way of example but not limitation, in a case where the electronic apparatus 100 operates in the operating scenario SR where a game application and a fast-charging application are executed , and the operating scenario SR (or the system information) indicates that the electronic apparatus 100 has enough battery charge, the heat source priority table PR may indicate that a heat source used to execute the game application (e.g. a processor module including a CPU and a GPU) has a higher priority than a heat source used to execute the fast-charging application (e.g. a charging module ). Hence, in step 744, the SPA circuit 130 may throttle the heat source associated with the fast-charging application to increase power allocated to the heat source associated with the game application, thereby maintaining the user experience with the game application . Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to implement the apparatus of Ardanaz with the plurality of application classes include a user experience application and a background application class of Wang. The motivation for doing so, as suggested by Wang, to prevent performance degradation by giving a higher priority, power allocation to user experience application class vs background application class. Thus, improve user’s viewing experience. Regarding claim 6, Ardanaz teaches the power control circuitry is to control the power consumption of the first core by controlling an operating frequency or a voltage of the first core to process the first application, the power control circuitry to select the operating frequency or voltage in accordance with the first application class [par. 0015, 0020, 0040]. Regarding claim 7, Ardanaz teaches wherein the first core and the second core are integral to a first system-on-chip integrated on a circuit board, the apparatus further comprising at least one additional SoC integrated on the circuit board [See par. 0026 - each processor having one or more cores, each core configured to process one or more application threads ]. Regarding claim 8, Ardanaz teaches a voltage regulator to control the voltage of the first core [par. 0013]. Regarding claim 9, Ardanaz teaches the first and second power information are to be stored in one or more control registers to be used by the power control circuitry to control the power consumption of the first core and the second core [par. 0012, 0016]. Regarding claims 10, it is directed to the method of steps and instructions to implement the system as set forth in claims 2. Therefore, it is rejected on the same basis as set forth hereinabove. Regarding claim 11, Ardanaz teaches wherein the first respective power control characteristic causes a time window [ time of energy report ] to be used in the control of the power consumption of the first core when the first application is operated on the first core, [0014] Energy sampling rates may vary over time as RMID may allow software to create thread groups for energy monitoring. When power samples are taken may be different in time across the threads. For example, when energy may be sampled for RMID-0 may be different than when it may be sampled for RMID-1. Therefore, in an example of energy reporting, 64-bit registers may be used in which the lower 48 bits may contain the sampled energy value encoded using an energy unit defined in a control register . The upper 16 bits may provide a relative time stamp of the moment in time such energy sample was taken. For example, the 16 bits may be the least significant bits of an “always running timer” (ART) driven by a 25 MHz clock. These least significant bits provide about 2 ms of energy reporting range . Software may read the full ART in combination with the energy reported least significant bits to reconstruct an absolute time reference . [0020] Power steering logic 96 may use CLOS information to allocate power resources to the various CPU cores 24. Each CPU core may include power control logic (PCL) 60 that implements that power policy determined by the PCU 50. The PCL 60 may also include fixed-functionality logic hardware, configurable logic, logic instructions (e.g., software), etc., or any combination thereof In one aspect, the PCL 60 may change the frequency of the core 24 in implementing the change of power. As the overall power needs of the system change during processing of one or more applications, the PCU 50 may dynamically balance the power load among the processors/processor cores based on CLOS configuration to meet user demands . The PCL 60 may enforce the dynamic power balancing of the PCU 50 at the core or processor level . further comprising executing program code on one or more of the plurality of cores to implement an operating system (OS) [par. 0005, 0017]. Regarding claim 12, Ardanaz teaches wherein the OS is to provide services to the first and second applications, including a scheduler to assign the first core to process the first application and to assign the second core to process the second application [par. 0012, 0017] Regarding claim 13, Ardanaz teaches the first power information of the first application is assigned by the scheduler [SEE par. 0012, 0015, 0016 - Logic instructions implemented in hardware, configurable logic and/or software may use either the system-level or core-level MSR to associate a thread with a particular RMID or CLOS ]. Regarding claim 17, Ardanaz teaches storing the first and second power information in one or more control registers to be used to control the power consumption of the first core and the second core [par. 0012, 0016]. Regarding claims 18-20, they are directed to the instructions to implement the system as set forth in claims 2, 6, and 11. Therefore, they are rejected on the same basis as set forth hereinabove. Regarding claim 23, the first respective power control characteristic causes a time window to be used in the control of the power consumption of the first core when the first application is operated on the first core [See discussion in claim 11] . 07-22-aia AIA Claim (s) 3-5, 14-16, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ardanaz/Wang as applied to claim 2 above, and further in view of Kumar . Regarding claim 3, Ardanaz teaches a non-transitory computer-readable storage medium to store program code to be executed on one or more of the plurality of cores to implement an operating system (OS) [See par. 0005, 0017]. Ardanaz/Wang does not teach each of the plurality of power control characteristic representing a different parameter to be used to operate the first application. Kumar teaches a system includes a system on chip having a plurality of cores, a memory storing historical use data for application. Specifically, Kumar teaches the historical use data for application indicate a power control characteristic of a plurality of power control characteristics, each of the plurality of power control characteristic representing a different parameter to be used to operate the application [ SEE fig. 5 ]. [0037] During normal operation of the computing device 100 (FIG. 1), the user may interact with the computing device 100 to open or close one or more applications, to consume content such as video or audio streams, or other operations. In one example in which a user opens an application, such application may be associated with tens or hundreds of processing threads that would then be placed in various queues of the processing components 310, 320, 340, 350. Each of the cores Core 0-Core 3 includes its own processing queue, and any one of the cores Core 0-Core 3 may receive processing threads as well. The thread scheduler is responsible for placing the processing threads in the various queues according to a variety of different criteria. As explained in more detail below, the various criteria may include the information stored in tables 400 and 500 of FIGS. 4 and 5 . [0043] The example of FIG. 5 is provided with respect to two applications, but it is understood that the scope of embodiments may include historical use data for any appropriate number of applications. The historical use data of Table 500 may include data observed during operation of an application on a computing device , and the historical use data may be updated as different values are observed by an OS kernel or other appropriate algorithm over time . [0044] Each of the columns in Table 500 includes a particular operating characteristic attributable to a given application . For instance, the first four columns of Table 500 include minimum and maximum operating voltages and minimum and maximum operating frequencies . In some applications, such as those that include audio or video or more intense data processing may have higher operating voltage requirements and higher operating frequency requirements. By contrast, some applications that may handle primarily text and still images (e.g., messaging applications) may have lower operating voltage requirements and lower operating frequency requirements. Thus, in this example, application X may represent a messaging application, as it has a minimum frequency requirement of 50 MHz. On the other hand, application Y may represent a gaming application, as it has a minimum frequency requirement of 200 MHz . Before the effective filing data of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of the cited reference because they all directed to the method and system for controlling power consumption of the system according to the characteristic of an application. Kumar’s teachings of each of the plurality of power control characteristic representing a different parameter to be used to operate the application would ensure optimum application’s performance while reducing power consumption of the system. Regarding claim 4, Ardanaz teaches the OS is to provide services to the first and second applications, including a scheduler to assign the first core to process the first application and to assign the second core to process the second application [par. 0012, 0017]. Regarding claim 5, Ardanaz teaches the first power information of the first application is assigned by the scheduler [SEE par. 0012, 0015, 0016 - Logic instructions implemented in hardware, configurable logic and/or software may use either the system-level or core-level MSR to associate a thread with a particular RMID or CLOS ]. Regarding claim 14, Ardanaz teaches controlling the power consumption of the first core is performed by controlling an operating frequency or a voltage of the first core to process the first application, including select the operating frequency of voltage in accordance with the first application [par. 0015, 0020, 0040]. Ardanaz/Wang does not teach each of the plurality of power control characteristic representing a different parameter to be used to operate the first application. Kumar teaches a system includes a system on chip having a plurality of cores, a memory storing historical use data for application. Specifically, Kumar teaches the historical use data for application indicate a power control characteristic of a plurality of power control characteristics, each of the plurality of power control characteristic representing a different parameter to be used to operate the application [ SEE discussed above in claim 3 ]. Regarding claim 15, Ardanaz teaches wherein the first core and the second core are integral to a first system-on-chip integrated on a circuit board, the method further comprising at least one additional SoC integrated on the circuit board [See par. 0026 - each processor having one or more cores, each core configured to process one or more application threads ]. Regarding claim 16, Ardanaz teaches a voltage regulator to control the voltage of the first core [par. 0013]. Regarding claim 21, Ardanaz teaches wherein the first and second power information are to be stored in one or more control registers to be used by the power control circuitry to control the power consumption of the first core and the second core [par. 0012, 0016]. Ardanaz/Wang does not teach each of the plurality of power control characteristic representing a different parameter to be used to operate the first application. Kumar teaches a system includes a system on chip having a plurality of cores, a memory storing historical use data for application. Specifically, Kumar teaches the historical use data for application indicate a power control characteristic of a plurality of power control characteristics, each of the plurality of power control characteristic representing a different parameter to be used to operate the application [ SEE discussed above in claim 3 ]. Regarding claim 22, Ardanaz/Wang in view of Kumar teaches each of the plurality of power control characteristics is to represent a different parameter to be used to operate the first application [See discussion in claim 3 above] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT HUY TRAN whose telephone number is (571)272-7210. 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VINCENT H TRAN Primary Examiner Art Unit 2115 /VINCENT H TRAN/Primary Examiner, Art Unit 2115 Application/Control Number: 18/491,689 Page 2 Art Unit: 2115 Application/Control Number: 18/491,689 Page 3 Art Unit: 2115 Application/Control Number: 18/491,689 Page 4 Art Unit: 2115 Application/Control Number: 18/491,689 Page 5 Art Unit: 2115 Application/Control Number: 18/491,689 Page 6 Art Unit: 2115 Application/Control Number: 18/491,689 Page 7 Art Unit: 2115 Application/Control Number: 18/491,689 Page 8 Art Unit: 2115 Application/Control Number: 18/491,689 Page 9 Art Unit: 2115 Application/Control Number: 18/491,689 Page 10 Art Unit: 2115 Application/Control Number: 18/491,689 Page 11 Art Unit: 2115 Application/Control Number: 18/491,689 Page 12 Art Unit: 2115 Application/Control Number: 18/491,689 Page 13 Art Unit: 2115 Application/Control Number: 18/491,689 Page 14 Art Unit: 2115
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