DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant’s arguments filed 05/24/2026 with respect to claims 1-17 and 23-27 have been fully considered but are not persuasive.
With respect to claimed limitation “wherein the remote memory-set instruction is smaller in size than a total amount of data written to the volatile memory in response to the remote memory-set instruction”, besides reciting that the remote memory-set instruction is smaller than a total amount of data written to the volatile memory, the limitation is also reciting the remote memory-set instruction is in response to the remote memory-set instruction, which is confusing. The examiner doesn’t know how to interpret this limitation.
With respect to claimed ‘network adapter’, ‘remote network adapter’ or ‘communication network’, the claim language doesn’t provide more specifics of what those items comprise off.
OBJECTIONS TO THE CLAIMS
Claims 1-17 and 23-27 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
As per claims 1, 5, 8, 12 and 15, limitation “wherein the remote memory-set instruction is smaller in size than a total amount of data written to the volatile memory in response to the remote memory-set instruction” is confusing. Besides reciting that the remote memory-set instruction is smaller than a total amount of data written to the volatile memory, the limitation is also reciting the remote memory-set instruction is in response to the remote memory-set instruction, which is confusing. The examiner doesn’t know how to interpret this limitation. Correction is needed.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1, 5, 8, 12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by over Tomishima et al., (US pub. # 2018/0181344), hereinafter, “Tomishima”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 5, 8, 12 and 15, Tomishima discloses a network adapter (I/O interface logic 122 of fig. 1, as discloses in paragraph 0032), comprising: a port, to connect to a communication network (see fig. 1); and circuitry, to send to a remote network adapter (I/O interface logic 142), via the communication network (see paragraphs 0025 and 0112), a remote memory-set instruction (WRITE-F command, as disclose in paragraphs 0042 and 0046) [see paragraph 0042, which discloses “as mentioned above, in one embodiment, the memory controller 120 can transmit a command to the memory device 140 to cause a data pattern to be written to memory without transmitting the data pattern for each write”, and paragraph 0046, which discloses “the memory controller 120 then transmits a second command (such as the WRITE-F command), which causes the memory device 140 to write the latched data to memory without receiving the data pattern over the signal lines for a data bus again”] that instructs the remote network adapter to [see paragraph 0042, which discloses “in one embodiment, the command can be a modified write command that causes the memory device 140 to write a data pattern to memory in response to the command”, and paragraph 0046, which discloses “in one embodiment, if the mode register indicates that the data pattern source is external data, then the controller 150 writes the latched data pattern stored in data latches from a previous write command. In one such example, the memory controller 120 transmits a first write command to the memory device with the desired write pattern, causing the data pattern to be latched in data latches of the memory device. The memory controller 120 then transmits a second command (such as the WRITE-F command), which causes the memory device 140 to write the latched data to memory without receiving the data pattern over the signal lines for a data bus again”] fill one or more address ranges in a volatile memory with multiple copies of one or more fill-data value (see paragraph 0055, which disclose “bank control logic 322 selects which bank group will be selected for the memory access operation (command) received. Column address counter 324 generates a signal to select the column for the operation. In one embodiment, control logic 302 includes a counter (not explicitly shown) to internally generate bank group addresses and sequence through selected bank groups for a single command. Thus, one or more selected bank groups can be accessed for a single command”), wherein the remote memory-set instruction is smaller in size than a total amount of data written to the volatile memory in response to the remote memory-set instruction (see paragraph 0042. Note, this limitation is confusing. Besides reciting that the remote memory-set instruction is smaller than a total amount of data written to the volatile memory, the limitation is also reciting the remote memory-set instruction is in response to the remote memory-set instruction, which is confusing. The examiner doesn’t know how to interpret this limitation).
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 2-4, 6, 7, 9-11, 13, 14, 16, 17 and 23-27 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tomishima et al., (US pub. # 2018/0181344), hereinafter, “Tomishima”, in view of Wang et al. (US pub. # 2020/0371914), hereinafter, “Wang”.
5. As per claims 2, 6, 9, 13 and 16, Tomishima discloses “the network adapter according to claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the remote memory-set instruction comprises an address-range indicator that indicates the one or more address ranges.
Wang discloses wherein the remote memory-set instruction comprises an address-range indicator that indicates the one or more address ranges (see paragraphs 0025, 0040 and 0094).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Wang’s teaching of an interface apparatus that includes a packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory, into Tomishima’s teaching of a system to program data pattern for repeated writes to a memory without transmitting the data pattern for each write, for the benefit of enabling a remote system to indicate a desired behavior for memory transactions through networking and a network interface card or network interface controller, and cause receiver hardware or software to take appropriate actions to achieve data durability.
6. As per claims 3, 7, 10 and 17, Tomishima discloses “the network adapter according to claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the remote memory-set instruction comprises a fill-data indicator that indicates the one or more fill-data values.
Wang discloses wherein the remote memory-set instruction comprises a fill-data indicator that indicates the one or more fill-data values (see paragraphs 0025, 0040 and 0094).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Wang’s teaching of an interface apparatus that includes a packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory, into Tomishima’s teaching of a system to program data pattern for repeated writes to a memory without transmitting the data pattern for each write, for the benefit of enabling a remote system to indicate a desired behavior for memory transactions through networking and a network interface card or network interface controller, and cause receiver hardware or software to take appropriate actions to achieve data durability.
7. As per claims 4, 11 and 14, Tomishima discloses “the network adapter according to claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the circuitry is to receive, from a host, a command specifying the one or more address ranges and the one or more fill-data values, and to send the remote memory-set instruction in response to the command.
Wang discloses wherein the circuitry is to receive, from a host, a command specifying the one or more address ranges and the one or more fill-data values, and to send the remote memory-set instruction in response to the command (see paragraphs 0025, 0026 and 0033).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Wang’s teaching of an interface apparatus that includes a packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory, into Tomishima’s teaching of a system to program data pattern for repeated writes to a memory without transmitting the data pattern for each write, for the benefit of enabling a remote system to indicate a desired behavior for memory transactions through networking and a network interface card or network interface controller, and cause receiver hardware or software to take appropriate actions to achieve data durability.
8. As per claims 23-27, Tomishima discloses “the network adapter according to claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the remote memory-set instruction is implemented as an RDMA operation.
Wang discloses wherein the remote memory-set instruction is implemented as an RDMA operation (see paragraphs 0019 and 0026).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Wang’s teaching of an interface apparatus that includes a packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory, into Tomishima’s teaching of a system to program data pattern for repeated writes to a memory without transmitting the data pattern for each write, for the benefit of enabling a remote system to indicate a desired behavior for memory transactions through networking and a network interface card or network interface controller, and cause receiver hardware or software to take appropriate actions to achieve data durability.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-17 and 23-27 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights