DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/18/2025 has been entered.
Applicant’s arguments filed on 11/18/2025 with respect to claims 1-27 have been fully considered but are moot in view of newly cited reference.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-14, 18-21 and 23-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For example, limitation “a remote memory-set instruction transmitted without a data payload” is new matter; it was not disclosed in applicant original filed specification.
Applicant is required to remove such language.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim 1-27 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tomishima et al., (US pub. # 2018/0181344), hereinafter, “Tomishima”, in view of Wang et al. (US pub. # 2020/0371914), hereinafter, “Wang”.
3. As per claim 1, 5, 8, 12 and 15, Tomishima discloses a network adapter (I/O interface logic 122 of fig. 1, as discloses in paragraph 0032), comprising: a port, to connect to a communication network (see fig. 1); and circuitry, to send to a remote network adapter (I/O interface logic 142), via the communication network (see paragraphs 0025 and 0112), a remote memory-set instruction (WRITE-F command, as disclose in paragraphs 0042 and 0046) transmitted without a data payload [see paragraph 0042, which discloses “as mentioned above, in one embodiment, the memory controller 120 can transmit a command to the memory device 140 to cause a data pattern to be written to memory without transmitting the data pattern for each write”, and paragraph 0046, which discloses “the memory controller 120 then transmits a second command (such as the WRITE-F command), which causes the memory device 140 to write the latched data to memory without receiving the data pattern over the signal lines for a data bus again”] that instructs the remote network adapter to locally generate one or more fill-data values [see paragraph 0042, which discloses “in one embodiment, the command can be a modified write command that causes the memory device 140 to write a data pattern to memory in response to the command”, and paragraph 0046, which discloses “in one embodiment, if the mode register indicates that the data pattern source is external data, then the controller 150 writes the latched data pattern stored in data latches from a previous write command. In one such example, the memory controller 120 transmits a first write command to the memory device with the desired write pattern, causing the data pattern to be latched in data latches of the memory device. The memory controller 120 then transmits a second command (such as the WRITE-F command), which causes the memory device 140 to write the latched data to memory without receiving the data pattern over the signal lines for a data bus again”], and fill one or more address ranges in a volatile memory with multiple copies of the one or more fill-data values (see paragraph 0055, which disclose “bank control logic 322 selects which bank group will be selected for the memory access operation (command) received. Column address counter 324 generates a signal to select the column for the operation. In one embodiment, control logic 302 includes a counter (not explicitly shown) to internally generate bank group addresses and sequence through selected bank groups for a single command. Thus, one or more selected bank groups can be accessed for a single command”).
Tomishima fails to specifically disclose wherein a fill-data value comprises a pattern of data values that is specified once in the instruction and is to be written to the volatile memory multiple times by the remote network adapter.
Wang disclose wherein a fill-data value comprises a pattern of data values that is specified once in the instruction and is to be written to the volatile memory multiple times by the remote network adapter (see paragraph 0033, which discloses “in response to receipt of the data durability flag, indicator that data is to be persisted, or indicator to store the data into a cache and memory buffer, NIC 260 can cause IO controller 256 at (3) to write data associated with the received RDMA write to LLC 254, or other cache level or memory. A cache can be a volatile memory and closer to a processor core than an on-device memory. The cache can store copies of the data from frequently used main memory locations”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Wang’s teaching of an
interface apparatus that includes a packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory, into Tomishima’s teaching of a system to program data pattern for repeated writes to a memory without transmitting the data pattern for each write, for the benefit of enabling a remote system to indicate a desired behavior for memory transactions through networking and a network interface card or network interface controller, and cause receiver hardware or software to take appropriate actions to achieve data durability.
4. As per claims 2, 6, 9, 13 and 16, the combination of Tomishima and Wang discloses “The network adapter according to claim 1” [See rejection to claim 1 above], wherein the remote memory-set instruction comprises an address-range indicator that indicates the one or more address ranges (see paragraphs 0025, 0040 and 0094 of Wang).
5. As per claims 3, 7, 10 and 17, the combination of Tomishima and Wang discloses “The network adapter according to claim 1” [See rejection to claim 1 above], wherein the remote memory-set instruction comprises a fill-data indicator that indicates the one or more fill-data values (see paragraphs 0025, 0040 and 0094 of Wang).
6. As per claims 4, 11 and 14, the combination of Tomishima and Wang discloses “The network adapter according to claim 1” [See rejection to claim 1 above], wherein the circuitry is to receive, from a host, a command specifying the one or more address ranges and the one or more fill-data values, and to send the remote memory-set instruction in response to the command (see paragraphs 0025, 0026 and 0033 of Wang).
7. As per claims 18-22, the combination of Tomishima and Wang discloses “The network adapter according to claim 1” [See rejection to claim 1 above], wherein the pattern of data values comprises a single data value (see paragraphs 0016 and 0020 of Wang. Please note, the claim language is not limited to ‘only’ a single value).
8. As per claims 23-27, the combination of Tomishima and Wang discloses “The network adapter according to claim 1” [See rejection to claim 1 above], wherein the remote memory-set instruction is implemented as an RDMA operation (see paragraphs 0019 and 0026 of Wang).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-27 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181