DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 10, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2021/0125989) hereinafter “Shin” in view of Li et al. (US 2024/0023310) hereinafter “Li”.
Regarding claim 1, Fig. 3A of Shin teaches a semiconductor memory device comprising: a source layer (Item SD1), a semiconductor layer (Item CH), and a drain layer (Item SD2) that are arranged in a first horizontal direction (Up and down across the page) on a substrate (Paragraph 006); a cell capacitor (Item DS) on the substrate, extending in the first horizontal direction (Up and down across the page), and comprising an upper electrode layer (Item PE), a capacitor dielectric film (Item DL), and lower electrode layer (Item SE) connected to the drain layer (Item SD2); a bit line (Item BL) on the substrate, extending in a vertical direction (Left to right across the page) and connected to the source layer (Item SD1); and a gate structure (Combination of Items Gox and WL2) covering the semiconductor layer (Item CH) and comprising a gate dielectric film (Item Gox) on the semiconductor layer (Item CH) and a gate electrode film (Item WL2) on the gate dielectric film (Item WL2); and where the source layer (Item SD1) has a second thickness at the other end portion of the semiconductor layer (Item CH) and has a third thickness (Where Item SD1 flares out at the BL based on the shape of Item 13), which is greater than the second thickness, as a maximum thickness.
Shin does not teach where the semiconductor layer comprises a semiconductor protrusion structure nor wherein a value of a first thickness of an end portion of the semiconductor protrusion structure facing the drain layer is greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing the source layer.
Fig. 1 of Li teaches where a semiconductor layer (Item 205) comprises a semiconductor protrusion structure wherein a value of a first thickness of an end portion of the semiconductor protrusion structure facing away from a bit line is greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing toward the bit line (Paragraph 0021 where the drain is connected to the bit line).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the value of a first thickness of an end portion of the semiconductor protrusion structure facing away from a bit line be greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing toward the bit line because this allows for a leakage current from the channel region be reduced in an off state (Li Paragraph 0027).
When the a value of a first thickness of an end portion of the semiconductor protrusion structure facing away from a bit line is greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing toward the bit line taught by Li is applied to Shin, where the source region is between the bit line and the semiconductor layer, a value of a first thickness of an end portion of the semiconductor protrusion structure facing the drain layer will be greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing the source layer.
Regarding claim 7, Fig. 3A of Shin further teaches where a maximum thickness of the semiconductor layer (Item CH) is equal to the maximum thickness of the drain layer (Item SD2).
Regarding claim 10, Fig. 3A of Shin further teaches where a word line contact (Item WL1) connected to the gate structure (Combination of Items Gox and WL2) and extending in the vertical direction (Fig. 2 where WL2 has a thickness and thus extends in the same vertical direction as the bit line), wherein a bottom surface of the word line (Item WL1) contacts a portion of the gate electrode film covering a top surface of the semiconductor protrusion pattern.
Regarding claim 19, Fig. 3A of Shin teaches a semiconductor memory device comprising: a plurality of horizontal semiconductor structures on a substrate and arranged in a first horizontal direction, each comprising a source layer (Item SD1), a semiconductor layer (Item CH), and a drain layer (Item SD2), the plurality of horizontal semiconductor structures arranged apart in columns in a second horizontal direction orthogonal to the first horizontal direction and in rows in a vertical direction; a plurality of cell capacitors (Item DS) extending in the first horizontal direction from the plurality of horizontal semiconductor structures, the plurality of cell capacitors each comprising a lower electrode layer (Item SE) connected to the source layer (Item SD1) of a respective one of each of the plurality of horizontal semiconductor structures, a capacitor dielectric film (Item DL) covering each of the plurality of lower electrode layers, and an upper electrode layer (Item PE) covering the capacitor dielectric film; a plurality of bit lines (Item BL) extending in the vertical direction on the substrate, connected to the source layers of horizontal semiconductor structures, and arranged apart from one another in the vertical direction from among the plurality of horizontal semiconductor structures, and arranged apart from one another in the second horizontal direction; a plurality of gate structures (Combination of Items Gox and WL2) surrounding the semiconductor layers (Item CH), apart from one another in the second horizontal direction from among the plurality of semiconductor layers and extending the second horizontal direction, the plurality of gate structures each comprising a gate dielectric film (Item Gox) on the semiconductor layer (Item CH) and a gate electrode film (Item WL2) on the gate dielectric film (Item Gox); a plurality of word line contacts (Items WL1) extending in the vertical direction and arranged apart from one another in the second horizontal direction, where the plurality of word line contacts are arranged apart from the plurality of bit lines in the first horizontal direction and are connected to the gate electrode film of each of the plurality of gate structures, where each of the plurality of semiconductor layers extends from an end of the semiconductor layer facing each of the plurality of drain layers to another end of the semiconductor layer facing each of the source layers; each of the source layers (Items SD1) extends in the first horizontal direction from the other end of each of the semiconductor layers (Items CH), with an increase in a thickness from the second thickness to a third thickness (Where Item SD1 flares out at the bit line) that is greater than the second thickness and a thickness of each of the drain layers (Items SD2) extends in a constant thickness between an end of each of the semiconductor layers (Items CH) and each of the plurality of cell capacitors (Items DS).
Shin does not teach where the semiconductor layer comprises a semiconductor protrusion structure nor where each of the plurality of semiconductor protrusions extends with a decrease from a first thickness to a second thickness that is less than the first thickness, from an end of the semiconductor protrusion structure facing each of the plurality of drain layers to another end of the semiconductor protrusion structure facing each of the source layers.
Fig. 1 of Li teaches where a semiconductor layer (Item 205) comprises a semiconductor protrusion structure wherein a value of a first thickness of an end portion of the semiconductor protrusion structure facing away from a bit line is greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing toward the bit line (Paragraph 0021 where the drain is connected to the bit line).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor protrusion structures, where each of the plurality of semiconductor protrusions extends with a decrease from a first thickness to a second thickness that is less than the first thickness, from an end of the semiconductor protrusion structure facing each of the plurality of drain layers to another end of the semiconductor protrusion structure facing each of the source layers because this allows for a leakage current from the channel region be reduced in an off state (Li Paragraph 0027).
Regarding claim 20, the combination of Shin and Li teaches all of the elements of the claimed invention as stated above.
Shin does not teach, in the vertical direction, the first thickness of an end of the semiconductor protrusion structure facing the drain layer is 20 nm to 50 nm, and the second thickness of another end of the semiconductor protrusion structure facing the source layer is from 5 to 20 nm.
Li further teaches the diameter of the semiconductor channel (Item 205) facing the bit line is between 4-20 nm and the diameter of the semiconductor channel (Item 205) facing away from the bit line is between 15-50 nm (Paragraph 0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the diameter of the semiconductor channel (Item 205) facing the bit line be between 4-20 nm and the diameter of the semiconductor channel (Item 205) facing away from the bit line is between 15-50 nm such that, in the vertical direction, the first thickness of an end of the semiconductor protrusion structure facing the drain layer is 20 nm to 50 nm, and the second thickness of another end of the semiconductor protrusion structure facing the source layer is from 5 to 20 nm because this allows for a leakage current from the channel region be reduced in an off state (Li Paragraph 0027) and “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)” (MPEP 2144.05).
Claims 2-4, 6, 9, 11-14, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2021/0125989) hereinafter “Shin” in view of Li et al. (US 2024/0023310) hereinafter “Li” and in further view of Seong et al. (US 2019/0245076) hereinafter “Seong”.
Regarding claim 2, the combination of Shin and Li teaches all of the elements of the claimed invention a stated above except where the source layer comprises a polygon shape having facets.
Fig. 3B of Seong teaches a source layer (Item 162U) comprises a polygon shape having facets (Paragraph 0054).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a source layer comprises a polygon shape having facets because it allows the source layer to have a large lateral width (Seong Paragraph 0054) such that good contact with the bitline may be made.
Regarding claim 3, the combination of Shin and Li teaches all of the elements of the claimed invention a stated above except where the drain layer comprises a polygon shape having facets.
Fig. 3B of Seong teaches a drain layer (Item 162U) comprises a polygon shape having facets (Paragraph 0054).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the drain layer comprises a polygon shape having facets because it allows the drain layer to have a large lateral width (Seong Paragraph 0054) such that good contact with the capacitor may be made.
Regarding claim 4, the combination of Shin, Li and Seong teaches all of the elements of the claimed invention as stated above except where the drain layer has a cuboid shape.
Fig. 3B of Seong teaches a drain layer (Item 164U) has a cuboid shape (Paragraph 0057).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the drain layer have a cuboid shape because it allows the drain layer to have a large lateral width (Seong Paragraph 0057) such that good contact with the capacitor may be made.
Regarding claim 6, the combination of Shin and Li teaches all of the elements of the claimed invention as stated above.
Shin further teaches where the drain layer (Item SD2) and the source layer (Item SD1) respectively contact the end portion and the other end portion of the semiconductor layer (Item CH) (Semiconductor protrusion structure when combined with Li as recited in claim 1 above).
Shin does not teach where a value of a maximum thickness of the drain layer is greater than a value of the first thickness.
Fig. 3B of Seong teaches a drain layer (Item 164U) having a cuboid shape (Paragraph 0057) where the maximum width of the drain layer (Item 164U) is wider than a channel (Item 124).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a value of a maximum thickness of the drain layer is greater than a value of the first thickness because it allows the drain layer to have a large lateral width (Seong Paragraph 0057) such that good contact with the capacitor may be made.
Regarding claim 9, the combination of Shin and Li teaches all of the elements of the claimed invention as stated above.
Shin does not teach where the semiconductor protrusion structure extends from the drain layer toward the source layer with a decrease in a vertical cross section of the semiconductor protrusion structure.
Fig. 1 of Li teaches where a semiconductor layer (Item 205) comprises a semiconductor protrusion structure wherein the semiconductor protrusion structure extends a drain layer toward a source layer with a decrease in a vertical cross section of the semiconductor protrusion structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor protrusion structure extends from the drain layer toward the source layer with a decrease in a vertical cross section of the semiconductor protrusion structure because this allows for a leakage current from the channel region be reduced in an off state (Li Paragraph 0027).
Regarding claim 11, Fig. 3A of Shin teaches a semiconductor memory device comprising: a plurality of horizontal semiconductor structures each comprising a source layer (Item SD1), a semiconductor layer (Item CH), and a drain layer (Item SD2) arranged in a first horizontal direction (Up and down across the page) on a substrate (Paragraph 006), where the plurality of horizontal semiconductor structures are apart from one another in columns in a second horizontal direction, which is orthogonal to the first horizontal direction, and in rows in a vertical direction; a plurality of cell capacitor (Item DS) extending in the first horizontal direction from the plurality of horizontal semiconductor structures and each comprising a lower electrode layer (Item SE) connected to the drain layer (Item SD2) of each of the plurality of horizontal semiconductor structures, a capacitor dielectric film (Item DL) covering the lower electrode layer, and an upper electrode layer (Item PE) covering the capacitor dielectric film; a plurality of bit lines (Item BL) extending in the vertical direction on the substrate, apart from one another in the second horizontal direction and connected to the drain layers (via the source and channel) of the plurality of horizontal semiconductor structures; and a plurality of gate structures (Combination of Items Gox and WL2) covering the plurality of semiconductor layers (Item CH) and extending in the second horizontal direction, the plurality of gate structures each comprising a gate dielectric film (Item Gox) on the semiconductor layer (Item CH) and a gate electrode film (Item WL2) on the gate dielectric film (Item WL2); where each of the plurality of semiconductor layers extends from an end of the semiconductor layer facing each of the plurality of drain layers to another end of the semiconductor layer facing each of the source layers.
Shin does not teach where the semiconductor layer comprises a semiconductor protrusion structure nor wherein where the semiconductor protrusion structure has a decrease from a first thickness to a second thickness that is less than the first thickness.
Fig. 1 of Li teaches where a semiconductor layer (Item 205) comprises a semiconductor protrusion structure wherein a value of a first thickness of an end portion of the semiconductor protrusion structure facing away from a bit line is greater than a value of a second thickness of another end portion of the semiconductor protrusion structure facing toward the bit line (Paragraph 0021 where the drain is connected to the bit line).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor protrusion structure have a decrease from a first thickness to a second thickness that is less than the first thickness because this allows for a leakage current from the channel region be reduced in an off state (Li Paragraph 0027).
Shin does not teach where each of the source layers has a polygon shape having facets extending from the other end of each of the semiconductor protrusion structures, with an increase from the second thickness to a third thickness that is greater than the second thickness in the first horizontal direction.
Fig. 3B of Seong teaches a source layer (Item 162U) comprises a polygon shape having facets (Paragraph 0054) extending from a channel with an increase from a first thickness to a second thickness in the middle of the source layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the source layers has a polygon shape having facets extending from the other end of each of the semiconductor protrusion structures, with an increase from the second thickness to a third thickness that is greater than the second thickness in the first horizontal direction because it allows the source layer to have a large lateral width (Seong Paragraph 0054) such that good contact with the bitline may be made.
Regarding claim 12, the combination of Shin, Li and Seong teaches all of the elements of the claimed invention as stated above.
Shin does not teach where each of the drain layers has a polygon shape having facets extending from an end of each of the plurality of semiconductor protrusion structures to each of the plurality of cell capacitors, with an increase from the first thickness to a fourth thickness that is greater than the first thickness.
Fig. 3B of Seong teaches drain layers (Item 162U) has a polygon shape having facets (Paragraph 0054) extending from semiconductor protrusion structures with an increase from the first thickness to a fourth thickness that is greater than the first thickness.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the drain layers has a polygon shape having facets extending from an end of each of the plurality of semiconductor protrusion structures to each of the plurality of cell capacitors, with an increase from the first thickness to a fourth thickness that is greater than the first thickness because it allows the source layer to have a large lateral width (Seong Paragraph 0054) such that good contact with the bitline may be made.
Regarding claim 13, the combination of Shin, Li and Seong teaches all of the elements of the claimed invention as stated above.
Shin does not teach wherein each of the drain layers extends toward each of the plurality of cell capacitors with a decrease in a thickness from the fourth thickness and then contacts respective ones of each of the plurality of cell capacitors.
However, when the shape of the drain taught by Seong is incorporated into the Shin reference, each of the drain layers will extend toward each of the plurality of cell capacitors with a decrease in a thickness from the fourth thickness and then contacts respective ones of each of the plurality of cell capacitors.
Regarding claim 14, Shin further teaches where each of the drain layers (Item SD2) has the first thickness between each of the plurality of semiconductor protrusion structures (When combined with Li as stated in the rejection of claim 11 above) and each of the plurality of cell capacitors (Item DS).
Regarding claim 17, Shin further teaches a plurality of word line contacts (Items WL1) extending in the vertical direction, connected to the plurality of gate structures (Items WL2), and arranged apart from one another in the second horizontal direction, wherein the plurality of word line contacts are connected to gate structures at different vertical levels among the plurality of gate structures.
Regarding claim 18, Shin further teaches the plurality of gate structures each cover a top surface and a bottom surface of each of the semiconductor protrusion structures and two side surfaces connecting the top surface and the bottom surface, to surround each of the semiconductor protrusion structures, and a bottom surface of each of the plurality of word line contacts is in contact with a portion of the plurality of gate films covering a top surface of any one of the plurality of semiconductor protrusion structures.
Allowable Subject Matter
Claims 5, 8, 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have the drain layer having a shape in which two polygons have facets contacting each other along with the other limitations in claims 1 and 2.
Regarding claim 8, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have a value of a horizontal width of the end portion of the semiconductor protrusion structure facing the drain layer is greater than a value of the horizontal width of the other end portion of the semiconductor protrusion structure facing the source layer along with the other limitations in claim 1.
Regarding claim 15, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have, in each of the drain layers, a first drain portion and a second drain portion contact each other, the first drain portion having a polygon shape having facets extending from respective ones of each of the plurality of cell capacitors to an end of respective ones of each of the plurality of semiconductor protrusion structures with increase from the first thickness to a thickness that is greater than the first thickness, the second drain portion having a polygon shape having facets extending from the end of each of the plurality of semiconductor protrusion structures to each of the plurality of the respective ones of the cell capacitors with increase from the first thickness to a thickness that is greater than the first thickness along with the limitations in claim 11.
Regarding claim 16, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have, where a maximum thickness of each of the drain layers is greater than a maximum thickness of each of the source layers along with the limitations in claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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