Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references cited in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Amendment
The preliminary amendment filed 11/05/2025 has been entered. Claims 1-20 remain pending in the present Office Action.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a plurality of components operable to perform computing tasks” in claim 1;
“a plurality of memory devices operable to provide memory and storage services to the computing tasks” in claim 1;
“a network manager configured to allocate channels, through the bus, for the computing tasks to access the memory and storage services” in claim 1;
“wherein the plurality of components are configured to provide timing data of the computing tasks to the network manager” in claim 3;
“wherein the network manager is configured to identify, for each of the virtual channels, a set of rules for communications over the bus to guarantee requirements specified in the timing data to be met in a deterministic way” in claim 3;
“wherein the network manager is configured to adjust a first virtual channel for a first computing task having a first urgency level, in allocation of a second virtual channel for a second computing task having a second urgency level higher than the first urgency level” in claim 4;
“wherein the network manager is configured to adjust the first virtual channel via at least: a change of a host of data of the first computing task from a first memory device to a second memory device; a change of a host of the first computing task; a change of a timing requirement of the first virtual channel; or a pause of usages of the first virtual channel by the first computing task” in claim 5;
“an analog compute module configured to perform at least a portion of inference computations in an analog form” in claim 6;
“a plurality of components configured to perform computing tasks” in claim 19; and
“a plurality of memory devices configured to provide memory and storage services over the networking bus” in claim 19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Regarding the limitation i) “a plurality of components operable to perform computing tasks” identified in claim 1 above, the Specification teaches each “component” may be a CPU, GPU, or another form of a processor chipset which perform computing tasks, e.g. by executing an application or routine (see Specification: [0005], [0022], [0183]-[0185] and [0188]).
Regarding the limitation ii) “a plurality of memory devices operable to provide memory and storage services to the computing tasks” identified in claim 1 above, the Specification teaches each “memory device” may include/be any combination of non-volatile or volatile memory components, where volatile memory devices may include RAM, DRAM, SDRAM, and non-volatile memory components may include NAND type flash memory and write in-place memory or arrays of memory cells, all of which may store data, e.g. having data read from, written to, or erased (“provide memory and storage services”) for the components performing the computing tasks (see Specification: [0188]-[0121]).
Regarding the limitation iii) “a network manager configured to allocate channels, through the bus, for the computing tasks to access the memory and storage services” identified in claim 1, the Specification teaches the network manager can include a logic circuit to perform the computations for allocation, reservation, and adjustments of a virtual channel, or that it may be implemented by one or more of the components, memory devices, or agents hosted on the components (see Spec: [0045], [0051]-[0054]). The network manager is disclosed as allocating virtual channels by allocating resources of the networking bus and by scheduling/shaping communication traffic over the networking bus to meet requirements of received timing data (see Specification [0022], [0025], and [0039]).
Regarding the limitation iv) “wherein the plurality of components are configured to provide timing data of the computing tasks to the network manager” identified in claim 3, the Specification teaches the components (e.g. the CPU, GPU, or another processor chipset; see Specification: [0005], [0183]-[0185] and [0188]), having an agent, e.g. hosted on the component, that identifies timing data of the computing tasks and communicating the timing data to the network manager (see Specification: [0021], [0038], [0043], and [0168]).
Regarding the limitation v) wherein the network manager is configured to identify, for each of the virtual channels, a set of rules for communications over the bus to guarantee requirements specified in the timing data to be met in a deterministic way” identified in claim 3, the Specification teaches the network manager can include a logic circuit to perform the computations for allocation, reservation, and adjustments of a virtual channel, or that it may be implemented by one or more of the components, memory devices, or agents hosted on the components (see Spec: [0045], [0051]-[0054]). The network manager is disclosed as scheduling/shaping communication traffic over the networking bus to meet requirements of received timing data, e.g., by identifying rules which identify the use of physical connection(s) in the networking bus and identifying the timing of communications involved in the physical connections (see Specification [0022], [0025], [0039], [0046], and [0163]).
Regarding the limitations vi) “wherein the network manager is configured to adjust a first virtual channel for a first computing task having a first urgency level, in allocation of a second virtual channel for a second computing task having a second urgency level higher than the first urgency level” identified in claim 4 and vii) “wherein the network manager is configured to adjust the first virtual channel via at least: a change of a host of data of the first computing task from a first memory device to a second memory device; a change of a host of the first computing task; a change of a timing requirement of the first virtual channel; or a pause of usages of the first virtual channel by the first computing task” identified in claim 5, the Specification teaches the network manager can include a logic circuit to perform the computations for allocation, reservation, and adjustments of a virtual channel, or that it may be implemented by one or more of the components, memory devices, or agents hosted on the components (see Spec: [0045], [0051]-[0054]). The network manager is disclosed as dynamically allocating virtual channels by reserving/adjusting resources of the networking bus and by scheduling/shaping communication traffic over the networking bus for different virtual channels (see Specification [0022]-[0023], [0028]-[0031] and [0039]).
Regarding the limitation viii) “an analog compute module configured to perform at least a portion of inference computations in an analog form” identified in claim 6, the Specification teaches the analog compute module having an array of memory cells programmable to store weight matrices of an artificial neural network and perform multiplication and accumulation operations in an analog form, or alternatively a memristor crossbar array, or implemented as an integrated circuit device (see Specification: [0032]-[0033], [0071]-[0072], and [0079]).
Regarding the limitation ix) “a plurality of components configured to perform computing tasks” identified in claim 19 above, the Specification teaches each “component” may be a CPU, GPU, or another form of a processor chipset which perform computing tasks, e.g. by executing an application or routine (see Specification: [0005], [0022], [0183]-[0185] and [0188]). As such, the broadest reasonable interpretation of “components configured to perform computing tasks” are any processor devices/chipsets such as a CPU, GPU, or equivalents known in the art performing compute tasks, e.g. via executing applications, routines, or equivalents.
Regarding the limitation x) “a plurality of memory devices configured to provide memory and storage services over the networking bus” identified in claim 19 above, the Specification teaches each “memory device” may include/be any combination of non-volatile or volatile memory components, where volatile memory devices may include RAM, DRAM, SDRAM, and non-volatile memory components may include NAND type flash memory and write in-place memory or arrays of memory cells, all of which may store data, e.g. having data read from, written to, or erased over the networking bus (“provide memory and storage services”) for the components performing the computing tasks (see Specification: [0188]-[0121]).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3, 8-11, and 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the virtual channels" in line 3. There is insufficient antecedent basis for this limitation in the claim. This limitation appears to be referring the “channels” recited in claim 1; however, the channels recited in claim 1 are not “virtual channels”. Thus, claim 3 should be amended as follows: “the [[virtual]] channels”.
Claim 8 recites the limitation "the timing data" in line 2. There is insufficient antecedent basis for this limitation in the claim. Timing data is previously recited in claim 3; however, claim 8 does not depend from claim 3. Accordingly, claim 8 should be amended as follows: “[[the]] timing data”.
Claims 9-11 depend from claim 8, and therefore inherit the deficiencies of claim 8.
Claim 13 recites the limitation "the virtual channels" in line 7. There is insufficient antecedent basis for this limitation in the claim. This limitation appears to be referring the “channels” recited in claim 12; however, the channels recited in claim 12 are not “virtual channels”. Thus, claim 13 should be amended as follows: “the [[virtual]] channels”.
Claims 14-18 depend from claim 13, and therefore inherit the deficiencies of claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dugast et al. (U.S. Pub. No. 2021/0377150), hereinafter Dugast, in view of Lautenschlaeger et al. (U.S. Pub. No. 2023/0026435), hereinafter Lautenschlaeger.
Regarding claim 1, Dugast teaches A computing system, comprising:
a plurality of components operable to perform computing tasks (Fig. 1, platforms 102, each containing processor(s) 306, executing applications 108; [0008] – “System 100 includes platforms 102 (e.g., 102A, B, and C)”; [0104] – “a platform 102 (e.g., 102A-C) may execute an application 108 (e.g., 108A-C)”; [0015] – “Application 108 may be executed by logic (e.g., a processor) of a platform 102”; [0054] – “platform 102 comprises […] a processor 306”; [0062] – “Processor 306 may comprise any suitable process, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, an SOC, or other device to execute code (e.g., software instructions). Processor 306, in the depicted embodiment, includes two processing elements (cores 308A and 308B in the depicted embodiment)”);
a plurality of memory devices operable to provide memory and storage services to the computing tasks (FIG. 1, memory pools 106 comprising memory 120; [0008] – “memory pools 106 (e.g., 106A, . . . 106N)”; [0016] – “Execution of the application 108 may include executing various memory flows 114, where a memory flow may comprise any number of reads from or writes to memory. The memory may be local to the platform or remote from the platform (e.g., within memory 120 of a memory pool 106).”; [0026] – “write requests from an application 108 and may provide data specified in these requests to a memory for storage therein”; [0035] – “A memory 120 may store any suitable data, such as data used by one or more applications 108 to provide the functionality of a platform 102.”; [0039] – “Memory 120 may comprise any suitable types of memory and are not limited to a particular speed, technology, or form factor of memory in various embodiments. For example, memory 120 may comprise one or more disk drives (such as solid-state drives), memory cards, memory modules (e.g., dual in-line memory modules) that may be inserted in a memory socket, or other types of memory devices.”);
a network of physical connections configured between the components and the memory devices […] for the computing tasks to access the memory and storage services (TSN network 104 and NICs 112 and 128 comprising TSN circuitry 116 and 124; [0027] – “When a memory request references memory that is part of a memory pool 106, the memory controller 110 forward the request to a NIC 112, which sends the request via TSN network 104, to a NIC 118 of the corresponding memory pool 106. The NIC 118 may then pass the request to memory controller 122 to access the memory 120.”; [0028] – “Various components along the path from the memory controller 110 to the memory 120 of the memory pool may include circuitry enabling TSN. For example, NIC 112 includes TSN circuitry 116, components (e.g., switches) of TSN network 104 may include TSN circuitry, NIC 118 includes TSN circuitry 124, and memory controller 122 includes TSN circuitry 126.”; [0029] – “NIC 112 may be used for the communication of signaling and/or data between platform 102, one or more networks (e.g., TSN network 104), and/or one or more devices or systems coupled to one or more networks ( e.g., memory pools 106). […] A TSN network utilizing Ethernet communications […] A NIC may include one or more physical ports that may couple to a cable (e.g., an Ethernet cable). In various embodiments a NIC may be integrated with a chipset of a platform (e.g., may be on the same integrated circuit or circuit board as a processor of the platform) or may be on a different integrated circuit or circuit board that is electromechanically coupled to the chipset.”; [0034] – “a given physical network”; [0041] – “The TSN network 104 couples platforms 102 to memory pools 106 via a series of TSN switches 202. In the embodiment depicted, a TSN switch 202 comprises switching fabric 204, queues 206, gates 208, traffic class table 210, gate control list 212, and TSN controller 214. Any suitable TSN component in system 100 may comprise any one or more of the components of TSN switch 202, where a TSN component may include, for example, a TSN switch 202, other component of the TSN network 104, or TSN circuitry of a component of a platform 102 or memory pool 106 (e.g., TSN circuitry 116, 124, 126).” [0048] – “By utilizing the TSN network 104 and the various TSN circuitry in a platform 102 and a memory pool 106, the traffic associated with memory pooling may share the TSN network 104”); and
a network manager configured to allocate channels, through the [network of physical connections], for the computing tasks to access the memory and storage services ([0013] – “Thus, in some embodiments, an end-to-end channel is setup between the host (e.g., a platform 102) and the memory controller ( e.g., 122) of a memory pool (e.g., 106) that guarantees a fixed latency for requests referencing an address within a particular memory address range.” [0033] – “memory controller 122 includes one or more request queues that are dedicated for traffic sent via a TSN channel (e.g., traffic sent by platforms 102 over the TSN network 104 that has a guaranteed latency). Utilizing these requests queues, the memory controller 122 may guarantee a fixed latency for such request queues”; [0034] – “Another TSN feature offered by TSN endpoints (e.g., memory pool 106) compliant with IEEE 802.1 Qbv (Enhancements for Scheduled Traffic) is queuing disciplines which controls hardware queuing mechanism support. This permits allocation of one hardware queue for memory pooling traffic, to reduce interference with other traffic classes. An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0060] – “NIC 112 includes a plurality of hardware queues 314 to store incoming or outgoing packets (or packet identifiers). In some embodiments, one or more of the hardware queues 314 may be dedicated for memory pooling traffic (e.g., to reduce interference to or by other traffic classes). In some embodiments, a hardware queue 314 may be reserved for a particular class of traffic (e.g., for guaranteed latency traffic).”).
Dugast fails to expressly teach the network of physical connections configured to form a bus, and that the channels are allocated through the bus.
However, Lautenschlaeger teaches the network of physical connections configured to form a bus, where channels are through the bus ([0038] – “Networked devices may communicate across a network using an Ethernet protocol stack. Ethernet advantageously allows efficient use of network bandwidth through packet switching, supports multicast and broadcast traffic, and the network infrastructure is already widely deployed and commonly supported by devices and so is readily available for networking of devices. In particular, packet switching in Ethernet permits link infrastructure to have a ‘backbone’/′bus' configuration, whereby different data channels may be served by common infrastructure, i.e., network cabling/switches. This may advantageously minimise the physical infrastructure required to network devices.”; [0043]-[0044] – “an aspect of the present disclosure implements a time-sensitive network (TSN) over a TDM backbone architecture utilised with a TDM shim layer inserted into the Ethernet protocol stack between the PHY and the MAC layers […] Aspects of the proposal may thus advantageously provide an efficient means for transporting both TSN/CBR traffic and conventional packet-switched traffic via shared Ethernet physical layer infrastructure.”; [0048] – “Ethernet bus 112 comprises a backbone medium 113 […] Ethernet bus 112 operates as an enhanced Ethernet physical layer network whereby TSN traffic between the machine-machine controller pairs 103-106, 104-107, and 105-108, and conventional packet-switched traffic between the IT devices 109 to 111 and IT server 102, is communicated concurrently.”; [0087] – “the TDM multiplexor may identify time slots reserved for transmission of TNS data via the Ethernet bus.”).
Dugast and Lautenschlaeger are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art that the “network of physical connections configured between the components and the memory devices” through which virtual channels are allocated, (specifically the Ethernet based TSN network) taught by Dugast may form a bus, e.g. an Ethernet bus, as taught by Lautenschlaeger. Lautenschlaeger teaches the network infrastructure for Ethernet is already widely supported, and that an Ethernet network having a backbone/bus configuration in which different data channels are served by common physical infrastructure provides the benefit of minimizing the physical infrastructure required to network between communicating devices (see Lautenschlaeger: [0038]).
Regarding claim 2, the combination of Dugast in view of Lautenschlaeger teaches The computing system of claim 1. Dugast further teaches wherein the [network of physical connections] is a time sensitive networking [network] ([0008] – “platforms 102 (e.g., 102A, B, and C) coupled via a TSN network 104 to memory pools 106 (e.g., 106A, . . . 106N).”; [0011] – “time sensitive networking (TSN) are included in the memory pooling infrastructure. The platforms 102 may leverage TSN-based connectivity in addition to regular connectivity ( e.g., in which a maximum latency is not guaranteed) to a memory pool. TSN achieves determinism over the network (e.g., an Ethernet network)”).
Dugast does not, however Lautenschlaeger teaches the bus is a time-sensitive networking bus ([0038] – “a ‘backbone’/′bus' configuration, whereby different data channels may be served by common infrastructure, i.e., network cabling/switches. This may advantageously minimise the physical infrastructure required to network devices.”; [0043]-[0044] – “an aspect of the present disclosure implements a time-sensitive network (TSN) over a TDM backbone architecture utilised with a TDM shim layer inserted into the Ethernet protocol stack between the PHY and the MAC layers […] Aspects of the proposal may thus advantageously provide an efficient means for transporting both TSN/CBR traffic and conventional packet-switched traffic via shared Ethernet physical layer infrastructure.”; [0048] – “Ethernet bus 112 comprises a backbone medium 113 […] Ethernet bus 112 operates as an enhanced Ethernet physical layer network whereby TSN traffic between the machine-machine controller pairs 103-106, 104-107, and 105-108, and conventional packet-switched traffic between the IT devices 109 to 111 and IT server 102, is communicated concurrently.”; [0087] – “the TDM multiplexor may identify time slots reserved for transmission of TNS data via the Ethernet bus.”).
It would have been obvious to one of ordinary skill in the art that the “network of physical connections configured between the components and the memory devices” through which virtual channels are allocated, (specifically the Ethernet based TSN network) taught by Dugast may form a bus, e.g. an Ethernet bus, as taught by Lautenschlaeger. Lautenschlaeger teaches the network infrastructure for Ethernet is already widely supported, and that an Ethernet network having a backbone/bus configuration in which different data channels are served by common physical infrastructure provides the benefit of minimizing the physical infrastructure required to network between communicating devices (see Lautenschlaeger: [0038]). Further, the Ethernet bus enhanced with time-sensitive networking taught by Lautenschlaeger provides the advantage of enabling sharing of the bus communications network for both time-sensitive traffic and relatively time-insensitive traffic (see Lautenschlaeger: [0048]).
Regarding claim 12, Dugast teaches A method, comprising:
performing, in a plurality of components of a computing system, computing tasks (Fig. 1, platforms 102, each containing processor(s) 306, executing applications 108; [0008] – “System 100 includes platforms 102 (e.g., 102A, B, and C)”; [0104] – “a platform 102 (e.g., 102A-C) may execute an application 108 (e.g., 108A-C)”; [0015] – “Application 108 may be executed by logic (e.g., a processor) of a platform 102”; [0054] – “platform 102 comprises […] a processor 306”; [0062] – “Processor 306 may comprise any suitable process, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, an SOC, or other device to execute code (e.g., software instructions). Processor 306, in the depicted embodiment, includes two processing elements (cores 308A and 308B in the depicted embodiment)”);
providing, via a plurality of memory devices in the computing system, memory and storage services to the computing tasks (FIG. 1, memory pools 106 comprising memory 120; [0008] – “memory pools 106 (e.g., 106A, . . . 106N)”; [0016] – “Execution of the application 108 may include executing various memory flows 114, where a memory flow may comprise any number of reads from or writes to memory. The memory may be local to the platform or remote from the platform (e.g., within memory 120 of a memory pool 106).”; [0026] – “write requests from an application 108 and may provide data specified in these requests to a memory for storage therein”; [0035] – “A memory 120 may store any suitable data, such as data used by one or more applications 108 to provide the functionality of a platform 102.”; [0039] – “Memory 120 may comprise any suitable types of memory and are not limited to a particular speed, technology, or form factor of memory in various embodiments. For example, memory 120 may comprise one or more disk drives (such as solid-state drives), memory cards, memory modules (e.g., dual in-line memory modules) that may be inserted in a memory socket, or other types of memory devices.”);
connecting, via a network of physical connections configured between the components and the memory devices […], the plurality of components having the computing tasks to access the memory and storage services (TSN network 104 and NICs 112 and 128 comprising TSN circuitry 116 and 124; [0027] – “When a memory request references memory that is part of a memory pool 106, the memory controller 110 forward the request to a NIC 112, which sends the request via TSN network 104, to a NIC 118 of the corresponding memory pool 106. The NIC 118 may then pass the request to memory controller 122 to access the memory 120.”; [0028] – “Various components along the path from the memory controller 110 to the memory 120 of the memory pool may include circuitry enabling TSN. For example, NIC 112 includes TSN circuitry 116, components (e.g., switches) of TSN network 104 may include TSN circuitry, NIC 118 includes TSN circuitry 124, and memory controller 122 includes TSN circuitry 126.”; [0029] – “NIC 112 may be used for the communication of signaling and/or data between platform 102, one or more networks (e.g., TSN network 104), and/or one or more devices or systems coupled to one or more networks ( e.g., memory pools 106). […] A TSN network utilizing Ethernet communications […] A NIC may include one or more physical ports that may couple to a cable (e.g., an Ethernet cable). In various embodiments a NIC may be integrated with a chipset of a platform (e.g., may be on the same integrated circuit or circuit board as a processor of the platform) or may be on a different integrated circuit or circuit board that is electromechanically coupled to the chipset.”; [0034] – “a given physical network”; [0041] – “The TSN network 104 couples platforms 102 to memory pools 106 via a series of TSN switches 202. In the embodiment depicted, a TSN switch 202 comprises switching fabric 204, queues 206, gates 208, traffic class table 210, gate control list 212, and TSN controller 214. Any suitable TSN component in system 100 may comprise any one or more of the components of TSN switch 202, where a TSN component may include, for example, a TSN switch 202, other component of the TSN network 104, or TSN circuitry of a component of a platform 102 or memory pool 106 (e.g., TSN circuitry 116, 124, 126).” [0048] – “By utilizing the TSN network 104 and the various TSN circuitry in a platform 102 and a memory pool 106, the traffic associated with memory pooling may share the TSN network 104”); and
allocating, via a network manager configured in the computing system, channels in the [network of physical connections] for the computing tasks to access the memory and storage services ([0013] – “Thus, in some embodiments, an end-to-end channel is setup between the host (e.g., a platform 102) and the memory controller ( e.g., 122) of a memory pool (e.g., 106) that guarantees a fixed latency for requests referencing an address within a particular memory address range.” [0033] – “memory controller 122 includes one or more request queues that are dedicated for traffic sent via a TSN channel (e.g., traffic sent by platforms 102 over the TSN network 104 that has a guaranteed latency). Utilizing these requests queues, the memory controller 122 may guarantee a fixed latency for such request queues”; [0034] – “Another TSN feature offered by TSN endpoints (e.g., memory pool 106) compliant with IEEE 802.1 Qbv (Enhancements for Scheduled Traffic) is queuing disciplines which controls hardware queuing mechanism support. This permits allocation of one hardware queue for memory pooling traffic, to reduce interference with other traffic classes. An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0060] – “NIC 112 includes a plurality of hardware queues 314 to store incoming or outgoing packets (or packet identifiers). In some embodiments, one or more of the hardware queues 314 may be dedicated for memory pooling traffic (e.g., to reduce interference to or by other traffic classes). In some embodiments, a hardware queue 314 may be reserved for a particular class of traffic (e.g., for guaranteed latency traffic).”).
Dugast fails to expressly teach the network of physical connections configured to form a bus, and that the channels are allocated in the bus.
However, Lautenschlaeger teaches the network of physical connections configured to form a bus, where channels are in the bus ([0038] – “Networked devices may communicate across a network using an Ethernet protocol stack. Ethernet advantageously allows efficient use of network bandwidth through packet switching, supports multicast and broadcast traffic, and the network infrastructure is already widely deployed and commonly supported by devices and so is readily available for networking of devices. In particular, packet switching in Ethernet permits link infrastructure to have a ‘backbone’/′bus' configuration, whereby different data channels may be served by common infrastructure, i.e., network cabling/switches. This may advantageously minimise the physical infrastructure required to network devices.”; [0043]-[0044] – “an aspect of the present disclosure implements a time-sensitive network (TSN) over a TDM backbone architecture utilised with a TDM shim layer inserted into the Ethernet protocol stack between the PHY and the MAC layers […] Aspects of the proposal may thus advantageously provide an efficient means for transporting both TSN/CBR traffic and conventional packet-switched traffic via shared Ethernet physical layer infrastructure.”; [0048] – “Ethernet bus 112 comprises a backbone medium 113 […] Ethernet bus 112 operates as an enhanced Ethernet physical layer network whereby TSN traffic between the machine-machine controller pairs 103-106, 104-107, and 105-108, and conventional packet-switched traffic between the IT devices 109 to 111 and IT server 102, is communicated concurrently.”; [0087] – “the TDM multiplexor may identify time slots reserved for transmission of TNS data via the Ethernet bus.”).
Dugast and Lautenschlaeger are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art that the “network of physical connections configured between the components and the memory devices” through which virtual channels are allocated, (specifically the Ethernet based TSN network) taught by Dugast may form a bus, e.g. an Ethernet bus, as taught by Lautenschlaeger. Lautenschlaeger teaches the network infrastructure for Ethernet is already widely supported, and that an Ethernet network having a backbone/bus configuration in which different data channels are served by common physical infrastructure provides the benefit of minimizing the physical infrastructure required to network between communicating devices (see Lautenschlaeger: [0038]).
Claims 3-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Dugast in view of Lautenschlaeger as applied to claims 1 and 12 above, and further in view of Mong et al. (U.S. Pub. No. 2019/0322298), hereinafter Mong.
Regarding claim 3, the combination of Dugast in view of Lautenschlaeger teaches The computing system of claim 1. Dugast, in view of Lautenschlaeger as applied to claim 1, further teaches timing data of the computing tasks […] ([0010] – “A key requirement for various applications is the execution of certain flows that require predictable and deterministic latencies.”; [0014] – “an application 108 (e.g., 108A-C) that includes various memory flows 114 (e.g., 308A-C).”; [0017] – “a memory flow may be a flow with guaranteed latency, where the latency may include, e.g., an elapsed amount of time between a request for memory contents and retrieval of the memory contents for access by the requester (e.g., application executing the memory flow). In various embodiments, the latency that is guaranteed may be for any suitable portion of the request path. For example, the latency may be guaranteed for the amount of time from when a request is received at a memory controller 110 up to the time the data is received back at the memory controller 110”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic. These memory-specific properties may be passed to the operating system of the platform 102 […] The operating system may use these properties to match memory locations (e.g., memory pools) with requirements of the various memory flows of the platform 102”); and wherein the network manager is configured to identify, for each of the virtual channels, a set of rules for communications over the bus to guarantee requirements specified in the timing data to be met in a deterministic way ([0011] – “TSN achieves determinism over the network (e.g., an Ethernet network) by leveraging time synchronization and a schedule that is shared between network components. In embodiments, the architecture defines queues based on time, thereby guaranteeing a bounded maximum latency for scheduled traffic”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic.”; [0034] – “An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0042] – “A TSN path (e.g., through one or more components of platform 102, through network 104, and through one or more components of memory pool 106) may exhibit various characteristics, such as low and deterministic transmission latency (at least for particular network traffic) and synchronized clocks. Streams passing through the TSN path may be given latency and/or bandwidth guarantees. Scheduling and traffic shaping capabilities of the TSN components enable different traffic classes with different priorities on the TSN path, where each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency. In various embodiments, transmission times with guaranteed end-to-end latency may be achieved using one or more priority classes”; [0046]-[0048] – “the gate control list 212 may be coordinated among the components of the TSN path so that traffic of the same priority may be communicated through the TSN path during the time dedicated to that priority. This may ensure a guaranteed maximum latency (and/or a guaranteed bandwidth) for sending frames. In various embodiments, communication over the TSN path may utilize a time-division multiple access scheme in which communication over the TSN path is split into repeating time cycles with fixed lengths. Within a cycle, different time slices may be assigned to one or more priorities. This allows exclusive use of a transmission medium for a period of time for a traffic class that needs a transmission guarantee.”).
For the same reasons presented with respect to claim 1, it would have been obvious to one of ordinary skill in the art that the Ethernet based TSN network taught by Dugast may form a bus, e.g. an Ethernet bus, as taught by Lautenschlaeger, where the communications occur over the bus.
The combination of Dugast in view of Lautenschlaeger fails to expressly teach wherein the plurality of components are configured to provide timing data of the computing tasks to the network manager.
However, Mong teaches wherein the plurality of components are configured to provide timing data of the computing tasks to the network manager ([0107] – “The systems and methods described herein address how TSN should interpret and react to the QoS requirements of the data distribution service. By mapping configuration parameters of the data distribution service to the configuration parameters of TSN, a scheduler of TSN can create schedules that support QoS requirements of the data distribution service for time-critical control applications.”; [0116] – “the network through which data is communicated and the applications communicating the data (e.g., the devices 802, 804, 808, 814, 818).”; [0123] – “The QoS parameters 828 of the devices 802, 804, 808, 814, 818 may be defined by one or more, or a combination, of the deadline parameter, latency parameter, and/or transport priority parameter. The QoS parameters 828 are then used to determine data traffic schedules within the TSN using the data distribution service 824. Data traffic schedules can dictate communication paths and times at which data is communicated within the network.”; [0128] – “The method 1000 may be used by the control system 818 to determine schedules for communicating data within the network 900 to satisfy the QoS parameters 828 of various devices 802, 804, 808, 814, 818.”; [0129] – “QoS parameters 828 for the devices 802, 804, 808, 814, 818 are determined. These parameters may be input by an operator or user of the powered system or control system 818, or may be communicated to the control system 818 by the devices 802, 804, 808, 814, 818.”; [0150] – “the scheduler 1118 and the traffic shaper 1120 communicate with each other to determine what communication schedules are feasible to achieve the QoS parameter(s) 828 received from the control system 818.”).
Mong is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger to incorporate the teachings of Mong. Doing so would enable dynamic configuration of the time sensitive network to meet QoS requirements of a plurality of time-critical applications (see Mong: [0023], [0107], [0151], and [0154]).
Regarding claim 4, the combination of Dugast in view of Lautenschlaeger teaches The computing system of claim 1. Dugast further teaches a first virtual channel for a first computing task having a first urgency level ([0017] – “a memory flow may be a lower priority memory flow and may rely on best efforts to retrieve the memory”; [0033]-[0034] – “memory controller 122 includes one or more request queues that are dedicated for traffic sent via a TSN channel (e.g., traffic sent by platforms 102 over the TSN network 104 that has a guaranteed latency). Utilizing these requests queues, the memory controller 122 may guarantee a fixed latency for such request queues while using best effort scheduling for the other request queues. Another TSN feature offered by TSN endpoints (e.g., memory pool 106) compliant with IEEE 802.lQbv (Enhancements for Scheduled Traffic) is queuing disciplines which controls hardware queuing mechanism support. This permits allocation of one hardware queue for memory pooling traffic, to reduce interference with other traffic classes. An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0042] – “Scheduling and traffic shaping capabilities of the TSN components enable different traffic classes with different priorities on the TSN path, where each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency.”; [0048] – “Low priority IP-based communication can continue to take place with another "best effort" traffic class.”), [and] a second virtual channel for a second computing task having a second urgency level higher than the first urgency level ([0017] – “a memory flow may be a flow with guaranteed latency”; [0033]-[0034] and [0042]– see portions cited above with respect to prioritizing latency guaranteed traffic using virtual channels mapped to hardware queues ; [0045] – “The traffic class table 210 may map a priority indication ( e.g., traffic class) of a packet to a queue 206. […] In some embodiments, a high priority class may be mapped to multiple queues.”; [0047] – “communication over the TSN path may utilize a time-division multiple access scheme in which communication over the TSN path is split into repeating time cycles with fixed lengths. Within a cycle, different time slices may be assigned to one or more priorities. This allows exclusive use of a transmission medium for a period of time for a traffic class that needs a transmission guarantee.”; [0048] – “the TSN components may be compliant with IEEE 802. lQ-2018 (or other standard enabling guaranteed minimum latency for requests) and thus may allow predictable time of delivery by utilizing Ethernet traffic divided into different classes thus ensuring that, at specific times, only one traffic class (or set of traffic classes) has access to the network. This may guarantee the performance of memory pooling traffic without interfering with existing isochronous, low-latency, high-priority traffic.”).
The combination of Dugast in view of Lautenschlaeger fails to expressly teach wherein the network manager is configured to adjust the first virtual channel for a first computing task having a first urgency level in allocation of the second virtual channel for the second computing task having a second urgency level higher than the first urgency level.
However, Mong teaches wherein the network manager is configured to adjust the first virtual channel for a first computing task having a first urgency level in allocation of the second virtual channel for the second computing task having a second urgency level higher than the first urgency level ([0116] – “the network through which data is communicated and the applications communicating the data (e.g., the devices 802, 804, 808, 814, 818).”; [0123] – “The QoS parameters 828 of the devices 802, 804, 808, 814, 818 may be defined by one or more, or a combination, of the deadline parameter, latency parameter, and/or transport priority parameter. The QoS parameters 828 are then used to determine data traffic schedules within the TSN using the data distribution service 824. Data traffic schedules can dictate communication paths and times at which data is communicated within the network”; [0127] – “The network 826 can be an Ethernet based network that communicates different categories or groups or types of data according to different priorities. For example, the network 826 can communicate time sensitive data according to the schedule or schedules determined by the control system 818 to achieve or maintain the QoS parameters 828 of certain devices 802, 804, 808, 814, 818. The network 826 can communicate other data between or among the same or other devices 802, 804, 808, 814, 818 as "best effort" traffic or rate constrained traffic. Best effort traffic includes the communication of data between or among at least some of the devices 802, 804, 808, 814, 818 that is not subject to or required to meet the QoS parameters 828 of the devices 802, 804, 808, 814, 818. This data may be communicated at a higher priority than the data communicated in rate constrained traffic, but at a lower priority than the data communicated according to the schedules dictated by the control system 818 to meet or achieve the QoS parameters 828 (also referred to herein as time sensitive traffic). […] The time sensitive data, the best effort traffic, and the rate constrained traffic are communicated within or through the same network 826, but with different priorities. The time sensitive data is communicated at designated times or within designated time periods, while the best effort traffic and rate constrained traffic is attempted to be communicated in a timely manner, but that may be delayed to ensure that the time sensitive data is communicated to achieve or maintain the QoS parameters 828.”; [0135] – “The selected schedules may be updated as needed. For example, if one or more devices are added to the powered system, the control system 818 may evaluate feasible schedules for the added devices in light of the currently used selected schedules and select feasible schedules for the added devices. This can ensure that the QoS parameters 828 of the added devices are met while avoiding having to take down the entire powered system and re-evaluating the schedules of all devices.”; [0136] – “writer devices and reader devices (e.g., Writers and Readers) are able to directly communicate directly with TSN virtual link registration devices (e.g., Talkers and Listeners) to enable TSN stream reservation that dynamically changes to reflect the Quality-of-Service (QoS) requirements”; [0142] – “The talker 1122 and listener 1124 are the devices within the time sensitive network 826 that establish a communication link (also referred to as a virtual link) through which data or information is communicated between the writer 1110 and the reader 1112.”; [0147] – “the control system 818 may direct other changes 1130 to communications. For example, a new device 1114, 1116, new talker 1122, and/or new listener 1124 may be added to the time sensitive network 826. As another example, the control system 818 may direct that new or different information is communicated to and/or from one or more devices 1114, and/or may change when information is communicated with and/or between the devices 1114, 1116.”; [0151] – “Based on receipt of the network availability 1134, the traffic shaper 1120 can determine when different data packets or frames of the non-time sensitive communications can occur. This can involve the traffic shaper 1120 delaying communication of one or more groups of packets, frames, or datagrams to bring the communication of the groups into a traffic profile. The writers 1110 and the readers 1112 communicating non-time sensitive communications may then be restricted to communicating the data packets, frames, or datagrams at the times restricted by the traffic profile.”; [0153] – “the traffic shaper 1120 can restrict (or only permit) the communication of rate constrained traffic and best effort traffic within the bandwidths represented by the traffic profile 1200 at the associated times.”; [0157]-[0160] – “At 1304, an available bandwidth for communication of non-time sensitive communications of the data distribution service in the time sensitive network is determined. The traffic shaper can examine the bandwidth that is not reserved or scheduled to be used by the time sensitive communications by the scheduler. This remaining amount of bandwidth may be used for the communication of rate constrained communications and/or best effort communications between the writers and the readers of the data distribution service. At 1306, a permissible traffic profile for the communication of the non-time sensitive communications is determined. The traffic shaper can determine this profile as representative of how much non-time sensitive data can be communicated at different times, based on the available bandwidth for non-time sensitive communications that are available at different times. At 1308, the time sensitive communications and non-time sensitive communications of the data distribution service are communicated in the time sensitive network. The time sensitive communications may be communicated along or via communication or virtual links between some writers and readers using sufficient bandwidth to ensure that the time sensitive communications occur no later than designated times or within designated time periods. The non-time sensitive communications may be communicated along or via communication or virtual links between the same and/or different writers and readers, but according to the traffic profile determined by the traffic shaper. At 1310, a determination is made as to whether any changes to the communication of data of the data distribution service in the time sensitive network is requested or directed (e.g., by the control system). […] If a change in communication is requested or directed by the control system, then flow of the method 1300 can return toward 1302. For example, the method 1300 can again determine what bandwidth is needed for the communication of time sensitive communications, what bandwidth is available for the communication of non-time sensitive communications, and the traffic profile for use in communicating the non-time sensitive communications subject to the communication changes.”; [0168] – “a network calculus engine may work with the scheduler 1118 (or the scheduler 1118 may use network calculus) to determine how to set network traffic latency requirements for each, or at least one or more, path or route through the network. […] For example, the network calculus engine could suggest to the operator which virtual links would benefit most or more than others from easing traffic load or increasing maximum (or another upper limit on) latency.” In response to a change, e.g. a new device implementing an application, the scheduler generates a new schedule which reserves (i.e., allocates) times and communication paths for the time sensitive traffic (i.e., traffic of the second computing task having a second urgency level higher than the first urgency level), corresponding to the second virtual channel as taught by Dugast. The traffic shaper then generates an updated traffic profile which specifies updated/adjusted times and bandwidth limits when the best-effort traffic (i.e., traffic of the first computing task having a first urgency level), corresponding to the first virtual channel as taught by Dugast, is able to send communications. Implementing the updated traffic profile may include delaying the best-effort traffic. Further, generating the new schedule in response to changes may include adjusting maximum latency of one or more virtual links (i.e., “virtual channels”).).
Mong is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger to incorporate the teachings of Mong. Doing so would enable dynamic configuration of the time sensitive network to meet QoS requirements of a plurality of time-critical applications (see Mong: [0023], [0107], [0151], and [0154]).
Regarding claim 5, the combination of Dugast in view of Lautenschlaeger and Mong teaches The computing system of claim 4. Mong further teaches wherein the network manager is configured to adjust the first virtual channel via at least: a change of a host of data of the first computing task from a first memory device to a second memory device; a change of a host of the first computing task; a change of a timing requirement of the first virtual channel; or a pause of usages of the first virtual channel by the first computing task ([0123] – “Data traffic schedules can dictate communication paths and times at which data is communicated within the network”; [0127] – “The time sensitive data is communicated at designated times or within designated time periods, while the best effort traffic and rate constrained traffic is attempted to be communicated in a timely manner, but that may be delayed to ensure that the time sensitive data is communicated to achieve or maintain the QoS parameters 828.”; [0142] – “The talker 1122 and listener 1124 are the devices within the time sensitive network 826 that establish a communication link (also referred to as a virtual link) through which data or information is communicated between the writer 1110 and the reader 1112.”; [0147] – “the control system 818 may direct other changes 1130 to communications […] and/or may change when information is communicated with and/or between the devices 1114, 1116.”; [0151] – “Based on receipt of the network availability 1134, the traffic shaper 1120 can determine when different data packets or frames of the non-time sensitive communications can occur. This can involve the traffic shaper 1120 delaying communication of one or more groups of packets, frames, or datagrams to bring the communication of the groups into a traffic profile. The writers 1110 and the readers 1112 communicating non-time sensitive communications may then be restricted to communicating the data packets, frames, or datagrams at the times restricted by the traffic profile.”; [0153] – “the traffic shaper 1120 can restrict (or only permit) the communication of rate constrained traffic and best effort traffic within the bandwidths represented by the traffic profile 1200 at the associated times.”; [0157]-[0160] – “At 1306, a permissible traffic profile for the communication of the non-time sensitive communications is determined. The traffic shaper can determine this profile as representative of how much non-time sensitive data can be communicated at different times, based on the available bandwidth for non-time sensitive communications that are available at different times. […] The non-time sensitive communications may be communicated along or via communication or virtual links between the same and/or different writers and readers, but according to the traffic profile determined by the traffic shaper. At 1310, a determination is made as to whether any changes to the communication of data of the data distribution service in the time sensitive network is requested or directed (e.g., by the control system). […] If a change in communication is requested or directed by the control system, then flow of the method 1300 can return toward 1302. For example, the method 1300 can again determine what bandwidth is needed for the communication of time sensitive communications, what bandwidth is available for the communication of non-time sensitive communications, and the traffic profile for use in communicating the non-time sensitive communications subject to the communication changes.”; [0168] – “a network calculus engine may work with the scheduler 1118 (or the scheduler 1118 may use network calculus) to determine how to set network traffic latency requirements for each, or at least one or more, path or route through the network. […] For example, the network calculus engine could suggest to the operator which virtual links would benefit most or more than others from easing traffic load or increasing maximum (or another upper limit on) latency.” In response to a change, e.g. a new device implementing an application, the scheduler generates a new schedule which reserves (i.e., allocates) times and communication paths for the time sensitive traffic (i.e., traffic of the second computing task having a second urgency level higher than the first urgency level), corresponding to the second virtual channel as taught by Dugast. The traffic shaper then generates an updated traffic profile which specifies updated/adjusted times and bandwidth limits when the best-effort traffic (i.e., traffic of the first computing task having a first urgency level), corresponding to the first virtual channel as taught by Dugast, is permitted (i.e., “a change of a timing requirement of the first virtual channel”). Implementing the updated traffic profile may include delaying the best-effort traffic (i.e. “pause of usages of the first virtual channel by the first computing task”). Further, generating the new schedule in response to changes may include adjusting maximum latency of one or more virtual links (i.e., “virtual channels”) (i.e. “a change of a timing requirement of the first virtual channel”).).
For clarity of the record claim 5 recites a list of limitations in the alternative, i.e., a change of a host of data of the first computing task from a first memory device to a second memory device; a change of a host of the first computing task; a change of a timing requirement of the first virtual channel; or a pause of usages of the first virtual channel by the first computing task. As such, only one of the listed alternatives is required by the claims. The Examiner has cited portions of Mong which teach the alternatives “a change of a timing requirement of the first virtual channel” and “a pause of usages of the first virtual channel by the first computing task”.
It would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger to incorporate the teachings of Mong. Doing so would enable dynamic configuration of the time sensitive network to meet QoS requirements of a plurality of time-critical applications (see Mong: [0023], [0107], [0151], and [0154]).
Regarding claim 13, the combination of Dugast in view of Lautenschlaeger teaches The method of claim 12. Dugast further teaches wherein the [network of physical connections] is a time sensitive networking [network] ([0008] – “platforms 102 (e.g., 102A, B, and C) coupled via a TSN network 104 to memory pools 106 (e.g., 106A, . . . 106N).”; [0011] – “time sensitive networking (TSN) are included in the memory pooling infrastructure. The platforms 102 may leverage TSN-based connectivity in addition to regular connectivity ( e.g., in which a maximum latency is not guaranteed) to a memory pool. TSN achieves determinism over the network (e.g., an Ethernet network)”); and the method further comprises:
[…] timing data of the computing tasks, wherein the timing data identifies urgency levels of the computing tasks and latency requirements of the computing tasks in accessing the memory and storage services ([0010] – “A key requirement for various applications is the execution of certain flows that require predictable and deterministic latencies.”; [0014] – “an application 108 (e.g., 108A-C) that includes various memory flows 114 (e.g., 308A-C).”; [0017] – “a memory flow may be a flow with guaranteed latency, where the latency may include, e.g., an elapsed amount of time between a request for memory contents and retrieval of the memory contents for access by the requester (e.g., application executing the memory flow). In various embodiments, the latency that is guaranteed may be for any suitable portion of the request path. For example, the latency may be guaranteed for the amount of time from when a request is received at a memory controller 110 up to the time the data is received back at the memory controller 110. […] As one more example, a memory flow may be a lower priority memory flow and may rely on best efforts to retrieve the memory (and thus may have neither a guaranteed bandwidth nor latency).”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic. These memory-specific properties may be passed to the operating system of the platform 102 […] The operating system may use these properties to match memory locations (e.g., memory pools) with requirements of the various memory flows of the platform 102”; [0024] – “When a memory controller receives a request specifying a virtual address in the address space 128, the memory controller may process the request based on the specific address space that contains the virtual address. For example, the memory controller may tag the request with a priority identifier that may be used by the components along the path to the destination memory pool 106 to ensure that any bandwidth or latency guarantees are honored during fulfillment of the request.”; [0042] – “each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency.”); and
identifying, by the network manager and for each of the virtual channels, a set of rules for communications over the [network] to guarantee latency requirements specified in the timing data to be met in a deterministic way ([0011] – “TSN achieves determinism over the network (e.g., an Ethernet network) by leveraging time synchronization and a schedule that is shared between network components. In embodiments, the architecture defines queues based on time, thereby guaranteeing a bounded maximum latency for scheduled traffic”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic.”; [0034] – “An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0042] – “A TSN path (e.g., through one or more components of platform 102, through network 104, and through one or more components of memory pool 106) may exhibit various characteristics, such as low and deterministic transmission latency (at least for particular network traffic) and synchronized clocks. Streams passing through the TSN path may be given latency and/or bandwidth guarantees. Scheduling and traffic shaping capabilities of the TSN components enable different traffic classes with different priorities on the TSN path, where each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency. In various embodiments, transmission times with guaranteed end-to-end latency may be achieved using one or more priority classes”; [0046]-[0048] – “the gate control list 212 may be coordinated among the components of the TSN path so that traffic of the same priority may be communicated through the TSN path during the time dedicated to that priority. This may ensure a guaranteed maximum latency (and/or a guaranteed bandwidth) for sending frames. In various embodiments, communication over the TSN path may utilize a time-division multiple access scheme in which communication over the TSN path is split into repeating time cycles with fixed lengths. Within a cycle, different time slices may be assigned to one or more priorities. This allows exclusive use of a transmission medium for a period of time for a traffic class that needs a transmission guarantee.”).
Dugast does not, however Lautenschlaeger teaches the bus is a time-sensitive networking bus ([0038] – “a ‘backbone’/′bus' configuration, whereby different data channels may be served by common infrastructure, i.e., network cabling/switches. This may advantageously minimise the physical infrastructure required to network devices.”; [0043]-[0044] – “an aspect of the present disclosure implements a time-sensitive network (TSN) over a TDM backbone architecture utilised with a TDM shim layer inserted into the Ethernet protocol stack between the PHY and the MAC layers […] Aspects of the proposal may thus advantageously provide an efficient means for transporting both TSN/CBR traffic and conventional packet-switched traffic via shared Ethernet physical layer infrastructure.”; [0048] – “Ethernet bus 112 comprises a backbone medium 113 […] Ethernet bus 112 operates as an enhanced Ethernet physical layer network whereby TSN traffic between the machine-machine controller pairs 103-106, 104-107, and 105-108, and conventional packet-switched traffic between the IT devices 109 to 111 and IT server 102, is communicated concurrently.”; [0087] – “the TDM multiplexor may identify time slots reserved for transmission of TNS data via the Ethernet bus.”).
It would have been obvious to one of ordinary skill in the art that the “network of physical connections configured between the components and the memory devices” through which virtual channels are allocated, (specifically the Ethernet based TSN network) taught by Dugast may form a bus, e.g. an Ethernet bus, as taught by Lautenschlaeger. Lautenschlaeger teaches the network infrastructure for Ethernet is already widely supported, and that an Ethernet network having a backbone/bus configuration in which different data channels are served by common physical infrastructure provides the benefit of minimizing the physical infrastructure required to network between communicating devices (see Lautenschlaeger: [0038]). Further, the Ethernet bus enhanced with time-sensitive networking taught by Lautenschlaeger provides the advantage of enabling sharing of the bus communications network for both time-sensitive traffic and relatively time-insensitive traffic (see Lautenschlaeger: [0048]).
The combination of Dugast in view of Lautenschlaeger fails to expressly teach receiving, in the network manager, timing data of the computing tasks.
However, Mong teaches receiving, in the network manager, timing data of the computing tasks ([0107] – “The systems and methods described herein address how TSN should interpret and react to the QoS requirements of the data distribution service. By mapping configuration parameters of the data distribution service to the configuration parameters of TSN, a scheduler of TSN can create schedules that support QoS requirements of the data distribution service for time-critical control applications.”; [0116] – “the network through which data is communicated and the applications communicating the data (e.g., the devices 802, 804, 808, 814, 818).”; [0123] – “The QoS parameters 828 of the devices 802, 804, 808, 814, 818 may be defined by one or more, or a combination, of the deadline parameter, latency parameter, and/or transport priority parameter. The QoS parameters 828 are then used to determine data traffic schedules within the TSN using the data distribution service 824. Data traffic schedules can dictate communication paths and times at which data is communicated within the network.”; [0128] – “The method 1000 may be used by the control system 818 to determine schedules for communicating data within the network 900 to satisfy the QoS parameters 828 of various devices 802, 804, 808, 814, 818.”; [0129] – “QoS parameters 828 for the devices 802, 804, 808, 814, 818 are determined. These parameters may be input by an operator or user of the powered system or control system 818, or may be communicated to the control system 818 by the devices 802, 804, 808, 814, 818.”; [0150] – “the scheduler 1118 and the traffic shaper 1120 communicate with each other to determine what communication schedules are feasible to achieve the QoS parameter(s) 828 received from the control system 818.”).
Mong is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger to incorporate the teachings of Mong. Doing so would enable dynamic configuration of the time sensitive network to meet QoS requirements of a plurality of time-critical applications (see Mong: [0023], [0107], [0151], and [0154]).
Claim 14 recites substantially the same additional limitations recited in claims 4-5, applied to the method of claim 13. Accordingly, claim 14 is rejected as being unpatentable over Dugast in view of Lautenschlaeger and Mong for the same reasons presented with respect to claims 4-5 above.
Claims 6-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Dugast in view of Lautenschlaeger and Mong as applied to claims 5 and 14 above, and further in view of Musleh et al. (U.S. Pub. No. 2021/0092069), hereinafter Musleh, and Tran et al. (U.S. Pub. No. 2021/0209458), hereinafter Tran.
Regarding claim 6, the combination of Dugast in view of Lautenschlaeger and Mong teaches The computing system of claim 5, but fails to expressly teach wherein the network manager includes an analog compute module configured to perform at least a portion of inference computations in an analog form.
However, Musleh teaches wherein the network manager includes [a] compute module configured to perform at least a portion of inference computations ([0208] – “Applications 1806 can include machine learning features that are trained or make an inference according to a DL, ML, or AI framework 1806A. […] Framework 1806A can determine inter-layer data dependencies (e.g., producer-consumer relationships) and layer execution schedule and determine an approximate compute time in each layer.”; [0214] – “applications 1806 can provide indications or hints of priority level of data that is to be transmitted by NIC 1820”; [0221] – “NIC 1820 can support transmission and receipt of multiple traffic priority classes (e.g. virtual channels (VCs)). A driver (not shown) for NIC 1820 or OS 1808 can expose availability of NIC 1820 to support multiple priority levels. Applications 1806 can decide how to prioritize the different messages.”; [0242]-[0245] – “a machine learning application, communication interface, and/or NIC can determine one or more of: layer order, computation time for each layer, and amount of data to be sent for each layer. […] At 2506, a machine learning application can determine a priority level of data made available by a layer. For example, priority of a message sent by a layer can be based on one or more of: layer order, computation time for each layer, amount of data to be sent for each layer, and network congestion or expected time a message is inflight between a sender node and receiver node. […] At 2508, a priority of a packet that carries a message of the neural network based on the priority level can be set. For example, an application can specify a priority level of a message and a NIC can insert the priority level into a header of a packet that conveys the message and/or assign a particular virtual channel or traffic class to the packet.”).
Musleh is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of allocating virtual channels to meet timing requirements of a plurality of computing tasks. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the network manager which allocates virtual channels as taught by Dugast in view of Lautenschlaeger and Mong to incorporate the teachings of Musleh. Doing so would improve prioritization of network traffic to achieve better overall network utilization and to reduce latency of availability of data (see Musleh: [0205] and [0213]).
The combination of Dugast in view of Lautenschlaeger, Mong, and Tran fails to expressly teach the compute module is an analog compute module configured to perform the portion of inference computations in an analog form.
However, Tran teaches an analog compute module configured to perform at least a portion of inference computations in an analog form ([0003] – “Artificial neural networks mimic biological neural
networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown.”; [0006] – “an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses […] The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. […] Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.”; [0124]-[0125] – “VMM array 1200 comprises a memory array 1203 of non-volatile memory cells […] By performing the multiplication and addition function, memory array 1203 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WL1 , WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation.”).
Tran is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of accelerating inference operations, e.g. those performed by the network manager in virtual channel allocation. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the network manager configured to perform at least a portion of inference computations (e.g. a trained machine learning algorithm such as neural network) as taught by Dugast in view of Lautenschlaeger, Mong, and Musleh to include an analog compute module configured to perform at least a portion of the inference computations in an analog form as taught by Tran. Using such an analog compute module to implement a portion of inference computations, e.g., to perform the multiplication and addition functions, negates the need for separate multiplication and addition logic circuits and improves power efficiency (see Tran: [0125]).
Regarding claim 7, the combination of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran teaches The computing system of claim 6. Tran further teaches wherein the analog compute module includes a non-volatile memory cell array having memory cells programmed in a first mode according to weight matrices of an artificial neural network trained to perform at least the portion of the inference computations ([0006] – “an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses […] The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. […] Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.”; [0092] – “any other appropriate application could be implemented using a non-volatile memory array based neural network”; [0124]-[0125] – “VMM array 1200 comprises a memory array 1203 of non-volatile memory cells […] Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200 on respective memory cells thereof. Second, memory array 1203 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into the input voltages to supply to wordlines WL0, WL1 , WL2, and WL3) by the weights stored in the memory array 1203 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array 1203 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WL1 , WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.”; [0079] and Table 1 – shows different modes (e.g., read 1, read 2, erase, program) in which the memory cells can be in based on voltage ranges applied to its terminals for read, erase and program operations; [0126] and Table 5 – shows specific operating voltages for the read, erase and program modes of VMM array 1200. In the read (inference) mode, the VMM array has been programmed to store weights and perform multiplication and addition operations for the neural network using them).
It would have been obvious to one of ordinary skill in the art to have modified the network manager configured to perform at least a portion of inference computations (e.g. a trained machine learning algorithm such as neural network) as taught by Dugast in view of Lautenschlaeger, Mong, and Musleh to include the analog compute module taught by Tran. Using such an analog compute module to implement a portion of inference computations, e.g., to perform the multiplication and addition functions, negates the need for separate multiplication and addition logic circuits and improves power efficiency (see Tran: [0125]).
Regarding claim 8, the combination of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran teaches The computing system of claim 7. Musleh further teaches wherein the artificial neural network is trained (applications 1806; [0208] – “Applications 1806 can include machine learning features that are trained or make an inference according to a DL, ML, or AI framework 1806A.”; [0191]-[0192] – “An exemplary type of machine learning algorithm is a neural network.”) to predict an aspect of the timing data based on which the second virtual channel is allocated ([0208] – “Framework 1806A can determine inter-layer data dependencies (e.g., producer-consumer relationships) and layer execution schedule and determine an approximate compute time in each layer.”; [0215]-[0216] – “applications 1806 can assign a weight based on specific system and application conditions to determine a priority, where specific system and application conditions can include one or more of: […] or compute/communication-ratio-based prioritization (e.g., time spent to process data over time that data is expected to traverse a network to a next node). Applications 1806 can specify a priority level of a message using a Flow Label for inclusion in a packet as an indicator of Deadline-Awareness of certain application flows. […] a virtual channel identifier (ID) field of a packet header can also be used to convey packet priority if there is QoS mapping of virtual channel ID to a priority level. Virtual channels (VCs) can be allocated for the highest deemed priority messages. Utilizing different VCs to achieve Quality-of-Service (QoS) levels can be used.”; [0231] – “NIC 1820 can assign messages to a higher priority VC if the Flow Label indicates a packet is higher priority”; [0239] – “Compute time can be an amount of time a compute at a layer is expected to take to complete and can incorporate communication time of a message to be processed by the layer from an earlier layer or the same layer number. Communication time of a message can depend on message size, node traversal, number of switches, network congestion, and so forth.”; [0242] – “a software framework (e.g., ML application) can assign the weight of prioritization level of each factor. […] Message priority from a layer can be assigned based on weighing various prioritization schemes to derive a combined priority. In some examples, equal weights are applied to a prioritization level of each factor whereas in some examples, different weightings are applied to a prioritization level of each factor. An administrator or machine learning algorithm can be used to determine which weights provide the least time amount of processing stalls due to unavailability of data (e.g., data from a prior layer not being available for processing by a current layer).”; [0244]-[0245] – “FIG. 25A depicts an example process. The process can be performed at a computing node to prioritize data transmission in connection with execution of a neural network on multiple nodes using data parallelism or model parallelism. At 2502, a layer order, computation time for each layer, and amount of data to be sent for one or more layers of a neural network can be determined. For example, a machine learning application, communication interface, and/or NIC can determine one or more of: layer order, computation time for each layer, and amount of data to be sent for each layer. […] At 2506, a machine learning application can determine a priority level of data made available by a layer. For example, priority of a message sent by a layer can be based on one or more of: layer order, computation time for each layer, amount of data to be sent for each layer, and network congestion or expected time a message is inflight between a sender node and receiver node. […] At 2508, a priority of a packet that carries a message of the neural network based on the priority level can be set. For example, an application can specify a priority level of a message and a NIC can insert the priority level into a header of a packet that conveys the message and/or assign a particular virtual channel or traffic class to the packet.”).
It would have been obvious to one of ordinary skill in the art to have modified the network manager which allocates virtual channels as taught by Dugast in view of Lautenschlaeger and Mong to incorporate the teachings of Musleh. Doing so would improve prioritization of network traffic to achieve better overall network utilization and to reduce latency of availability of data (see Musleh: [0205] and [0213]).
Claim 15 recites substantially the same additional limitations recited in claims 6-7, applied to the method of claim 14. Accordingly, claim 15 is rejected as being unpatentable over Dugast in view of Lautenschlaeger and Mong, and further in view of Musleh and Tran for the same reasons presented with respect to claims 6-7 above.
Claim 16 recites substantially the same additional limitations recited in claim 8, applied to the method of claim 15. Accordingly, claim 16 is rejected as being unpatentable over Dugast in view of Lautenschlaeger, Mong, Musleh and Tran for the same reasons presented with respect to claim 8 above.
Claims 9-11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dugast in view of Lautenschlaeger, Mong, Musleh and Tran as applied to claims 8 and 16 above, and further in view of Hayashi et al. (U.S. Patent No. 5,768,184), hereinafter Hayashi.
Regarding claim 9, the combination of the combination of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran teaches The computing system of claim 8. Tran further teaches wherein each respective memory cell programmed in the first mode in the non-volatile memory cell array is configured to output: a […] amount of current in response to a predetermined read voltage when the respective memory cell has [a number of electrons on the floating gate] programmed to represent a value of one; or a negligible amount of current in response to the predetermined read voltage when [number of electrons on the floating gate] is programmed to represent a value of zero ([0078] – “Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal). If the floating gate 20 is positively charged (i.e. erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or "1" state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or "0" state.”; [0079] – “Table No. 1 depicts typical voltage ranges that can be applied to the terminals of memory cell 110 for performing read, erase, and program operations: […]"Read 1 " is a read mode in which the cell current is output on the bit line.”; [0109] – “Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell […] Io is the memory cell current at gate voltage equal to threshold voltage”; [0117] – “the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region: […] meaning weight W in the linear region is proportional to (Vgs-Vth)”; [0186] – “a "0" value for w (zero w or not used cells) can be defined as <10 nA or another pre-determined threshold”); wherein each respective memory cell is programmable in a second mode in the nonvolatile memory cell array to have […] one of a plurality of predetermined values ([0006] – “Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate.”; [0007] – “Each non-volatile memory cell used in the VMM array must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell.”; [0075] – “Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14.”; [0077] – “Memory cell 210 is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14.”; [0089] – “the memory state (i.e. charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance of other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance of other memory cells. This means the cell storage is analog or at the very least can store one of many discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all the cells in the memory array”; [0117] – “weight W in the linear region is proportional to (Vgs-Vth)”).
It would have been obvious to one of ordinary skill in the art to have modified the network manager configured to perform at least a portion of inference computations (e.g. a trained machine learning algorithm such as neural network) as taught by Dugast in view of Lautenschlaeger, Mong, and Musleh to include the analog compute module taught by Tran. Using such an analog compute module comprising a non-volatile memory cell array to implement a portion of inference computations, e.g., to perform the multiplication and addition functions, negates the need for separate multiplication and addition logic circuits and improves power efficiency (see Tran: [0125]).
The combination of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran does not explicitly teach a predetermined amount of current output when the respective memory cell has a threshold voltage programmed to represent a value of one; or the threshold voltage programmed to represent a value of zero; and that each non-volatile memory cell may be programmed to have a threshold voltage positioned in one of a plurality of voltage regions, each representative of one of the predetermined values.
However, Hayashi teaches a predetermined amount of current output when the respective memory cell has a threshold voltage programmed to represent a value of one (Col. 1, line 52-Col. 2, line 3 – “V.sub.th1 indicates a change of the threshold voltage of the memory cell in which the "1" data (on at the time of reading) is stored. […] a current i.sub.r1 which is read out from the memory cell in which the "1" data is stored remains substantially constant without regard as to the elapse of time […] as the reference cell for preparing the reference data, conventionally a transistor which becomes ON at the time of reading ("1" data is stored) is used and set up so that the reference current i.sub.rp at the time of the reading is in a constant proportion relative to i.sub.r1”); or the threshold voltage programmed to represent a value of zero Col. 1, lines 43-44 – “a threshold voltage V.sub.th0 of a memory cell in which the "0" data (off at the time of reading) is stored”); and that each non-volatile memory cell may be programmed to have a threshold voltage positioned in one of a plurality of voltage regions, each representative of one of the predetermined values (Col. 5, lines 24-59 – “the non-volatile semiconductor memory device of the present embodiment is a NOR-type memory and the multi-level memory cells 2 are arranged in the form of a matrix. Each multi-level memory cell 2 is constituted by a transistor having a floating gate […] electrons are injected into or removed from the floating gate 10 by utilizing the FN (Fowler Nordheim) effect or the like, whereby the threshold voltage of the transistor is changed, and the writing and erasing of at least three-level data, for example, four-level data of V (0,0), V (0,1), V (1,0), and V (1,1) can be carried out. In the case of a memory cell which can store four levels of V (0,0), V (0,1), V (1,0), and V (1,1), the distribution of the threshold voltages of the level 0 to level 3 is, as shown in FIG. 2, a level 3 (1, 1) of 1.5 V to 3 V, a level 2 (1, 0) of 3.7 V to 4 V, a level 1 (0, 1) of 4.6 V to 4.9 V, and a level 0 (0, 0) of 5.6 V to 5.9 V. […] To write the four levels, for example, first erasure is performed to shift the threshold voltage to the level "0" or more, then electrons are injected into the floating gate while applying a write bias voltage, and a verification operation comprised of repeatedly suspending the write operation and reading the written state is performed. This ends at the point when the above-mentioned desired threshold voltage is obtained.”; Col. 2, lines 30-35 – “In reading data from this multi-level memory cell in which data is stored over four levels. conventionally. The threshold voltage of the cell to be read out and the level 1 to level 3 are compared to determine the value of the data. Namely. the decision of the data is carried out by a comparison at the voltage levels.”).
Hayashi is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of using a non-volatile memory cell array to accelerate inference operations. Tran teaches programming each memory cell to store one of a plurality of predetermined values, e.g., weight values of a neural network, by injecting and removing electrons on the floating gate of each memory cell to correspond to different memory states (see Tran: [0006]-[0007], [0076]-[0078], and [0089]). Hayashi teaches this process of injecting and removing electrons on the floating gate of each non-volatile memory cell is the same as setting the threshold voltage of the respective memory cell as is known in the art (see Hayashi: Col. 5, lines 24-59). Thus, one of ordinary skill in the art would recognize the above-cited teachings of Tran as teaching “each respective memory cell programmed in the first mode in the non-volatile memory cell array is configured to output: [an] amount of current in response to a predetermined read voltage when the respective memory cell has a threshold voltage programmed to represent a value of one; or a negligible amount of current in response to the predetermined read voltage when the threshold voltage is programmed to represent a value of zero wherein each respective memory cell is programmable in a second mode in the nonvolatile memory cell array to have a threshold voltage positioned in one of a plurality of voltage regions, each representative of one of a plurality of predetermined values” as recited in the claims since injecting and removing electrons from the floating gate of a memory cell until the number of electrons on the floating gate correspond to one of a plurality of values/memory states is programming the threshold voltage of the memory cells to correspond to the different values as evidenced by Hayashi. Further, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran to incorporate the teachings of Hayashi. Doing so would improve the data retention, number of rewrites and manufacturing yield of the non-volatile memory cells which store multiple different values (see Hayashi: Col. 2, lines 47-51).
Regarding claim 10, the combination of Dugast in view of Lautenschlaeger, Mong, Musleh, Tran, and Hayashi teaches The computing system of claim 9. Tran further teaches wherein the analog compute module further comprises: voltage drivers (DAC converter 31, e.g., of input circuit 3306; [0165]); and current digitizers (ADC, e.g., of output circuit 3307; [0166]); wherein the non-volatile memory cell array includes wordlines and bitlines (FIG. 12, wordlines WL0, WL1, WL2, WL3, and bitlines BL0-BLN); wherein the analog compute module is configured to instruct the voltage drivers to apply voltages to the wordlines according to input bits to cause output currents through memory cells, programmed in the first mode to store a weight matrix, to be summed in the bitlines in an analog form ([0097] – “VMM array 33 comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33. Input to VMM array 33 can be from the erase gate and wordline gate decoder 34”; [0101] – “The input to VMM system 32 in FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level”; [0102] – “the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31, and provided to input VMM system 32a. The converted analog inputs could be voltage or current. The input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM system 32a.”; [0165] – “Input circuit 3306 may include circuits such as a DAC (digital to analog converter)”; [0185] – “Wordlines are used instead of control gate lines to receive the row data inputs (activation values), such as through pulse width modulated inputs or analog voltages applied to the wordlines”; [0125] – “Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200 on respective memory cells thereof. Second, memory array 1203 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLRl, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array 1203 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WLl , WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.”); and wherein the current digitizers are configured to convert currents in the bitlines […], representative of digital results of multiplication and accumulation applied to the input bits and the weight matrix ([0098] – “VMM array 33 effectively multiplies the inputs by the weights stored in VMM array 33 and adds them up per output line (source line or bit line) to produce the output”; [0101] – “the output can be analog level, binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).”; [0125] – “Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200 on respective memory cells thereof. Second, memory array 1203 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLRl, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into the input voltages to supply to wordlines WL0, WLl, WL2, and WL3) by the weights stored in the memory array 1203 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array 1203 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WLl , WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.”; [0166] – “Output circuit 3307 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits)”).
It would have been obvious to one of ordinary skill in the art to have modified the network manager configured to perform at least a portion of inference computations (e.g. a trained machine learning algorithm such as neural network) as taught by Dugast in view of Lautenschlaeger, Mong, and Musleh to include the analog compute module taught by Tran. Using such an analog compute module comprising a non-volatile memory cell array to implement a portion of inference computations, e.g., to perform the multiplication and addition functions, negates the need for separate multiplication and addition logic circuits and improves power efficiency (see Tran: [0125]).
Tran does not, however, Hayashi further teaches currents in the bitlines as multiple of the predetermined amount of current (Col. 2, lines 61-65 – “a decision circuit which decides the value stored in the non-volatile memory cell by comparing a current, or k-multiple current of the same, of the non-volatile memory cell and the output current of the reference current generation circuit.”; Col. 8, lines 9-16 – “By comparing the magnitudes of the read currents i.sub.data(0,0), i.sub.data(0,1), i.sub.data(1,0), and i.sub.data(1,1), or k-multiples of the same, of the selected multi-level memory cell to be input to the second input terminal 32b and the reference currents i.sub.re (i.sub.re(0,0), i.sub.re(1,0), and i.sub.re(1,1)) or k-multiples of the same, it can be decided that which among the data V (0, 0), V (0, 1), V (1, 0), and V (1, 1) is stored in the multi-level memory cell 2”; Col. 6, lines 60-67 – “a reference current generation circuit 30 which performs simple addition or weighted addition (summation) by selecting two current values detected from the bit line 22 and generates an intermediate value, or k-multiple of the same”).
It would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger, Mong, Musleh, and Tran to incorporate the teachings of Hayashi. Doing so would improve the data retention, number of rewrites and manufacturing yield of the non-volatile memory cells which store multiple different values (see Hayashi: Col. 2, lines 47-51).
Regarding claim 11, the combination of Dugast in view of Lautenschlaeger, Mong, Musleh, Tran, and Hayashi teaches The computing system of claim 10. Tran further teaches wherein the analog compute module further includes a logic circuit configured to cause a voltage driver to apply, to a respective wordline: the predetermined read voltage, when an input bit provided for the respective wordline is one ([0101] – “The input to VMM system 32 in FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to- analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level”; [0102] – “the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31, and provided to input VMM system 32a. The converted analog inputs could be voltage or current. The input DIA conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog
levels for the matrix multiplier of input VMM system 32a.”; [0126] – “Table No. 5 depicts operating voltages for VMM array 1200. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells […] The rows indicate the operations of read, erase, and program.”; [0126] – the predetermined voltage applied to a selected wordline (i.e., the “input bit provided for the respective wordline is one”) for a read operation is 0.5-3.5 V); or a voltage lower than the predetermined read voltage to cause memory cells on the respective wordline to output negligible amount of currents to the bitlines, when the input bit provided for the respective wordline is zero ([0125] – “results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN) […] the voltage inputs are provided on the word lines WL0, WLl , WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation”; [0126] – the predetermined voltage applied to an unselected wordline (i.e., the “input bit provided for the respective wordline is zero”) for a read operation is -0.5 V/0 V which is less than the predetermined read voltage applied to the wordline for selected cells; [0168] – “a programming operation (such as by deep programming or by coarse/fine programming to a target) is performed on all unused cells (step 3404) such as to get to <pA current level or to an equivalent zero weight”).
It would have been obvious to one of ordinary skill in the art to have modified the network manager configured to perform at least a portion of inference computations (e.g. a trained machine learning algorithm such as neural network) as taught by Dugast in view of Lautenschlaeger, Mong, and Musleh to include the analog compute module taught by Tran. Using such an analog compute module comprising a non-volatile memory cell array to implement a portion of inference computations, e.g., to perform the multiplication and addition functions, negates the need for separate multiplication and addition logic circuits and improves power efficiency (see Tran: [0125]).
Claim 17 recites substantially the same additional limitations recited in claim 9, applied to the method of claim 16. Accordingly, claim 17 is rejected as being unpatentable over Dugast in view of Lautenschlaeger, Mong, Musleh and Tran, and further in view of Hayashi for the same reasons presented with respect to claim 9 above.
Claim 18 recites substantially the same additional limitations recited in claims 10-11, applied to the method of claim 17. Accordingly, claim 18 is rejected as being unpatentable over Dugast in view of Lautenschlaeger, Mong, Musleh, Tran, and Hayashi for the same reasons presented with respect to claims 10-11 above.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dugast in view of Lautenschlaeger and Mong.
Regarding claim 19, Dugast teaches A non-transitory computer storage medium storing instructions which, when executed in a computing system ([0080] – “The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (e.g., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system.”), cause the computing system to perform a method, the method comprising:
[a time-sensitive network] having a network of physical connections configured (TSN network 104 and NICs 112 and 128 comprising TSN circuitry 116 and 124; [0027] – “When a memory request references memory that is part of a memory pool 106, the memory controller 110 forward the request to a NIC 112, which sends the request via TSN network 104, to a NIC 118 of the corresponding memory pool 106. The NIC 118 may then pass the request to memory controller 122 to access the memory 120.”; [0028] – “Various components along the path from the memory controller 110 to the memory 120 of the memory pool may include circuitry enabling TSN. For example, NIC 112 includes TSN circuitry 116, components (e.g., switches) of TSN network 104 may include TSN circuitry, NIC 118 includes TSN circuitry 124, and memory controller 122 includes TSN circuitry 126.”; [0029] – “NIC 112 may be used for the communication of signaling and/or data between platform 102, one or more networks (e.g., TSN network 104), and/or one or more devices or systems coupled to one or more networks ( e.g., memory pools 106). […] A TSN network utilizing Ethernet communications […] A NIC may include one or more physical ports that may couple to a cable (e.g., an Ethernet cable). In various embodiments a NIC may be integrated with a chipset of a platform (e.g., may be on the same integrated circuit or circuit board as a processor of the platform) or may be on a different integrated circuit or circuit board that is electromechanically coupled to the chipset.”; [0034] – “a given physical network”; [0041] – “The TSN network 104 couples platforms 102 to memory pools 106 via a series of TSN switches 202. In the embodiment depicted, a TSN switch 202 comprises switching fabric 204, queues 206, gates 208, traffic class table 210, gate control list 212, and TSN controller 214. Any suitable TSN component in system 100 may comprise any one or more of the components of TSN switch 202, where a TSN component may include, for example, a TSN switch 202, other component of the TSN network 104, or TSN circuitry of a component of a platform 102 or memory pool 106 (e.g., TSN circuitry 116, 124, 126).” [0048] – “By utilizing the TSN network 104 and the various TSN circuitry in a platform 102 and a memory pool 106, the traffic associated with memory pooling may share the TSN network 104”) between a plurality of components configured to perform computing tasks (Fig. 1, platforms 102, each containing processor(s) 306, executing applications 108; [0008] – “System 100 includes platforms 102 (e.g., 102A, B, and C)”; [0104] – “a platform 102 (e.g., 102A-C) may execute an application 108 (e.g., 108A-C)”; [0015] – “Application 108 may be executed by logic (e.g., a processor) of a platform 102”; [0054] – “platform 102 comprises […] a processor 306”; [0062] – “Processor 306 may comprise any suitable process, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, an SOC, or other device to execute code (e.g., software instructions). Processor 306, in the depicted embodiment, includes two processing elements (cores 308A and 308B in the depicted embodiment)”) and a plurality of memory devices configured to provide memory and storage services over the [network] (FIG. 1, memory pools 106 comprising memory 120; [0008] – “memory pools 106 (e.g., 106A, . . . 106N)”; [0016] – “Execution of the application 108 may include executing various memory flows 114, where a memory flow may comprise any number of reads from or writes to memory. The memory may be local to the platform or remote from the platform (e.g., within memory 120 of a memory pool 106).”; [0026] – “write requests from an application 108 and may provide data specified in these requests to a memory for storage therein”; [0035] – “A memory 120 may store any suitable data, such as data used by one or more applications 108 to provide the functionality of a platform 102.”; [0039] – “Memory 120 may comprise any suitable types of memory and are not limited to a particular speed, technology, or form factor of memory in various embodiments. For example, memory 120 may comprise one or more disk drives (such as solid-state drives), memory cards, memory modules (e.g., dual in-line memory modules) that may be inserted in a memory socket, or other types of memory devices.”), timing data of the computing tasks, wherein the timing data is configured to identify: urgency levels of the computing tasks ([0010] – “A key requirement for various applications is the execution of certain flows that require predictable and deterministic latencies.”; [0014] – “an application 108 (e.g., 108A-C) that includes various memory flows 114 (e.g., 308A-C).”; [0017] – “a memory flow may be a flow with guaranteed latency, where the latency may include, e.g., an elapsed amount of time between a request for memory contents and retrieval of the memory contents for access by the requester (e.g., application executing the memory flow). In various embodiments, the latency that is guaranteed may be for any suitable portion of the request path. For example, the latency may be guaranteed for the amount of time from when a request is received at a memory controller 110 up to the time the data is received back at the memory controller 110. […] As one more example, a memory flow may be a lower priority memory flow and may rely on best efforts to retrieve the memory (and thus may have neither a guaranteed bandwidth nor latency).”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic. These memory-specific properties may be passed to the operating system of the platform 102 […] The operating system may use these properties to match memory locations (e.g., memory pools) with requirements of the various memory flows of the platform 102”; [0024] – “When a memory controller receives a request specifying a virtual address in the address space 128, the memory controller may process the request based on the specific address space that contains the virtual address. For example, the memory controller may tag the request with a priority identifier that may be used by the components along the path to the destination memory pool 106 to ensure that any bandwidth or latency guarantees are honored during fulfillment of the request.”; [0042] – “each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency.”); and
allocating, by the network manager, virtual channels in the [network] for the computing tasks to access the memory and storage services ([0013] – “Thus, in some embodiments, an end-to-end channel is setup between the host (e.g., a platform 102) and the memory controller ( e.g., 122) of a memory pool (e.g., 106) that guarantees a fixed latency for requests referencing an address within a particular memory address range.” [0033] – “memory controller 122 includes one or more request queues that are dedicated for traffic sent via a TSN channel (e.g., traffic sent by platforms 102 over the TSN network 104 that has a guaranteed latency). Utilizing these requests queues, the memory controller 122 may guarantee a fixed latency for such request queues”; [0034] – “Another TSN feature offered by TSN endpoints (e.g., memory pool 106) compliant with IEEE 802.1 Qbv (Enhancements for Scheduled Traffic) is queuing disciplines which controls hardware queuing mechanism support. This permits allocation of one hardware queue for memory pooling traffic, to reduce interference with other traffic classes. An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0060] – “NIC 112 includes a plurality of hardware queues 314 to store incoming or outgoing packets (or packet identifiers). In some embodiments, one or more of the hardware queues 314 may be dedicated for memory pooling traffic (e.g., to reduce interference to or by other traffic classes). In some embodiments, a hardware queue 314 may be reserved for a particular class of traffic (e.g., for guaranteed latency traffic).”) including identifying, for each of the virtual channels, a set of rules for communications over the [network] ([0011] – “TSN achieves determinism over the network (e.g., an Ethernet network) by leveraging time synchronization and a schedule that is shared between network components. In embodiments, the architecture defines queues based on time, thereby guaranteeing a bounded maximum latency for scheduled traffic”; [0019] – “As the memories 120 of the memory pools 106 are accessed over NICs 112, 118 and network 104 with TSN capabilities, the bandwidth, latency, and jitter for requests for contents of these memories are deterministic.”; [0034] – “An IEEE 802.1 Qbv time-aware scheduler may separate communication on an Ethernet network into fixed length, repeating time cycles. This is used to create virtual channels on a given physical network. By scheduling a slice of time for traffic related to memory pooling traffic (e.g., latency guaranteed traffic) only and leaving the rest of the time credit for all other traffic, it is possible to prioritize memory pooling traffic (using time-division multiple access). With traffic shaping, each slice of time is bound to one or multiple hardware queues which are in turn mapped to virtual channels used on the host by memory pooling.”; [0042] – “A TSN path (e.g., through one or more components of platform 102, through network 104, and through one or more components of memory pool 106) may exhibit various characteristics, such as low and deterministic transmission latency (at least for particular network traffic) and synchronized clocks. Streams passing through the TSN path may be given latency and/or bandwidth guarantees. Scheduling and traffic shaping capabilities of the TSN components enable different traffic classes with different priorities on the TSN path, where each priority (e.g., where priorities may be identified by a priority identifier of a packet) may have different requirements for bandwidth and end-to-end latency. In various embodiments, transmission times with guaranteed end-to-end latency may be achieved using one or more priority classes”; [0046]-[0048] – “the gate control list 212 may be coordinated among the components of the TSN path so that traffic of the same priority may be communicated through the TSN path during the time dedicated to that priority. This may ensure a guaranteed maximum latency (and/or a guaranteed bandwidth) for sending frames. In various embodiments, communication over the TSN path may utilize a time-division multiple access scheme in which communication over the TSN path is split into repeating time cycles with fixed lengths. Within a cycle, different time slices may be assigned to one or more priorities. This allows exclusive use of a transmission medium for a period of time for a traffic class that needs a transmission guarantee.”).
Dugast fails to expressly teach receiving, in the network manager the timing data and fails to teach the time sensitive network is a networking bus.
However, Lautenschlaeger teaches the time-sensitive network having a network of physical connections is a networking bus, where virtual channels are through the bus ([0038] – “Networked devices may communicate across a network using an Ethernet protocol stack. Ethernet advantageously allows efficient use of network bandwidth through packet switching, supports multicast and broadcast traffic, and the network infrastructure is already widely deployed and commonly supported by devices and so is readily available for networking of devices. In particular, packet switching in Ethernet permits link infrastructure to have a ‘backbone’/′bus' configuration, whereby different data channels may be served by common infrastructure, i.e., network cabling/switches. This may advantageously minimise the physical infrastructure required to network devices.”; [0043]-[0044] – “an aspect of the present disclosure implements a time-sensitive network (TSN) over a TDM backbone architecture utilised with a TDM shim layer inserted into the Ethernet protocol stack between the PHY and the MAC layers […] Aspects of the proposal may thus advantageously provide an efficient means for transporting both TSN/CBR traffic and conventional packet-switched traffic via shared Ethernet physical layer infrastructure.”; [0048] – “Ethernet bus 112 comprises a backbone medium 113 […] Ethernet bus 112 operates as an enhanced Ethernet physical layer network whereby TSN traffic between the machine-machine controller pairs 103-106, 104-107, and 105-108, and conventional packet-switched traffic between the IT devices 109 to 111 and IT server 102, is communicated concurrently.”; [0087] – “the TDM multiplexor may identify time slots reserved for transmission of TNS data via the Ethernet bus.”).
Dugast and Lautenschlaeger are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art that the “network of physical connections configured between the components and the memory devices” through which virtual channels are allocated, (specifically the Ethernet based TSN network) taught by Dugast may form a networking bus, e.g. an Ethernet bus, as taught by Lautenschlaeger. Lautenschlaeger teaches the network infrastructure for Ethernet is already widely supported, and that an Ethernet network having a backbone/bus configuration in which different data channels are served by common physical infrastructure provides the benefit of minimizing the physical infrastructure required to network between communicating devices (see Lautenschlaeger: [0038]).
The combination of Dugast in view of Lautenschlaeger receiving, in the network manager the timing data.
However, Mong teaches receiving, in the network manager the timing data ([0107] – “The systems and methods described herein address how TSN should interpret and react to the QoS requirements of the data distribution service. By mapping configuration parameters of the data distribution service to the configuration parameters of TSN, a scheduler of TSN can create schedules that support QoS requirements of the data distribution service for time-critical control applications.”; [0116] – “the network through which data is communicated and the applications communicating the data (e.g., the devices 802, 804, 808, 814, 818).”; [0123] – “The QoS parameters 828 of the devices 802, 804, 808, 814, 818 may be defined by one or more, or a combination, of the deadline parameter, latency parameter, and/or transport priority parameter. The QoS parameters 828 are then used to determine data traffic schedules within the TSN using the data distribution service 824. Data traffic schedules can dictate communication paths and times at which data is communicated within the network.”; [0128] – “The method 1000 may be used by the control system 818 to determine schedules for communicating data within the network 900 to satisfy the QoS parameters 828 of various devices 802, 804, 808, 814, 818.”; [0129] – “QoS parameters 828 for the devices 802, 804, 808, 814, 818 are determined. These parameters may be input by an operator or user of the powered system or control system 818, or may be communicated to the control system 818 by the devices 802, 804, 808, 814, 818.”; [0150] – “the scheduler 1118 and the traffic shaper 1120 communicate with each other to determine what communication schedules are feasible to achieve the QoS parameter(s) 828 received from the control system 818.”).
Mong is considered to be analogous art to the claimed invention because it is reasonably pertinent to the problem faced by the inventor of satisfying timing requirements of applications using time-sensitive networking. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Dugast in view of Lautenschlaeger to incorporate the teachings of Mong. Doing so would enable dynamic configuration of the time sensitive network to meet QoS requirements of a plurality of time-critical applications (see Mong: [0023], [0107], [0151], and [0154]).
Claim 20 recites substantially the same additional limitations recited in claims 4-5, applied to the non-transitory computer storage medium of claim 20. Accordingly, claim 20 is rejected as being unpatentable over Dugast in view of Lautenschlaeger and Mong for the same reasons presented with respect to claims 4-5 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fan et al. (U.S. Patent No. 6,747,310), incorporated by reference into Tran, teaches charging the floating gate of a non-volatile memory cell changes the threshold voltage of the memory cell (see Col. 9, lines 10-21).
Balle et al. (U.S. Pub. No. 2019/0138481) teaches a method for providing dynamic communication path modification in which a communication abstraction logic unit determines a logical communication path between an accelerator device on an accelerator sled performing a workload and a storage or memory sled and preemptively allocates physical communication path capacity in preparation for a predicted increase in congestion in the physical communication paths, e.g. underlying buses and network connections, allocated to a logical communication path (see [0078]).
Subramanian et al. (U.S. Patent No. 10,853,308 B1) teaches a time-aware DMA circuit including a controller which performs time-aware DMA data transfers various portions of a time-sensitive networking system (e.g., between a processing unit and memory of a TSN talker) via one or more data channels of a data bus (see Col. 8, lines 20-34, and Col. 9, lines 3-16).
SANCHEZ-GARRIDO et al. (NPL Document: “Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers”) teaches a time-sensitive networking bus which can be used for multiprocessor systems in which bounded end-to-end latency can be guaranteed by TSN traffic shapers, which allows forwarding of TSN data flows during time slots specified in it gate control list schedule (see Abstract and page 2745).
Pagano et al. (U.S. Pub. No. 2008/0205158) teaches it is known in the art that each non-volatile memory cell in a memory array comprises a floating gate transistor, and storage of a logic state is performed by programming the corresponding threshold voltage through injection of a quantity of electrical charge in its floating-gate region (see [0003]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER MARIE GUTMAN whose telephone number is (703)756-1572. The examiner can normally be reached M-F: 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JENNIFER MARIE GUTMAN/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
Prosecution Insights