Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on January 9, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng et al (US 20220122971 A1) hereafter referred to as “Peng”.
Regarding claim 1, Peng discloses an integrated circuit device (100) comprising: an upper transistor (120) comprising an upper channel region (L5) on a substrate (paragraph 27, Fig. 2); a lower transistor (110) between the substrate and the upper transistor (paragraph 27), the lower transistor comprising a lower channel region (nanosheets 196, paragraph 51); and a power line (VSS, 132) extending longitudinally in a first horizontal direction (direction X, Fig. 2A), wherein at least one of the upper channel region or the lower channel region (196) extends longitudinally in a second horizontal direction (direction Y, Fig. 2A-D) that traverses the first horizontal direction (direction X), and the at least one of the upper channel region or the lower channel region overlaps the power line (132) in a thickness direction (direction Z, Fig. 2E, paragraph 45).
Regarding claim 2, Peng discloses the integrated circuit device of Claim 1, wherein the at least one of the upper channel region or the lower channel region is electrically connected to a source/drain region (154, 156) that overlaps the power line in the thickness direction (the drain vias implying the presence of source/drain regions, paragraph 42, Fig. 2E).
Regarding claim 3, Peng discloses the integrated circuit device of Claim 1, wherein the at least one of the upper channel region (L5) or the lower channel region (L3) comprises a central portion in the second horizontal direction that overlaps the power line (142, 132) in the thickness direction (Fig. 2A, 2E).
Regarding claim 9, Peng discloses the integrated circuit device of Claim 1, wherein both the upper channel region (L5) and the lower channel region (L3) overlap the power line (142, 132) in the thickness direction (Fig. 2E).
Regarding claim 10, Peng discloses the integrated circuit device of Claim 1, wherein the power line is a first power line (142), the integrated circuit device further comprises a second power line (144a) and a third power line (144b) that are spaced apart from each other in the second horizontal direction with the first power line therebetween (Fig. 2E), and the at least one of the upper channel region (L5) or the lower channel region (L3) comprises a portion (nanosheets, 196) that is spaced apart from the second and third power lines in the second horizontal direction by an equal distance (Fig. 2E, 3E, 4E).
Claims 11-12, 14-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hong et al. (US 20230037833 A1) hereafter referred to as “Hong”.
Regarding claim 11, Hong discloses an integrated circuit device (200B) comprising: a first transistor (201) comprising a first channel region on a substrate (205); and a pair of second transistors (202), respectively, comprising a pair of second channel regions that are spaced apart from each other in a first horizontal direction, wherein the first channel region overlaps the pair of second channel regions in a thickness direction (D3) (Fig. 2B).
Regarding claim 12, Hong discloses the integrated circuit device of Claim 11, wherein the first channel region (201) is between the substrate (205) and the pair of second channel regions (202) (Fig. 2B).
Regarding claim 14, Hong discloses the integrated circuit device of Claim 11, wherein the first channel region comprises (201): a first portion (212) that overlaps a first one (214) of the pair of second channel regions (202) in the thickness direction; a second portion (211) that overlaps a second one (213) of the pair of second channel regions in the thickness direction; and a third portion (215) that is between the first and second portions and is free of overlap with the pair of second channel regions in the thickness direction (Fig. 2B).
Regarding claim 15, Hong discloses the integrated circuit device of Claim 11, further comprising a power line (543) extending longitudinally in a second horizontal direction that traverses the first horizontal direction, wherein the first channel region (501) overlaps the power line in the thickness direction (Fig. 5B).
Regarding claim 16, Hong discloses the integrated circuit device of Claim 15, wherein the pair of second channel regions (502) are free of overlap with the power line (542) in the thickness direction (Fig. 5B).
Regarding claim 17, Hong discloses the integrated circuit device of Claim 11, wherein a width of the first channel region (310) in the first horizontal direction is wider than a combined width of the pair of second channel regions (320) in the first horizontal direction (Fig. 3B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (US 20220122971 A1) in view of Hong et al. (US 20230037833 A1) hereinafter referred to as “Hong”.
Regarding claim 4, Peng is discussed above. Peng does not disclose the integrated circuit device of Claim 1, wherein the lower channel region overlaps the power line in the thickness direction, and the upper channel region is free of overlap with the power line in the thickness direction
However, Hong discloses an integrated circuit, wherein the lower channel region overlaps the power line in the thickness direction, and the upper channel region is free of overlap with the power line in the thickness direction (Fig. 5B)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Hong such that the lower channel region overlaps the power line in the thickness direction, and the upper channel region is free of overlap with the power line in the thickness direction. Doing so would reduce parasitic capacitance and to ensure low-resistance electrical connection to the power source.
Regarding claim 5, Peng does not disclose the integrated circuit device of Claim 4, wherein a width of the lower channel region in the second horizontal direction is at least two times wider than a width of the upper channel region in the second horizontal direction.
However, Hong discloses a width of the lower channel region in the second horizontal direction is at least two times wider than a width of the upper channel region in the second horizontal direction. (Hong teaches the limitation, wherein Hong discloses narrow fins of the second channel set (620) in the top transistor which can replace the nanosheets in the upper transistor, and the widths of the source/drain regions of the upper transistor formed when the second channel set may be made smaller than the widths of the source/drain regions of the lower transistor form the first channel set (610), paragraph 87, Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Hong such that the width of the source/drain region in the upper transistor is smaller than the width of the source/drain region of the lower transistor. Doing so would reduce parasitic capacitance and resistance, improving AC performance and switching speeds.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (US 20220122971 A1) in view of Chu et al. (US 20230178619 A1) hereinafter referred to as “Chu”.
Regarding claim 6, Peng is discussed above. Peng does not disclose the integrated circuit device of Claim 1, wherein the upper transistor is a first upper transistor, and the upper channel region is a first upper channel region, the integrated circuit device further comprises a second upper transistor comprising a second upper channel region that is spaced apart from the first upper channel region in the second horizontal direction, and the lower channel region overlaps the first and second upper channel regions in the thickness direction.
However, Chu discloses the upper transistor is a first upper transistor (200b), and the upper channel region is a first upper channel region (224, left), the integrated circuit device (200) further comprises a second upper transistor comprising a second upper channel region (224, right) that is spaced apart from the first upper channel region in the second horizontal direction (Fig. 13B), and the lower channel region (208).
None of the above references disclose the lower channel region overlaps the first and second upper channel regions in the thickness direction. However, rearrangement of parts is within the routine skill level of one in the art. You can change rearrange the first and second upper channel regions in the thickness direction. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chu such that the lower channel region overlaps the first and second upper channel regions in the thickness direction. Doing so would optimize device density, performance, and manufacturing efficiency.
Regarding claim 7, Peng does not disclose the integrated circuit device of Claim 1, wherein the upper channel region overlaps the power line in the thickness direction, and the lower channel region is free of overlap with the power line in the thickness direction.
However, Chu discloses the integrated circuit, wherein the upper channel region (200b) overlaps the power line (242) in the thickness direction, and the lower channel region (200a) is free of overlap with the power line in the thickness direction (Fig. 13A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chu such that the power line overlaps with the upper channel region in the thickness direction but does not overlap the lower channel region. Doing so would manage electric fields and ensure proper device switching behavior.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (US 20220122971 A1) in view of Chu et al. (US 20230178619 A1) as applied to claim 7 above, in further view of Hong et al. (US 20230037833 A1) hereinafter referred to as “Hong”.
Regarding claim 8, Peng and Chu are discussed above. Neither Peng nor Chu discloses a width of the upper channel region in the second horizontal direction is at least two times wider than a width of the lower channel region in the second horizontal direction. However, Hong discloses that the width of the source/drain regions of the upper transistor may be made smaller than the width of the source/drain regions of the lower transistor (paragraph 87).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references in view of Hong such that the width of the upper channel region in the second direction is at least two times wider than the width of the lower channel region in the second direction. Doing so would optimize electrical performance and manufacturability, particularly in the context of backside power delivery networks.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20230037833 A1).
Regarding claim 13, Hong is discussed above. Hong further discloses the first channel region (201) is between the substrate (205) and the pair of second channel regions (202) (Fig. 2B). Swapping first channel region location for the second channel region locations would yield the same result. Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Hong such that the pair of second channel regions are between the substrate and the first channel region. Doing so would optimize electrostatic control and increase current density.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al (US 20230037833 A1) in view of Peng et al (US 20220122971 A1) hereinafter referred to as “Peng” and Chu et al. (US 20230178619 A1) hereinafter referred to as “Chu”.
Regarding claim 18, Hong is discussed above. Hong does not disclose the first channel region is electrically connected to a first source/drain region, the pair of second channel regions are electrically connected to second and third source/drain regions, respectively, and the first source/drain region overlaps the second and third source/drain regions in the thickness direction.
However, Peng discloses the first channel region (L3, Fig. 2E) is electrically connected to a first source/drain region (paragraph 42, Fig. 2E), second (123) and third (124) source/drain regions, respectively, and the first (113) source/drain region overlaps the second and third source/drain regions in the thickness direction (Fig. 1).
However, Peng does not disclose the pair of second channel regions.
On the other hand, Chu discloses a pair of second channel regions (224, Fig. 10B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chu such that there is a pair of second channel regions on the second region of the integrated circuit. Doing so would maximize drive current while maintaining a smaller footprint.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817