Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 10/23/2023 and IDS filed on 10/23/2023. Claims 1-20 are pending.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
4. Claims 11 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, 14, and 15 of U.S. Patent No. 11,763,058. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented application recited a layout correction method that include machine learning and optical proximity correction of a layout that correspond to the method of the current application – wherein it is apparent that the layout is for semiconductor manufacturing on a substrate (claim 19).
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 9 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recited “performing a first deep learning-based inference based on linear
regression on a plurality of tokens; and performing a second deep learning-based inference based on nonlinear regression on a result of the first deep learning-based inference”, however it is not apparent what the tokens represent. It is not apparent of the relationship between the tokens and the patterns of the layout.
As per claim 10 is rejected to for incorporating the above limitations into the claims by dependency.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claim(s) 1, 11-13, and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Pub. No. 2021/0334444 A1).
As per claim 1, Lee discloses:
A deep learning-based process proximity correction method comprising:
receiving a first layout associated with an After Cleaning Inspection (ACI), the first layout including a plurality of patterns associated with manufacturing a semiconductor device (See Figure 2, i.e. s110 & Para [0035], i.e. receive a first layout. For example, the first layout may be a target layout that an operator/technician/engineer wants to or intends to obtain in ACI);
generating a predictive model based on the plurality of patterns, through deep learning (See Figure 2, i.e. s120 & Para [0036], i.e. perform process proximity correction (PPC) on the first layout to generate a second layout. The process proximity correction may be made by performing a machine learning-based inference on features of patterns of the first layout, See Figure 6 & Para [0050]-[0061], i.e. the semiconductor process machine learning module 200 may perform the machine learning-based inference on the features, so as to generate an image of the ACI);
generating a layout associated with an After Development Inspection (ADI) by correcting the first layout (See Figure 6, i.e. S260 – adjust features & Para [0050]-[0061] –[prior art adjust layout, is considered as the generating as cited above, the layout is for development, therefore considered as ADI as cited above]); and
predicting ACI by using the layout of the ADI, through the predictive model (See Figure 6, i.e. S240 & Para [0050]-[0061] –[prior art second iteration, after adjust layout in s260, is feed into S240, therefore perform the predicting as cited above]).
As per claim 11, Lee discloses:
A deep learning-based process proximity correction method comprising:
receiving a first layout associated with an After Cleaning Inspection (ACI), the first layout including a plurality of patterns for manufacturing a semiconductor device (See Figure 2, i.e. s110 & Para [0035], i.e. receive a first layout. For example, the first layout may be a target layout that an operator/technician/engineer wants to or intends to obtain in ACI);
generating a second layout by performing deep learning (DL)-process proximity correction (PPC) based on the plurality of patterns of the first layout (See Figure 2, i.e. s120 & Para [0036], i.e. perform process proximity correction (PPC) on the first layout to generate a second layout. The process proximity correction may be made by performing a machine learning-based inference on features of patterns of the first layout); and
generating a third layout by performing optical proximity correction (OPC) on the second layout (See Figure 2, i.e. S130 & Para [0038], i.e. perform optical proximity correction (OPC) on the second layout to generate a third layout).
As per claim 12, Lee discloses all of the features of claim 11 discloses above wherein Lee also discloses wherein the generating of the second layout comprises: generating a predictive model based on the plurality of patterns, through deep learning; generating a layout associated with an After Development Inspection (ADI) by correcting the first layout; and predicting ACI by using the layout of the ADI, through the predictive model (See Figure 6 & Para [0050]-[0061], i.e. the semiconductor process machine learning module 200 may perform the machine learning-based inference on the features, so as to generate an image of the ACI).
As per claim 13, Lee discloses all of the features of claim 12 discloses above wherein Lee also discloses wherein the predicting of the ACI is performed based on critical dimension (CD) information of each of the plurality of patterns (See Para [0047], i.e. predict a critical dimension (CD)).
As per claim 16, Lee discloses all of the features of claim 11 discloses above wherein Lee also discloses correcting a plurality of patterns multiple times, such that, after correcting the plurality of patterns multiple times, among the plurality of patterns a position of at least one first pattern is fixed within an error range; and further correcting one or more second patterns having a position greater than or equal to the error range (See Figure 6 & Para [0050]-[0061], i.e. the semiconductor process machine learning module 200 may perform the machine learning-based inference on the features, so as to generate an image of the ACI –[prior art perform correction include multiple iteration (See Figure 6), until meet threshold, considered as the correcting as cited above]).
As per claim 17, Lee discloses all of the features of claim 16 discloses above wherein Lee also discloses wherein the error range is equal to or less than 0.1 nm (See Figure 6 & Para [0050]-[0061], i.e. the semiconductor process machine learning module 200 may perform the machine learning-based inference on the features, so as to generate an image of the ACI, See Figure 6, i.e. S240 & S250 –[prior art determine difference between target and adjusted layout, in order to determine error based on threshold, therefore teaching error range as cited above]).
As per claim 18, Lee discloses all of the features of claim 12 discloses above wherein Lee also discloses after the predicting of ACI through the predictive model: determining whether a difference between the predicted ACI and an ACI target is within an allowable range; in response the difference being outside the allowable range, proceeding to the generating of a layout of the ADI; and determining the layout of the ADI as the second layout and proceeding to the generating of the third layout, in response to the difference being within the allowable range (See Figure 6 & Para [0050]-[0061], i.e. the semiconductor process machine learning module 200 may perform the machine learning-based inference on the features, so as to generate an image of the ACI, See Figure 6, i.e. S240 & S250).
As per claim 19, Lee discloses:
A mask manufacturing method comprising:
receiving a first layout including a plurality of patterns associated with manufacturing a semiconductor device (See Figure 2, i.e. s110 & Para [0035], i.e. receive a first layout. For example, the first layout may be a target layout that an operator/technician/engineer wants to or intends to obtain in ACI);
generating a second layout by performing deep learning-based process proximity correction on the first layout (See Figure 2, i.e. s120 & Para [0036], i.e. perform process proximity correction (PPC) on the first layout to generate a second layout. The process proximity correction may be made by performing a machine learning-based inference on features of patterns of the first layout);
generating a third layout by performing optical proximity correction on the second layout (See Figure 2, i.e. S130 & Para [0038], i.e. perform optical proximity correction (OPC) on the second layout to generate a third layout);
transmitting the third layout as mask tape-out (MTO) design data (See Para [0040], i.e. semiconductor devices may be generated (or manufactured or fabricated) based on the third layout. For example, patterns of a photo resist may be generated on a target);
preparing mask data based on the MTO design data (See Para [0040], i.e. semiconductor devices may be generated (or manufactured or fabricated) based on the third layout. For example, patterns of a photo resist may be generated on a target); and
exposing a substrate associated with a mask based on the mask data (See Para [0040], i.e. semiconductor devices may be generated (or manufactured or fabricated) based on the third layout. For example, patterns of a photo resist may be generated on a target).
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim(s) 2-7, 9, 10, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. No. 2021/0334444 A1) in view of Yang et al. (U.S. Pub. No. 2024/0013033 A1).
As per claim 2, Lee discloses all of the features of claim 1 as discloses above.
Lee does not teach the limitations: wherein the generating of the predictive model based on the plurality of patterns through deep learning, comprises a tokenization operation of setting the plurality of patterns to a plurality of tokens, respectively.
However, Yang discloses: wherein the generating of the predictive model based on the plurality of patterns through deep learning, comprises a tokenization operation of setting the plurality of patterns to a plurality of tokens, respectively (See Para [0039]-[0059], See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Yang into the
teaching of Lee because it would allow engineer to perform large-scale mask
optimization tasks on circuit design (See Para [0026]).
As per claim 3, Lee and Yang discloses all of the features of claim 2 discloses above wherein Yang also discloses wherein a plurality of polygons in the first layout are set to the plurality of tokens, respectively (See Para [0039]-[0059], See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
As per claim 4, Lee and Yang discloses all of the features of claim 2 discloses above wherein Yang also discloses wherein each of the plurality of tokens independently has a two-dimensional or three-dimensional matrix form (See Para [0039]-[0059], i.e. equation 5 & 8, See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
As per claim 5, Lee discloses all of the features of claim 1 as discloses above.
Lee does not teach the limitations: wherein the predictive model comprises a transformer algorithm.
However, Yang discloses: wherein the predictive model comprises a transformer algorithm. (See Para [0031], i.e. Fourier Transform, See Para [0039]-[0059], See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Yang into the
teaching of Lee because it would allow engineer to perform large-scale mask
optimization tasks on circuit design (See Para [0026]).
As per claim 6, Lee and Yang discloses all of the features of claim 2 discloses above wherein Yang also discloses wherein the generating of the predictive model comprises setting an input order of the plurality of tokens with respect to the predictive model (See Para [0039]-[0059], i.e. equation 5 & 8, See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
As per claim 7, Lee and Yang discloses all of the features of claim 6 discloses above wherein Yang also discloses wherein, in the setting of the input order of the plurality of tokens, the input order is set according to arrangement positions of the plurality of tokens (See Para [0039]-[0059], i.e. equation 5 & 8, See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout, See Para [0142], i.e. position).
As per claim 9, Lee discloses all of the features of claim 1 as discloses above, wherein Lee also discloses wherein the generating of the predictive model comprises: performing a first deep learning-based inference based on linear regression; and performing a second deep learning-based inference based on nonlinear regression on a result of the first deep learning-based inference (See Figure 11 & Para [0075]-[0080]).
Lee does not teach the limitations: using plurality of tokens in the predictive model.
However, Yang discloses: using plurality of tokens in the predictive model. (See Para [0031], i.e. Fourier Transform, See Para [0039]-[0059], See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Yang into the
teaching of Lee because it would allow engineer to perform large-scale mask
optimization tasks on circuit design (See Para [0026]).
As per claim 10, Lee and Yang discloses all of the features of claim 9 discloses above wherein Yang also discloses wherein the performing of the first deep learning-based inference is based on information of one of the plurality of tokens (See Para [0031], i.e. Fourier Transform, See Para [0039]-[0059], See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
As per claim 20, Lee discloses all of the features of claim 19 as discloses above.
Lee does not teach the limitations: wherein the generating of the second layout comprises: converting each of the plurality of patterns independently into a two-dimensional or three-dimensional matrix; and inputting the two-dimensional or three-dimensional matrix into a transformer algorithm.
However, Yang discloses: wherein the generating of the second layout comprises: converting each of the plurality of patterns independently into a two-dimensional or three-dimensional matrix; and inputting the two-dimensional or three-dimensional matrix into a transformer algorithm. (See Para [0039]-[0059], i.e. equation 5 & 8, See Para [0044], i.e. Layout tokens are tiles of the overall high-definition image of the circuit layout).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Yang into the
teaching of Lee because it would allow engineer to perform large-scale mask
optimization tasks on circuit design (See Para [0026]).
Allowable Subject Matter
11. Claims 8, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 8 and/or 14 - wherein claim 15 depend on claim 14.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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