Detailed Action
This action is in response to the application filed on 07/31/2026. Claims 1-20 are
pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C 103 as being unpatentable over Williams et al (U.S Publication No. US 2011/0219376 A1), hereinafter referred to as Williams, in view of Volpe et al (U.S Patent No. US 10,666,775 B1), hereinafter referred to as Volpe, in further view of Agarwala et al. (U.S. Publication No. 2004/0102947 A1), hereinafter referred to as Agarwala.
With regards to Claim 1, Williams teaches:
An apparatus, comprising: ([0004])
a processor circuit configured to generate trace information in response to an activation of a trace operation; ([0065]; regarding, “The processing apparatus 1 also comprises at least one trace module 12 for generating trace data indicative of characteristics of the processing apparatus 1”);
and a trace circuit coupled to the processor circuit via a trace interface, ([0065]; regarding, “the trace module 12 of FIG. 1 is shown within the data processing apparatus 1”);
wherein the trace circuit is configured to:
receive the trace information from the processor circuit via the trace interface; ([0098]; regarding, “The trace circuitry 50 monitors information received from the trace target at a trace target port 58”);
generate a plurality of trace packets including a given trace packet that includes an ordered data structure that includes a plurality of data sections, ([0093]; Fig. 6);
Williams fails to explicitly disclose but Volpe teaches:
wherein an initial data section of the plurality of data sections includes a payload, (Fig. 4; Col. 12, lines 44-48);
and a final data section of the plurality of data sections includes a footer; (Fig. 4; Col. 16, lines 64-66).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Williams with the teachings of Volpe. Doing so can reduce CPU overhead (Volpe, Col. 17, lines 43-45).
Williams in view of Volpe fails to explicitly disclose but Agarwala teaches:
and encode program counter discontinuities associated with the given trace packet to generate a compressed trace packet, ([0039]; regarding, “Trace collection 230 hardware gets new trace data from the CPU core 201 every cycle. This trace comes form different pipeline stages of CPU core 201. Pipeline flattener 401 combines all data from different clock cycles within the instruction pipeline that correspond to the same instruction.”);
wherein the program counter discontinuities are represented as differences in addresses. ([0056]; regarding, “The unique exception signal is sent to pipeline flattener 401 followed by the target address of the discontinuity. This happens after the completion of the pipeline delay slots. Trace encoding hardware 230 then produces an exception packet. This exception packet indicates that this particular program counter discontinuity is as a result of emulation directed modification of the program counter.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Williams and Volpe with the teachings of Agarwala. Doing so may reduce power consumption (Agarwala [0012]).
With regards to Claim 2, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 1 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the footer includes first information indicative of a length of the given trace packet. (Volpe, Col. 18, lines 62-64; regarding, header information can be in footer; Col. 24, lines 62-65; regarding, packet header may include length).
With regards to Claim 3, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 2 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the footer further includes second information indicative of a presence of timestamp information in a different data section of the ordered data structure of data sections, (Volpe, Fig. 4; Col. 17, lines 66-67; regarding, a timestamp stored within a packet);
and wherein the timestamp information includes third information indicative of a count value that is incremented during a given clock cycle of the processor circuit. (Volpe, Fig. 4; Col. 17, lines 66-67 and Col. 18, lines 1-3; regarding, timestamp can be compared to a system clock).
With regards to Claim 4, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 1 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
further comprising a trace memory, (Volpe, Fig. 1A; regarding, memory);
and wherein the trace circuit is further configured to store the plurality of trace packets in the trace memory. (Volpe, Col. 18, lines 66-67 and Col. 19 line 1; Col. 19, lines 9-13).
With regards to Claim 5, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 1 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the trace circuit includes a trace decision circuit configured to generate a packet type identifier and packet field data using the trace information. (Williams, [0037]; regarding, identifying groups or types of packets corresponding to an event).
With regards to Claim 6, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 5 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the trace circuit further includes a trace packet builder circuit configured to:
generate a given trace packet of the plurality of trace packets using the packet type identifier and the packet field data; (Williams, [0038]; regarding, “In some situations there may be several types of trace packet… the types of trace packet may include… control trace packet… marker trace packet… marked trace packet…”);
Claims 7-9 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claims 1-2, and 4 respectively.
With regards to Claim 10, Williams in view of Volpe in further view of Agarwala teaches the method of Claim 9 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
reading, by a decoder, a last trace packet of the plurality of trace packets stored in the memory circuit using a trace packet pointer; (Volpe, Col. 5, lines 64-66; Col. 6, lines 1-5; regarding, “Forwarding table(s) can be stored onboard memory of integrated circuit 102 and can be accessed by packet processors 110, for example, to select an address… Host Interface 112 can enable relatively high bandwidth communications between integrated circuit 102, CPU 104, and/or memory 106.”);
determining, by the decoder, a location in the memory circuit of a preceding trace packet using length information included in a footer data section included in the last trace packet; (Volpe, Col. 6, lines 11-19; regarding, “The registers corresponding to packet processors 110 can store information pertaining to one or more operations of packet processors 110 including, for example, a number of dropped packets, a number of forwarded packets, a number of received packets, a number of trapped packets, a number of packets forwarded to a specific address or specific prefix…” and Col. 6, lines 25-50; regarding, “CPU 104 can access each of the registers to periodically collect information stored therein… Information within the registers can be used to determine, for example, if the test packets were correctly received and/or routed by device 102…”);
and in response to identifying corresponding locations of the plurality of trace packets, (Volpe, Col. 6, lines 43-50);
decoding the plurality of trace packets starting with an initial trace packet of the plurality of trace packets using the corresponding locations. (Volpe, Col. 7, lines 55-66).
With regards to Claim 11, Williams in view of Volpe in further view of Agarwala teaches the method of Claim 10 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein generating a particular trace packet of the plurality of trace packets includes:
determining a packet type for the particular trace packet using the trace information; (Volpe, Col. 11, lines 43-46; regarding, packet data can identify types of test data packets);
and determining a particular payload for the particular trace packet using the trace information. (Volpe, Col. 11, lines 50-56; regarding, test information can be included within a payload).
With regards to Claim 12, Williams in view of Volpe in further view of Agarwala teaches the method of Claim 11 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
assembling the particular trace packet using the packet type and the particular payload; (Volpe, Col. 11, lines 50-56);
and storing the compressed trace packet in the memory circuit. (Volpe, Col. 19, lines 9-11, 51-65; regarding, “Data to populate packet a payload data can be retrieved from memory 902… The length(s) can be modified based upon a profile stored in memory 902… Memory 902 can be embedded within packet generator 904 and/or shared between several packet generators…”).
With regards to Claim 13, Williams in view of Volpe in further view of Agarwala teaches the method of Claim 7 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
in response to detecting a load/store instruction in the trace information, assigning an index from a pool of indices to the load/store instruction. (Volpe, Col. 6, lines 11-13 and 25-26; regarding, a CPU accessing registers; Col. 17, lines 52-57).
With regards to Claim 14, Williams teaches:
An apparatus, comprising:
a processor circuit configured to generate trace information in response to an activation of a trace operation; ([0065]; regarding, “The processing apparatus 1 also comprises at least one trace module 12 for generating trace data indicative of characteristics of the processing apparatus 1”);
and a trace circuit coupled to the processor circuit via a trace interface, ([0065]; regarding, “the trace module 12 of FIG. 1 is shown within the data processing apparatus 1”);
wherein the trace circuit is configured to:
receive the trace information from the processor circuit via the trace interface; ([0098]; regarding, “The trace circuitry 50 monitors information received from the trace target at a trace target port 58”);
Williams fails to explicitly disclose but Volpe teaches:
in response to a detection of a load/store instruction in the trace information:
assign a particular index to the load/store instruction from a pool of indices; (Volpe, Col. 6, lines 11-13 and 25-26; regarding, a CPU accessing registers; Col. 17, lines 52-57);
generate a data index trace packet using the particular index. (Volpe, Col. 10, lines 38-41; Col. 13, lines 57-61).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Williams with the teachings of Volpe. Doing so can reduce CPU overhead (Volpe, Col. 17, lines 43-45).
Williams in view of Volpe fails to explicitly disclose but Agarwala teaches:
and encode program counter discontinuities associated with the given trace packet to generate a compressed trace packet, ([0039]; regarding, “Trace collection 230 hardware gets new trace data from the CPU core 201 every cycle. This trace comes form different pipeline stages of CPU core 201. Pipeline flattener 401 combines all data from different clock cycles within the instruction pipeline that correspond to the same instruction.”);
wherein the program counter discontinuities are represented as differences in addresses. ([0056]; regarding, “The unique exception signal is sent to pipeline flattener 401 followed by the target address of the discontinuity. This happens after the completion of the pipeline delay slots. Trace encoding hardware 230 then produces an exception packet. This exception packet indicates that this particular program counter discontinuity is as a result of emulation directed modification of the program counter.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Williams and Volpe with the teachings of Agarwala. Doing so may reduce power consumption (Agarwala [0012]).
With regards to Claim 15, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 14 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the trace circuit is further configured, in response to a detection of a bus access corresponding to an execution of the load/store instruction in the trace information, (Volpe, Col. 25, lines 9-12; regarding, a bus interface module; Col. 6, lines 11-13 and 25-26; regarding, a CPU accessing registers; Col. 17, lines 52-57);
to generate a data access trace packet using the particular index. (Volpe, Col. 10, lines 38-41; Col. 13, lines 57-61).
With regards to Claim 16, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 15 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
further comprising a memory circuit configured to store the data index trace packet and the data access trace packet. (Volpe, Col. 18, lines 66-67 and Col. 19 line 1; Col. 19, lines 9-13).
With regards to Claim 17, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 15 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein to assign the particular index, the trace circuit is further configured to compare the load/store instruction to at least one filter criterion. (Volpe, Col. 17, lines 46-50; regarding, memory being used by packet checker; Col. 13, lines 62-63; regarding, filtering or checking at a packet checker).
With regards to Claim 18, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 14 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the data index trace packet includes an ordered data structure of a plurality of data sections, (Williams, [0093]; Fig. 6);
wherein an initial data section of the plurality of data sections includes a payload for the data index trace packet, (Volpe, Fig. 4; Col. 12, lines 44-48);
and wherein a final data section of the plurality of data sections includes a footer for the data index trace packet. (Volpe, Fig. 4; Col. 16, lines 64-66).
With regards to Claim 19, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 18 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the footer includes first information indicative of a length of the data index trace packet, (Volpe, Col. 18, lines 62-64; regarding, header information can be in footer; Col. 24, lines 62-65; regarding, packet header may include length).
and wherein the payload includes second information indicative of the particular index. (Volpe, Col. 13, lines 57-61; regarding, header index; Col. 11, lines 17-19; regarding, header information is parsed from packet payload).
With regards to Claim 20, Williams in view of Volpe in further view of Agarwala teaches the apparatus of Claim 14 as cited above. Williams in view of Volpe in further view of Agarwala further teaches:
wherein the trace circuit is further configured to store the compressed trace packet in a memory circuit (Volpe, Col. 6, lines 33-42; regarding, “The operations of the device can include correctly routing test packets to a specific location, trapping a test packet that is not correctly addressed/formatted, correctly de-encapsulating and/or re-encapsulating a test packet, etc. In certain embodiments device 102 can include memory (not shown) that can be a buffer for trapping test and other packets. In such embodiments, CPU 104 may access the memory to obtain trapped packet(s).”).
Response to Arguments
Applicant’s arguments filed 07/31/2026 have been fully considered.
Applicant’s arguments with respect to claim(s) 1, 7, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/M.D.G./Examiner, Art Unit 2113
/BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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