DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/492,787 filed on 24 October 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species 2 (FIG. 6) embodiment in the reply filed on 30 March 2026 is acknowledged.
Regarding Applicant’s listing of claims 1-10, 12, 16, and 17 as readable on the elected species, however, the Examiner respectfully notes that claim 12 does not belong to the elected Species 2 embodiment. Claim 12 recites the limitation “the diode portion includes: an anode region of the second conductivity type which is arranged between the drift region and the upper surface of the semiconductor substrate, and a doping concentration of the base region and a doping concentration of the anode region differ.” Applicant’s elected embodiment is depicted in FIG. 6, however, which shows only base regions, and not anode regions. The unelected Species 4 embodiment is depicted in FIG. 8, which shows base regions and anode regions.
Accordingly, claims 11-15 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 10, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2019/0096989 (published Mar. 28, 2019) (hereinafter “Yoshida”).
Regarding independent claim 1, Yoshida discloses: A semiconductor device (FIG. 3, semiconductor device 100, [0053]) including a semiconductor substrate having an upper surface (FIG. 3, depicting wherein semiconductor substrate 10 has an upper surface 21, [0098]) and a lower surface (FIG. 3, depicting wherein semiconductor substrate 10 has an upper surface 21, [0097]), comprising:
a transistor portion provided in the semiconductor substrate (FIG. 3, depicting a transistor section 70 provided in the semiconductor substrate 10, [0057]);
a diode portion which is provided in the semiconductor substrate and is arranged next to the transistor portion in a first direction (FIG. 3, depicting a diode section 80 provided in the semiconductor substrate 10 and arranged next to the transistor section 70 in a first direction, [0057]); and
a boundary region which is provided in the semiconductor substrate and is arranged between the transistor portion and the diode portion (FIG. 3, depicting a boundary section 90 provided in the semiconductor substrate 10 and arranged between the transistor section 70 and the diode section 80, [0057]),
wherein the diode portion includes a lifetime adjustment region which is arranged in the upper surface side of the semiconductor substrate (FIG. 3, depicting wherein the diode section 80 includes a lifetime reduction region 92 arranged on a side of the upper surface 21, [0087]) and contains a lifetime killer that adjusts a lifetime of carriers (FIG. 3, [0087]: “The upper-surface-side lifetime reduction region 92 is a region in which the lifetime killer is intentionally introduced by, for example, implantation of impurities into the semiconductor substrate 10.”),
the boundary region includes:
a first portion which is in contact with the transistor portion and is not provided with the lifetime adjustment region (FIG. 3, depicting wherein the boundary section 90 includes a first portion contacts the transistor section 70 and in which the lifetime reduction region 92 is not provided); and
a second portion which is in contact with the diode portion and to which the lifetime adjustment region of the diode portion extends (FIG. 3, depicting wherein the boundary section 90 includes a second portion contacts the diode section 80 and in which the lifetime reduction region 92 provided in the diode section 80 extends),
a density distribution of the lifetime killer in the first direction has a lateral slope where a density of the lifetime killer decreases from the second portion of the boundary region toward the first portion (FIG. 3, depicting wherein the lifetime reduction region 92 is disposed in the second region but not the first region such that the lifetime killer is disposed in the second region but not the first region, and thus the concentration of the lifetime killer would decrease from a first value in the second region to a second value that in the first region that is less than the first value, and therefore the density distribution of the lifetime killer would have a lateral slope between the first value and the second value such that the density of the lifetime killer would decrease from the second portion toward the first portion, [0087]),
a width of the first portion is smaller than a width of the second portion in the first direction (FIG. 3, depicting wherein a width of the first portion is smaller than a width of the second portion), and
the width of the first portion is equal to or larger than a width of the lateral slope in the first direction (FIG. 3, depicting wherein the width of the first portion is larger than the width of the interface between the lifetime reduction region 92 and the first portion).
Regarding claim 2, Yoshida further discloses wherein the density distribution of the lifetime killer in a depth direction of the semiconductor substrate has a density peak in the second portion (FIG. 3, depicting wherein a doping concentration of lifetime killer has a peak concentration in the depth direction in the second portion, [0121]), and the width of the first portion in the first direction is equal to or larger than a peak width of the density peak in the depth direction (FIG. 3, depicting wherein the width of the first portion is larger than a peak concentration width in the depth direction).
Regarding claim 3, Yoshida further discloses wherein the width of the first portion in the first direction is equal to or larger than a distance from the upper surface of the semiconductor substrate to the density peak (FIG. 3, depicting wherein the width of the first portion is larger than a distance from the upper surface 21 of the semiconductor substrate 10 to the peak concentration of the lifetime reduction region 92).
Regarding claim 4, Yoshida further discloses wherein the transistor portion (FIG. 3, transistor section 70) includes:
a plurality of trench portions arranged next to one another in the first direction (FIG. 3, depicting a plurality of trench portions 30 arranged next to one another in the first direction, [0070]); and
a mesa portion sandwiched between two of the trench portions (FIG. 3, depicting a mesa portion 94-1 sandwiched between two trench portions 30, [0141]), and
the width of the first portion in the first direction is 2 times or more of a width of the mesa portion in the first direction (FIG. 3, depicting wherein a width of the first portion in the first direction is greater than a width of two mesa portions 94-1).
Regarding claim 5, Yoshida further discloses wherein the transistor portion (FIG. 3, transistor section 70) includes:
a plurality of trench portions arranged next to one another in the first direction (FIG. 3, depicting a plurality of trench portions 30 arranged next to one another in the first direction, [0070]); and
a mesa portion sandwiched between two of the trench portions (FIG. 3, depicting a mesa portion 94-1 sandwiched between two trench portions 30, [0141]), and
the width of the first portion in the first direction is larger than a width obtained by adding a width of at least one of the trench portions and a width of two of the mesa portions sandwiching the trench portion in the boundary region (FIG. 3, depicting wherein a width of the first portion in the first direction is greater than a width of two mesa portions 94-1 and at least one trench portion 30 sandwiching the trench portion in the boundary section 90).
Regarding claim 10, Yoshida further discloses wherein the width of the second portion in the first direction is equal to or larger than a distance from the upper surface of the semiconductor substrate to the density peak (FIG. 3, depicting wherein a width of the second portion in the first direction is larger than a distance from the upper surface 21 of the semiconductor substrate 10 to the peak concentration of the lifetime reduction region 92).
Regarding claim 16, Yoshida further discloses an upper surface electrode arranged above the upper surface of the semiconductor substrate (FIG. 3, depicting emitter electrode 52 arranged above the upper surface 21, [0068]); and
an interlayer dielectric film arranged between the upper surface electrode and the semiconductor substrate (FIG. 4, depicting an interlayer dielectric film arranged between the emitter electrode 52 and the semiconductor substrate 10, [0069]),
wherein in the boundary region, the interlayer dielectric film is provided with a contact hole that connects the upper surface electrode and the semiconductor substrate and has a longitudinal length in a second direction (FIG. 4, depicting wherein in the boundary section 90, the interlayer dielectric film is provided with a hole, e.g., contact hole 54, that connects the emitter electrode 52 and the semiconductor substrate 10, and further wherein the contact hole 54 has a longitudinal length in a second direction), and
when an end portion of the contact hole in the second direction is set as an end portion of the boundary region in the second direction (FIGS. 3/4, depicting wherein an end portion of a contact hole 54 may be set as an end portion of the boundary section 90),
an area Sk of the second portion and an area S of the boundary region in a top view satisfy an expression below 0.8 ≤ Sk/S < 1 (FIGS. 3/4/6/7, depicting wherein the semiconductor device 100 depicts numerous areas of the first and second portions in the boundary section 90 that may satisfy a number of expressions, including a particular expression wherein 0.8 ≤ area of the second portion/area of the first portion < 1).
Regarding independent claim 17, Yoshida discloses: A semiconductor device (FIG. 3, semiconductor device 100, [0053]) including a semiconductor substrate having an upper surface (FIG. 3, depicting wherein semiconductor substrate 10 has an upper surface 21, [0098]) and a lower surface (FIG. 3, depicting wherein semiconductor substrate 10 has an upper surface 21, [0097]), comprising:
a transistor portion provided in the semiconductor substrate (FIG. 3, depicting a transistor section 70 provided in the semiconductor substrate 10, [0057]);
a diode portion which is provided in the semiconductor substrate and is arranged next to the transistor portion in a first direction (FIG. 3, depicting a diode section 80 provided in the semiconductor substrate 10 and arranged next to the transistor section 70 in a first direction, [0057]); and
a boundary region which is provided in the semiconductor substrate and is arranged between the transistor portion and the diode portion (FIG. 3, depicting a boundary section 90 provided in the semiconductor substrate 10 and arranged between the transistor section 70 and the diode section 80, [0057]);
an upper surface electrode arranged above the upper surface of the semiconductor substrate (FIG. 3, depicting emitter electrode 52 arranged above the upper surface 21, [0068]); and
an interlayer dielectric film arranged between the upper surface electrode and the semiconductor substrate (FIG. 4, depicting an interlayer dielectric film arranged between the emitter electrode 52 and the semiconductor substrate 10, [0069]),
wherein the diode portion includes a lifetime adjustment region which is arranged in the upper surface side of the semiconductor substrate (FIG. 3, depicting wherein the diode section 80 includes a lifetime reduction region 92 arranged on a side of the upper surface 21, [0087]) and contains a lifetime killer that adjusts a lifetime of carriers (FIG. 3, [0087]: “The upper-surface-side lifetime reduction region 92 is a region in which the lifetime killer is intentionally introduced by, for example, implantation of impurities into the semiconductor substrate 10.”),
the boundary region includes:
a first portion which is in contact with the transistor portion and is not provided with the lifetime adjustment region (FIG. 3, depicting wherein the boundary section 90 includes a first portion contacts the transistor section 70 and in which the lifetime reduction region 92 is not provided); and
a second portion which is in contact with the diode portion and to which the lifetime adjustment region of the diode portion extends (FIG. 3, depicting wherein the boundary section 90 includes a second portion contacts the diode section 80 and in which the lifetime reduction region 92 provided in the diode section 80 extends),
in the boundary region, the interlayer dielectric film is provided with a contact hole that connects the upper surface electrode and the semiconductor substrate and has a longitudinal length in a second direction (FIG. 4, depicting wherein in the boundary section 90, the interlayer dielectric film is provided with a hole, e.g., contact hole 54, that connects the emitter electrode 52 and the semiconductor substrate 10, and further wherein the contact hole 54 has a longitudinal length in a second direction, and
when an end portion of the contact hole in the second direction is set as an end portion of the boundary region in the second direction (FIGS. 3/4, depicting wherein an end portion of a contact hole 54 may be set as an end portion of the boundary section 90),
an area Sk of the second portion and an area S of the boundary region in a top view satisfy an expression below 0.8 ≤ Sk/S < 1 (FIGS. 3/4/6/7, depicting wherein the semiconductor device 100 depicts numerous areas of the first and second portions in the boundary section 90 that may satisfy a number of expressions, including a particular expression wherein 0.8 ≤ area of the second portion/area of the first portion < 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of U.S. Patent Publication No. 2022/0123108 (published Apr. 21, 2022) (hereinafter “Ozaki”).
Regarding claim 6, Yoshida does not specifically disclose wherein the width of the first portion in the first direction is 1 µm or more.
In the same field of endeavor, however, Ozaki discloses a semiconductor device (FIG. 1B, depicting a semiconductor device 100, [0076]) including a first portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a first portion of the injection suppression region 90 borders the transistor portion 70 and is not provided with a lifetime control region 85 including a lifetime killer, [0060], [0097]) and a second portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a second portion of the injection suppression region 90 borders the diode portion 80 and the second portion of the injection suppression region and diode portion 80 are provided with an extending lifetime control region 85 including a lifetime killer, [0060], [0097]). Ozaki further discloses in [0106]: “In the injection suppression region 90, the interval between the end portion K of the lifetime control region 85 in the arrangement direction (X axis direction) and a boundary portion L between the injection suppression region 90 and the transistor portion 70 may be 1 μm or more.” Regarding the interval between the end portion K of the lifetime control region 85 and a boundary portion L between the injection suppression region 90 and the transistor portion 70, in [0107], Ozaki states: “The lifetime control region 85 is formed by, for example, irradiating protons or helium from the front surface 21 through a thick resist mask of 30 to 80 μm. Therefore, if the lifetime control region 85 is not slightly retracted into the injection suppression region 90, the lifetime control region 85 is formed in the transistor portion 70 when the inclination angle of the thick resist varies, and the threshold voltage tends to decrease or vary.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to modify the semiconductor device of Yoshida by forming the first and second regions such that a width of the first portion is 1 μm or more as disclosed by Ozaki, in order to prevent formation of the lifetime reduction region 92 in the transistor section 70, and therefore preventing threshold decrease or variation. See Ozaki [0106]-[0107].
Moreover, Ozaki “discloses a range encompassing a somewhat narrower claimed range,” and thus establishes a prima facie case of obviousness. MPEP § 2144.05(I) (quoting In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003)); see also In re Peterson, 315F.3d at 1382 (“In fact, when, as here, the claimed ranges are completely encompassed by the prior art, the conclusion is even more compelling than in cases of mere overlap. The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.”) (citing In re Boesch, 617 F.2d 272, 276 (CCPA 1980).
Applicant has not presented persuasive evidence that the claimed ranges are for a particular purpose that is critical to the overall claimed invention
Regarding claim 7, Yoshida does not specifically disclose wherein the width of the first portion in the first direction is 10 µm or more.
In the same field of endeavor, however, Ozaki discloses a semiconductor device (FIG. 1B, depicting a semiconductor device 100, [0076]) including a first portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a first portion of the injection suppression region 90 borders the transistor portion 70 and is not provided with a lifetime control region 85 including a lifetime killer, [0060], [0097]) and a second portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a second portion of the injection suppression region 90 borders the diode portion 80 and the second portion of the injection suppression region and diode portion 80 are provided with an extending lifetime control region 85 including a lifetime killer, [0060], [0097]). Ozaki further discloses in [0106]: “In the injection suppression region 90, the interval between the end portion K of the lifetime control region 85 in the arrangement direction (X axis direction) and a boundary portion L between the injection suppression region 90 and the transistor portion 70 may be 1 μm or more.” Regarding the interval between the end portion K of the lifetime control region 85 and a boundary portion L between the injection suppression region 90 and the transistor portion 70, in [0107], Ozaki states: “The lifetime control region 85 is formed by, for example, irradiating protons or helium from the front surface 21 through a thick resist mask of 30 to 80 μm. Therefore, if the lifetime control region 85 is not slightly retracted into the injection suppression region 90, the lifetime control region 85 is formed in the transistor portion 70 when the inclination angle of the thick resist varies, and the threshold voltage tends to decrease or vary.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to modify the semiconductor device of Yoshida by forming the first and second regions such that a width of the first portion is 10 μm or more as disclosed by Ozaki, in order to prevent formation of the lifetime reduction region 92 in the transistor section 70, and therefore preventing threshold decrease or variation. See Ozaki [0106]-[0107].
Moreover, Ozaki “discloses a range encompassing a somewhat narrower claimed range,” and thus establishes a prima facie case of obviousness. MPEP § 2144.05(I) (quoting In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003)); see also In re Peterson, 315F.3d at 1382 (“In fact, when, as here, the claimed ranges are completely encompassed by the prior art, the conclusion is even more compelling than in cases of mere overlap. The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.”) (citing In re Boesch, 617 F.2d 272, 276 (CCPA 1980).
Applicant has not presented persuasive evidence that the claimed ranges are for a particular purpose that is critical to the overall claimed invention
Regarding claim 8, Yoshida does not specifically disclose wherein the width of the first portion in the first direction is 200 µm or less.
In the same field of endeavor, however, Ozaki discloses a semiconductor device (FIG. 1B, depicting a semiconductor device 100, [0076]) including a first portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a first portion of the injection suppression region 90 borders the transistor portion 70 and is not provided with a lifetime control region 85 including a lifetime killer, [0060], [0097]) and a second portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a second portion of the injection suppression region 90 borders the diode portion 80 and the second portion of the injection suppression region and diode portion 80 are provided with an extending lifetime control region 85 including a lifetime killer, [0060], [0097]). Ozaki further discloses in [0106]: “In the injection suppression region 90, the interval between the end portion K of the lifetime control region 85 in the arrangement direction (X axis direction) and a boundary portion L between the injection suppression region 90 and the transistor portion 70 may be 1 μm or more.” Regarding the interval between the end portion K of the lifetime control region 85 and a boundary portion L between the injection suppression region 90 and the transistor portion 70, in [0107], Ozaki states: “The lifetime control region 85 is formed by, for example, irradiating protons or helium from the front surface 21 through a thick resist mask of 30 to 80 μm. Therefore, if the lifetime control region 85 is not slightly retracted into the injection suppression region 90, the lifetime control region 85 is formed in the transistor portion 70 when the inclination angle of the thick resist varies, and the threshold voltage tends to decrease or vary.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to modify the semiconductor device of Yoshida by forming the first and second regions such that a width of the first portion is 200 μm or less as disclosed by Ozaki, in order to prevent formation of the lifetime reduction region 92 in the transistor section 70, and therefore preventing threshold decrease or variation. See Ozaki [0106]-[0107].
Moreover, Ozaki “discloses a range encompassing a somewhat narrower claimed range,” and thus establishes a prima facie case of obviousness. MPEP § 2144.05(I) (quoting In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003)); see also In re Peterson, 315F.3d at 1382 (“In fact, when, as here, the claimed ranges are completely encompassed by the prior art, the conclusion is even more compelling than in cases of mere overlap. The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.”) (citing In re Boesch, 617 F.2d 272, 276 (CCPA 1980).
Applicant has not presented persuasive evidence that the claimed ranges are for a particular purpose that is critical to the overall claimed invention
Regarding claim 9, Yoshida does not specifically disclose wherein the width of the first portion in the first direction is 10% or more of a width of the boundary region in the first direction.
In the same field of endeavor, however, Ozaki discloses a semiconductor device (FIG. 1B, depicting a semiconductor device 100, [0076]) including a first portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a first portion of the injection suppression region 90 borders the transistor portion 70 and is not provided with a lifetime control region 85 including a lifetime killer, [0060], [0097]) and a second portion (FIG. 1B, depicting wherein the semiconductor device includes an injection suppression region 90 between a transistor portion 70 and a diode portion 80, wherein a second portion of the injection suppression region 90 borders the diode portion 80 and the second portion of the injection suppression region and diode portion 80 are provided with an extending lifetime control region 85 including a lifetime killer, [0060], [0097]). Ozaki further discloses in [0106]: “In the injection suppression region 90, the interval between the end portion K of the lifetime control region 85 in the arrangement direction (X axis direction) and a boundary portion L between the injection suppression region 90 and the transistor portion 70 may be 1 μm or more.” Regarding the interval between the end portion K of the lifetime control region 85 and a boundary portion L between the injection suppression region 90 and the transistor portion 70, in [0107], Ozaki states: “The lifetime control region 85 is formed by, for example, irradiating protons or helium from the front surface 21 through a thick resist mask of 30 to 80 μm. Therefore, if the lifetime control region 85 is not slightly retracted into the injection suppression region 90, the lifetime control region 85 is formed in the transistor portion 70 when the inclination angle of the thick resist varies, and the threshold voltage tends to decrease or vary.” Ozaki further states in [0108]: “Therefore, by providing the lifetime control region 85 up to a position slightly retracted in the injection suppression region 90, even if the inclination angle of the resist mask varies, the lifetime control region 85 is not formed in the transistor portion 70, and it is possible to prevent a decrease or variation in the threshold voltage.” Thus, noted in Ozaki, the interval between the end portion K of the lifetime control region 85 and a boundary portion L between the injection suppression region 90 and the transistor portion 70 is a result effective variable for optimizing the position of the lifetime control region, and thus determining threshold voltage characteristics of the semiconductor device.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the first portion relative to the width of the boundary section 90, identified by Ozaki as a result-effective variable. One of ordinary skill in the art would have had a reasonable expectation of success to arrive at a width such that the width of the first portion in the first direction is 10% or more of a width of the boundary region in the first direction in order to achieve a desired balance lifetime reduction region 92 position and threshold voltage characteristics as disclosed in Ozaki in [0106]-[0108]. See MPEP § 2144.05 (“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”) (quoting In re Aller, 220 F.2d 454, 456 (C.C.P.A. 1955)).
Applicant has not presented persuasive evidence that the claimed ranges are for a particular purpose that is critical to the overall claimed invention
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2020/0357903 (depicting a variable concentration lifetime control region); 2019/0326118 (depicting a variable depth lifetime control region).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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