DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 1/8/2026 have been accepted. Claims 1-20 are still pending. Claims 1, 4, 5, 12, 16, and 19 are amended. Claim 6 has been canceled. Applicant’s amendments to the claims have overcome each and every 103 rejection previously set forth in the Non-Final Office Action mailed 10/8/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "second data" which lacks antecedent basis as there is no longer a reference to “first data” in the claims (as any reference to “first data” has been removed from claim 1 with the amendments).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US PGPub 2017/0315925) in view of Byun (US PGPub 2021/0255961) in view of Kang (US PGPub 2021/0311879) in view of Callister et al. (US PGPub 2007/0067602, hereafter referred to as Callister).
Regarding claim 1, Yeh teaches a storage device comprising: a first memory, a plurality of non-volatile memories having an access speed slower than an access speed of the first memory (Fig. 4-5 and Paragraphs [0039]-[0044], shows the storage device and memory control circuit that contain a buffer memory (first memory) and non-volatile memory module which has multiple dies. While not explicitly stated the purpose of buffer memory is to offer faster memory that data can be stored in temporarily before being transferred to the non-volatile memory), and a controller configured to control a first data input/output operation with a host device using the plurality of non-volatile memories, based on a first map table stored in the first memory, in a first mode (Paragraphs [0011]-[0012] and [0072]-[0074], states how the memory management circuit (controller) will control the memory in a first operating mode using a sub-mapping table that is loaded into the buffer memory for use), and control a second data input/output operation with the host device using the first memory, based on a second map table stored in the first memory, in a second mode (Paragraphs [0011]-[0012] and [0072]-[0074], the memory management circuit can operate in a second mode using a different mapping table that is loaded into the first memory. It should be noted the claims do not state how the first memory is used to control the I/O operations), wherein the storage device is configured to switch between the first mode and the second mode (Paragraphs [0011]-[0012] and [0072]-[0074], as stated previously, the device can switch between the different modes), wherein the first map table includes physical addresses of the plurality of non- volatile memories for accessing first data from the plurality of non-volatile memories, the first data corresponding to the first data input/output operation, wherein the second map table includes physical addresses of the first memory for accessing the second data from the first memory (Paragraphs [0011]-[0012] and [0072]-[0074], states the sub-tables are logical to physical mapping tables meaning that they would contain the address information of the data being operated on as that is why they are the maps being used), wherein the controller is configured to control the storage device to move the first map table from the first memory to the plurality of non-volatile memories when changing from the first mode to the second mode (Paragraph [0058], [0099], and [0104], states that the mapping tables associated with a particular operation (and mode) can be updated in the buffer meaning that they would have to be loaded in the buffer for updating and then stored back to the non-volatile memory once updated and the mode has switched based on a different operation). Yeh does not teach wherein the second map table includes physical addresses of the first memory for accessing second data from the first memory, move second data related to the second data input/output operation from the plurality of non-volatile memories to the first memory when changing from the first mode to the second mode, move the second data related to the second data input/output operation from the first memory to the plurality of non-volatile memories when changing from the second mode to the first mode, wherein the second map table and the second data are stored separately in the first memory during the second mode.
Byun teaches wherein the second map table includes physical addresses of the first memory for accessing second data from the first memory (Paragraphs [0065]-[0069], the different modes will create different mapping tables that correspond to a first memory device and a second, separate memory device which map the logical addresses of the host to the physical addresses of the memory devices). Since both Yeh and Byun teach multiple mapping tables it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh to also have a mapping table related to the first memory as taught in Byun to obtain the predictable result of wherein the second map table includes physical addresses of the first memory for accessing second data from the first memory, the second data corresponding to the second data input/output operation. Yeh and Byun do not teach move second data related to the second data input/output operation from the plurality of non-volatile memories to the first memory when changing from the first mode to the second mode, moving the second data related to the second data input/output operation from the first memory to the plurality of non-volatile memories when changing from the second mode to the first mode, and wherein the second map table and the second data are stored separately in the first memory during the second mode.
Kang teaches move the first map table from the plurality of non-volatile memories to the first memory when changing from the second mode to the first mode (Paragraphs [0116] and [0121]-[0124], states that map data can be stored and updated in the memory and when no longer needed (changing modes, etc.) can be stored back into the non-volatile memory and then when in a different mode (requiring different map data) the controller can load the map data required for that mode). Since both Yeh/Byun and Kang teach mapping tables it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh and Byun to store the data associated with the map tables when switching modes as taught in Kang to obtain the predictable result of moving the first map table from the plurality of non-volatile memories to the first memory when changing from the second mode to the first mode. Yeh, Byun, and Kang do not teach move second data related to the second data input/output operation from the plurality of non-volatile memories to the first memory when changing from the first mode to the second mode, moving the second data related to the second data input/output operation from the first memory to the plurality of non-volatile memories when changing from the second mode to the first mode, and wherein the second map table and the second data are stored separately in the first memory during the second mode.
Callister teaches moving second data related to the second data input/output operation from the plurality of memories to the first memory when changing from the first mode to the second mode, moving the second data related to the second data input/output operation from the first memory to the plurality of memories when changing from the second mode to the first mode, and wherein the second map table and the second data are stored separately in the first memory during the second mode (Paragraph [0001], states the purpose of the reference is to better handle context switches where map data and working sets (data akin to second data) is swapped out of a cache and TLB. Paragraphs [0013]-[0015], states that upon a context switch data associated with a process (context) can be stored (moved out of the first memory to the plurality of memories) and that data can include map data and second data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yeh, Byun, and Kang to utilize the method of context switching as taught in Callister so to facilitate mitigating some effects of cache and TLB misses related to process context switching in a multiprogramming, virtual memory computing system (Callister, Paragraph [0013]).
Regarding claim 2, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the first map table indicates a mapping relationship between first logical addresses of the host device and the physical addresses of the plurality of non-volatile memories (Paragraph [0072], the mapping tables in question are logical-to-physical address tables). Byun further teaches the second map table indicates a mapping relationship between second logical addresses of the host device and physical addresses of the first memory (Paragraphs [0065]-[0069], the different modes will create different mapping tables that correspond to a first memory device and a second, separate memory device which map the logical addresses of the host to the physical addresses of the memory devices). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 3, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the controller is further configured to, when changing from the first mode to the second mode, to move the second map table from the plurality of non-volatile memories to the first memory (Paragraph [0058], [0099], and [0104], states that the mapping tables associated with a particular operation (and mode) can be updated in the buffer meaning that they would have to be loaded in the buffer for updating and then stored back to the non-volatile memory once updated and the mode has switched based on a different operation). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 4, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the controller is further configured to, when changing from the second mode to the first mode, control the storage device to move the first map table from the plurality of non-volatile memories to the first memory (Paragraphs [0011]-[0012] and [0072]-[0074], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the second map table is stored in the first memory in the first mode and the second mode (Fig. 12A-12B and Paragraphs [0093]-[0097], shows that the second mapping table (810) is stored in one portion of the buffer for both modes). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 10, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Byun further teaches wherein the first memory is a volatile memory (Paragraph [0028], states the first memory can be a volatile memory). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 12, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the controller is configured to, when changing from the first mode to the second mode, to move data related to the second map table and to the second data input/output operation from the plurality of non-volatile memories to the first memory (Paragraphs [0011]-[0012] and [0072]-[0074], as stated in the rejection to claim 1. It should be noted the claims do not specify what the data is or how it relates to the table or I/O operations). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 13, Yeh, Byun, Kang, and Callister teach all the limitations to claim 12. Yeh further teaches wherein the storage device is configured to automatically change from the first mode to the second mode in response to not receiving the first data input/output operation within a present time period (Paragraphs [0100]-[0102], states that the modes can correspond to sequential read or sequential write operations meaning that if it is sequential write mode and does not receive a sequential write in a present time period and instead receives a sequential read it will switch to the sequential read mode). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 14, Yeh, Byun, Kang, and Callister teach all the limitations to claim 13. Yeh further teaches wherein the storage device is configured to return the data related to the second map table and to the second data input/output operation to the plurality of non-volatile memories (Paragraphs [0011]-[0012] and [0072]-[0074], as stated in the rejection to claims 1 and 12, when the mode changes the table related to that mode will be loaded in to the buffer memory meaning that upon switching back to a previous mode the related table will be loaded back into the buffer memory). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 15, Yeh, Byun, Kang, and Callister teach all the limitations to claim 13. Yeh further teaches wherein the storage device is configured to change back to the first mode in response to receiving the first data input/output operation (Paragraphs [0100]-[0102], as stated in the rejection to claim 13, if a sequential write is received the device would switch back to the sequential write mode). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 16, Claim 16 is the device claim associated with claims 1 and 10. Since Yeh, Byun, Kang, and Callister teach all the limitations to claims 1 and 10, they also teach all the limitations to claim 16; therefore the rejections to claims 1 and 10 also apply to claim 16.
Regarding claim 18, Yeh, Byun, Kang, and Callister teach all the limitations to claim 16. Yeh further teaches wherein the mode in which the input/output resources are not occupied by the first data input/output operation is a second mode and a mode in which the input/output resources are occupied by the first data input/output operation is the first mode, and the controller is configured to switch from the second mode to the first mode in response to detecting a first data input/output operation request from the host device (Paragraphs [0100]-[0102], states that the modes can correspond to sequential read or sequential write operations meaning that if the controller is occupied with a sequential read it will be in the sequential read mode and when it detects a sequential write it will switch to the sequential write mode). The combination of and reason for combining are the same as those given in claim 10.
Regarding claim 19, Yeh, Byun, Kang, and Callister teach all the limitations to claim 18. Yeh further teaches wherein the switch from the second mode to the first mode includes moving data related to the second map table operation from the volatile memory to the plurality of non-volatile memories (Paragraphs [0011]-[0012] and [0072]-[0074], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 20, Yeh, Byun, Kang, and Callister teach all the limitations to claim 19. Yeh further teaches wherein the first map table indicates a mapping relationship between first logical addresses of the host device and physical addresses of the plurality of non-volatile memories (Paragraph [0072], the mapping tables in question are logical-to-physical address tables). Byun further teaches the second map table indicates a mapping relationship between second logical addresses of the host device and physical addresses of the first memory (Paragraphs [0065]-[0069], the different modes will create different mapping tables that correspond to a first memory device and a second, separate memory device which map the logical addresses of the host to the physical addresses of the memory devices). The combination of and reason for combining are the same as those given in claim 1.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh, Byun, Kang, and Callister as applied to claim 1 above, and in further view of Shacham et al. (US PGPub 2015/0074294, hereafter referred to as Shacham).
Regarding claim 7, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Kang further teaches wherein the controller is configured to manage mode state information having at least one of a first value indicating a state of operating in the first mode, a second value indicating a state of operating in the second mode (Paragraph [0119] and [0127]-[0128], states that there can be an indicator/identifier that is used to state what mode to operate in and that identifier can have two different values). Kang further teaches an indication that a state in which the first mode is changed to the second mode and another indication indicating that a state in which the second mode is changed to the first mode (Paragraphs [0129]-[0132], describe the process of switching modes based on whether or not a random or sequential write has been received and preparing the maps based on the upcoming mode switch. However there are no specific identifier values present for indicating that the mode will switch). Since Yeh, Byun, Kang, and Callister teach switching modes it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh, Byun, and Kang to use an identifier to indicate the mode states as taught in Kang to obtain the predictable result of wherein the controller is configured to manage mode state information having at least one of a first value indicating a state of operating in the first mode, a second value indicating a state in which the first mode is changed to the second mode, a third value indicating a state of operating in the second mode, or a fourth value indicating that a state in which the second mode is changed to the first mode (as all this does is have values indicating the current mode or whether or not the mode needs to change). Yeh, Byun, and Kang do not teach reporting the mode state information to the host device in response to receiving a mode state check command from the host device.
Shacham teaches reporting the mode state information to the host device in response to receiving a mode state check command from the host device (Claims 1 and 11, states the controller can receive a command from a host for state information and send back a response with the requested information). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yeh, Byun, Kang, and Callister to have the host request state information as taught in Shacham so he host can select a task to commence after completion of a current data transfer while the current data transfer is still ongoing (Shacham, Abstract).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, Byun, Kang, Callister, and Shacham as applied to claim 7 above, and further in view of Makuni et al. (US PGPub 2021/0374051, hereafter referred to as Makuni).
Regarding claim 8, Yeh, Byun, Kang, Callister, and Shacham teach all the limitations to claim 7. Kang further teaches wherein the controller is configured to change the first mode to the second mode and update the mode state information from the second value to the third value in response to the mode state information having the second value (Paragraph [0119] and [0127]-[0132], as stated in the rejection to claim 7, the mode can change and the value of the identifier can be updated. This can apply with the modifications stated in the combination of claim 7 to also include values associated with the need to change state and the process of going through those stages). Yeh, Byun, Kang, Callister, and Shacham do not teach updating the value in response to receiving from the host device, a mode change command.
Makuni teaches wherein the controller is configured to change the first mode to the second mode and update the mode state information from a value to another value in response to receiving, from the host device, a mode change command (Paragraphs [0062]-[0063], states the existence of a mode switch command that can be issued by the host and a register to store the value received in the command and indicate the mode that the device is to be operated in). Since both Yeh/Byun/Kang/Callister/Shacham and Makuni teach having different modes it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh, Byun, Kang, and Shacham to also use a mode change command from the host as taught in Makuni to obtain the predictable result of wherein the controller is configured to change the first mode to the second mode and update the mode state information from the second value to the third value in response to receiving, from the host device, a mode change command and the mode state information having the second value (as all this does is have the host be able to specify when to switch modes).
Regarding claim 9, Yeh, Byun, Kang, Callister, and Shacham teach all the limitations to claim 7. Kang further teaches wherein the controller is configured to change from the second mode to the first mode and update the mode state information from the fourth value to the first value in response to the mode state information having the fourth value (Paragraph [0119] and [0127]-[0132], as stated in the rejection to claim 7, the mode can change and the value of the identifier can be updated. This can apply with the modifications stated in the combination of claim 7 to also include values associated with the need to change state and the process of going through those stages). Yeh, Byun, Kang, Callister, and Shacham do not teach updating the value in response to receiving from the host device, a mode change command.
Makuni teaches wherein the controller is configured to change from the second mode to the first mode and update the mode state information from a value to another value in response to receiving, from the host device, a mode change command (Paragraphs [0062]-[0063], states the existence of a mode switch command that can be issued by the host and a register to store the value received in the command and indicate the mode that the device is to be operated in). Since both Yeh/Byun/Kang/Callister/Shacham and Makuni teach having different modes it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh, Byun, Kang, Callister, and Shacham to also use a mode change command from the host as taught in Makuni to obtain the predictable result of wherein the controller is configured to change from the second mode to the first mode and update the mode state information from the fourth value to the first value in response to receiving, from the host device, a mode change command and the mode state information having the fourth value (as all this does is have the host be able to specify when to switch modes).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh, Byun, Kang, and Callister in view of Madan et. al. (US PGPub 2023/0350765, hereafter referred to as Madan).
Regarding claim 11, Yeh, Byun, Kang, and Callister teach all the limitations of claim 1. Yeh further teaches wherein the second data input/output operation includes transferring data from a first region of the plurality of non-volatile memories to the first memory and the first data input/output operation include writing data to a second region of the plurality of non-volatile memories (Paragraphs [0101]-[0103], describe the various modes and the I/O operations associated with them which can include a sequential write mode (first data I/O operation) and garbage collection mode (second data I/O operation)). Yeh, Byun, Kang, and Callister do not teach namespace regions of the plurality of non-volatile memories.
Madan teaches namespace regions of the plurality of non-volatile memories (Abstract, states the reference deals with cloning files from one namespace to another meaning there exists multiple namespace regions of memory. Paragraph [0060], states the memory can be non-volatile). Since both Yeh/Byun/Kang/Callister and Madan teach the use of non-volatile memories it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Yeh, Byun, Kang, and Callister to use namespaces as taught in Madan to obtain the predictable result of wherein the second data input/output operation includes transferring data from a first namespace region of the plurality of non-volatile memories to the first memory, and the first data input/output operation includes writing data to a second namespace region of the plurality of non-volatile memories (as the data to be written or garbage collected will be associated with a particular namespace).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the applicant amended the claims with the limitation “…move second data related to the second data input/output operation from the plurality of non-volatile memories to the first memory when changing from the first mode to the second mode… wherein the second map table includes physical addresses of the first memory for accessing the second data from the first memory, and wherein the second map table and the second data are stored separately in the first memory during the second mode.” to overcome the prior rejections set forth in the Non-Final Rejection mailed 10/8/2025. To address this, new reference Callister has been incorporated into the rejection to help teach the amended limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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