DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 9, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kishimoto (US 2022/0093579).
As to claim 1, Kishimoto teaches a method for manufacturing a power electronic device (fig. 10) comprising the following successive steps:
providing a silicon semiconductor substrate (100), the substrate having a front face (100T) and a rear face (100B), opposite the front face ([0109] and [0111]);
forming, by epitaxial growth from the front face of the substrate, a first continuous layer (50) of at least one nitrided transition metal coating the front face of the substrate ([0197]); and
forming, on the first layer, by epitaxial growth from the front face side of the substrate, at least one second layer (22) of a III-V material, preferably Ill-N ([0116] and [0120]),
wherein the first layer is of titanium nitride and extends laterally over and in contact with the front face of the substrate ([0197], fig. 10).
As to claim 6, Kashimoto further teaches the semiconductor substrate is substantially monocrystalline, the front face of the substrate having a crystalline orientation ([0113]).
As to claim 9, Kashimoto teaches a power electronic device (fig. 10) comprising:
a silicon semiconductor substrate (100), the substrate having a front face (100T) and a rear face (100B), opposite the front face ([0109] and [0111]);
a first continuous epitaxial layer (50) of at least one nitrided transition metal coating the front face of the substrate ([0197]); and
at least one second continuous epitaxial layer (22) of a III-V material, preferably Ill-N ([0116] and [0120]), located on the first layer,
wherein the first layer is of titanium nitride and extends laterally over and in contact with the front face of the substrate ([0197], fig. 10).
As to claim 13, Kashimoto further teaches a third continuous layer of a material selected from aluminum nitride, gallium nitride, and indium nitride, the third layer coating said face of the first layer ([0118], the layer need not be homogenous but can have a multi-layered structure).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer (US 2016/0035851) in view of Kashimoto.
As to claim 1, Meyer teaches a method for manufacturing a power electronic device (fig. 6) comprising the following successive steps:
Providing a silicon semiconductor substrate (1), the substrate having a front face and a rear face (top and bottom, respectively), opposite the front face ([0197], other types of substrates can be used, silicon is a well-known substrate material);
forming, by epitaxial growth from the front face of the substrate, a first continuous layer of at least one nitrided transition metal (2) coating the front face of the substrate ([0021]); and
forming, on the first layer, by epitaxial growth from the front face side of the substrate, at least one second layer of a III-V material, preferably Ill-N ([0022]),
wherein the first layer extends laterally over and in contact with the front face of the substrate (fig. 6).
Meyer does not teach the first layer is of titanium nitride (TiN). However, TiN is a known transition metal nitride in the semiconductor field and Kishimoto teaches forming a TiN buffer layer on a growth substrate between said substrate and epitaxially grown semiconductor layers ([0197]). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first layer comprise TiN so as to use an known material having predictable results and properties.
As to claim 9, Meyer teaches a power electronic device (fig. 6) comprising:
a silicon semiconductor substrate (1), the substrate having a front face and a rear face (top and bottom, respectively), opposite the front face ([0197], other types of substrates can be used, silicon is a well-known substrate material);
a first continuous epitaxial layer (2) of at least one nitrided transition metal coating the front face of the substrate ([0021]); and
at least one second continuous epitaxial layer (3) of a III-V material, preferably III-N, located on the first layer ([0022]),
wherein the first layer extends laterally over and in contact with the front face of the substrate (fig. 6).
Meyer does not teach the first layer is of titanium nitride. However, TiN is a known transition metal nitride in the semiconductor field and Kishimoto teaches forming a TiN buffer layer on a growth substrate between said substrate and epitaxially grown semiconductor layers ([0197]). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first layer comprise TiN so as to use an known material having predictable results and properties.
Claim(s) 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kashimoto, as applied to claim 1, and in further view of Teo (US 2021/0305373).
As to claim 2, Kashimoto further teaches between steps b) and c), a step of forming an epitaxial third layer of a material selected from aluminum nitride, gallium nitride, indium nitride, and alloys of these materials, the third layer coating said face of the first layer ([0118], the layer need not be homogenous but can have a multi-layered structure).
Kashimoto teaches growing the second and third layers but does not teach the third layer is formed by pulsed laser ablation from a face of the first layer opposite the front face of the substrate.
However, Teo teaches forming a GaN device having a growth substrate upon which a buffer layer and a III-N layer are formed, all of which are grown using “any growth method using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), pulsed laser deposition (PLD), Sputtering and so on.” ([0047]).
That is, these growth methods are known equivalents in the art to grow semiconductor layers. Thus, choosing PLD would have been obvious so as to use an industrially tested and accepted method of growing semiconductor layers.
As to claim 7, Kashimoto does not teach in step b), the first continuous layer is formed by pulsed laser ablation. However, Teo teaches forming a GaN device having a growth substrate upon which a buffer layer and a III-N layer are formed, all of which are grown using “any growth method using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), pulsed laser deposition (PLD), Sputtering and so on.” ([0047]).
That is, even the buffer layer (which is a layer “grown to tackle the lattice mismatch between the wafer material and the III-N semiconductor.” (Teo, [0045]) which is what the first layer of Kashimoto does) is known to be grown using one of these methods. Thus, choosing PLD would have been obvious so as to use an industrially tested and accepted method of growing a buffer layer.
Claim(s) 5, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer, as applied to claim 1 and 9, and in further view of Gardner (US 9209359).
As to claims 5 and 10, Meyer teaches the semiconductor structure (i.e. the substrate (1), the transition metal layer (2), and the GaN layer (3)) of the LED but is silent on the electrode formation. However, Gardner teaches forming an LED having a semiconductor structure 22 by forming a first conduction electrode (36) of the device, coating a face of said at least one second layer opposite the front face of the substrate, and a second conduction electrode (34) of the device, coating the rear face of the substrate (fig. 2, col. 5:56-67 and col. 6:1-14).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the electrodes on the top and bottom surfaces of the LED, as taught by Gardner, so as to fabricate an LED device in an industrially tested and accepted manner.
As to claim 11, Gardner further teaches the first and second electrodes are anode and cathode electrodes respectively, the device being of the diode type (col. 5:56-67 and col. 6:1-14, the electrodes are the p and n contacts).
Allowable Subject Matter
Claims 3, 4, 8, 12, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claims 3 and 4, Kashimoto and Meyer both fail to teach between steps a) and b), a step of etching the substrate; and between steps b) and c), a step of etching the first layer and the substrate. No etching of the substrate is taught by either reference.
As to claim 8, Neither Kashimoto nor Meyer teach between steps b) and c), a step of forming a selective growth mask. The entire surface of the transition metal layer is covered by the semiconductor layer, so there would be no reason for a growth mask.
As to claim 12, Neither Kashimoto nor Meyer teach the substrate comprises a first part, located in regard of the anode electrode, having a thickness greater than that of a second part of the substrate of annular shape surrounding the first part. The substrate is not etched or modified in any way that would result in this configuration.
As to claim 14, Neither Kashimoto nor Meyer teach a control electrode penetrating inside said at least one second layer, the device being of the transistor type.
As to claim 15, Neither Kashimoto nor Meyer teach the flanks of said at least one second layer are coated with a passivation layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
4/27/26
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