DETAILED ACTION
Claims 1-20 are pending in the case. Claims 1, 7, and 14 are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hervin et al. (US 6,138,230 A).
Regarding claim 1, Hervin teaches an apparatus (FIGS. 1a, 1b and Col. 4, lines 13-16: the processor system/apparatus is shown in FIGS. 1a and 1b, which respectively illustrate the basic functional blocks of the exemplary superscalar, superpipelined microprocessor along with the pipe stages of the two execution pipelines), comprising:
an instruction memory circuit configured to store a plurality of instructions (FIG. 1a and Col. 4, lines 25-36: A 256 byte instruction line cache 75/instruction memory circuit provides a primary instruction cache and allows a full line of 32 instruction bytes to be transferred/store a plurality of instructions to the instruction line cache in a single clock);
a plurality of execution circuits (FIG. 1a and Col. 4, lines 53-56: The CPU core 20 is a superscalar design with two execution pipes X and Y, including execution units 23X and 23Y/plurality of execution circuits);
and a program sequencer circuit (FIG. 1a and Col. 4, lines 59-60: the microcontrol unit 26 includes the microsequencer circuitry/program sequencer circuit, which provides execution control of the execution units 23X and 23Y; Col. 15, lines 44-45: the microsequencer circuitry 23/program sequencer circuit provides independent flows of microinstructions to the execution stages) configured to:
fetch the plurality of instructions from the instruction memory circuit in a program order (FIGS. 1a, 1b and Col. 5, lines 1-19: A pipe control unit 28 controls instruction flow through the execution pipes, keeping the instructions/plurality of instructions in program order until it is determined that an instruction will not cause an exception. The microprocessor has a seven-stage X and Y execution pipeline, including an instruction fetch IF stage, which provides a continuous code stream into the CPU core 20. The prefetcher 40 fetches 16 bytes of instruction data into the prefetch buffer 30 from either the (primary) instruction line cache 75/instruction memory circuit or the (secondary) unified cache 70.); and
issue, at a first time, a particular instruction of the plurality of instructions to a particular execution circuit of the plurality of execution circuits (FIG. 1a and Col. 5, lines 37-39: During the instruction decode stages, the optimum pipe for executing an instruction is determined, and the instruction/particular instruction is issued into that pipe/particular execution circuit.) in response to a determination that there are no hazards associated with the particular instruction (FIG. 1a and Col. 5, lines 1-4: The pipe control unit 28 controls instruction flow through execution pipes keeping the instructions in program order until it is determined that the instruction will not cause an exception/no hazard associated; FIG. 1b and Col. 9, lines 6-14: a pipe stage generates an “exception’ the instruction cannot complete due to an error condition and should not transfer beyond the current stage, which can occur in the IF (instruction fetch) stage, the ID1 and ID2 (instruction decode) stages, or the AC1 and AC2 (address calculation) stages for all instructions; Col. 11, line 57 – Col. 12, line 10: Once an instruction passes/is issued from an address control (AC2) stage to an execution (EX) stage, it can complete its execution out-of-order, unless there is a resource or a data dependency which prevents it. One example is a read-after-write (RAW) dependency/hazard which would prevent an instruction from completing its EX stage until the dependency is cleared. Thus, an instruction such as ADD AX,BX cannot complete its EX stage until execution of a previous ADD BX,CX is completed, since the value of operand BX is dependent upon the previous instruction. However, junior instructions that are issued to the EX stage without dependencies on a senior instruction may complete, and therefore it is possible for many instructions to pass a senior instruction which requires multiple clock periods in the opposite EX stage.; Col. 16, lines 27-31: data dependencies/hazards can arise from a RAW hazard as well as a WAR (write-after-read) hazard, and a WAW (write-after write) hazard.);
issue, at a second time prior to the first time, a different instruction of the plurality of instructions to a different execution circuit of the plurality of execution circuits (issuing instructions into the two pipelines “substantially simultaneously” and the environment in which a “different” (junior) instruction may be issued earlier into the other pipe; issuance without regard to dependencies; issuance into X/Y pipelines — col. 4–5, col. 31–33, col. 62–63, col. 131–134. See also discussion of issuing and pipe switching (col. 41–44; col. 84–92)); and
wherein the particular execution circuit is configured to complete the particular instruction prior to a completion of the different instruction (FIG. 1b and Col. 6, lines 25-30: The execution stages EXx (in the X Pipe) and Exy (in the Y Pipe) of execution units 23X and 23Y/plurality of execution circuits, respectively, perform the operations defined by the instruction. Instructions spend a variable number of clocks in EX, i.e., they are allowed to execute out of order (out of order completion) based on dependencies.; FIG. 1b and Col. 11, line 55 - Col. 12, line 12: An instruction is considered “passed”/issued to the EX (execution) stage once execution begins on the instruction (i.e., completion of the instruction). Once an instruction passes/is issued from an AC2 (address calculation) stage to an EX stage, it can complete its execution out-of-order. Junior instructions/the particular instruction which pass/are issued to the EX (execution stage)/of the particular execution circuit without dependencies on a senior instruction/different instruction of the plurality of instructions may complete first. It is possible for many junior instructions to pass/be issued prior to a senior instruction/different instruction of the plurality of instructions which requires multiple clock periods in the opposite EX (execution) stage/a different execution circuit of the plurality of execution circuits to clear the dependency. In this situation, one or more junior instructions without dependencies can be issued, completed (executed) and continue on to the write back stage before a senior instruction is issued.; FIG. 5 and Col. 13, lines 16-20: In block 200, the pipe control determines whether an instruction can cause an exception at its present stage (or beyond). If not, in block 202, the instruction is allowed to complete ahead of senior instructions/different instruction of the plurality of instructions.
Regarding claim 2, Hervin further teaches the apparatus of claim 1, further comprising a plurality of register circuits corresponding to the plurality of execution circuits (FIG. 1a and Col. 4, lines 55-56: CPU core 20 is a superscalar design with two execution pipes X and Y including execution units 23X and 23Y/plurality of execution circuits, and a register file 24 with 32 32-bit registers/plurality of register circuits) and,
wherein to complete the particular instruction, the particular execution circuit is further configured to write a result generated by executing the particular instruction to a particular register circuit of the plurality of register circuits corresponding to the particular execution circuit (FIG. 1b and Col. 5, line 10 - Col. 6, line 33: In the microprocessors seven-stage X and Y execution pipelines of the execution units 23X and 23Y/execution circuits, respectively, there is a write back stage (WB). Here the execution unit/particular execution circuit updates/writes to the register file 24, condition codes, and other parts of the machine state with the results of the previously executed instruction/a result generated by executing the particular instruction to a particular register circuit.; FIG. 10 and Col. 17, lines 32-36: For each instruction/particular instruction which writes (via the particular execution circuit during the write back stage) results to a logical register/particular register circuit, a new physical register is allocated by the register translation unit 25a. The register allocation process first identifies a “free” physical register, namely one that is not in use.; Col. 16, line 37 - Col. 17, line 3: A new physical register is assigned each time a logical register is to be written (destination of result). There are 32 physical registers which will be used to map the eight general purpose registers (logical registers). For each AC1 (address calculation) pipe stage (which corresponds to a particular execution circuit 23X or 23Y), up to 2 new logical registers are allocated/correspond as destinations of the current instructions in the AC pipe stage/particular register circuit.
Regarding claim 3, Hervin further teaches the apparatus of claim 1, wherein the program sequencer circuit is further configured to delay issuing a given instruction of the plurality of instructions in response to a determination that the given instruction has at least one associated hazard (Col. 5, lines 1-9: A pipe control unit 28 controls instruction flow through the execution pipes, and for each stage (seven-stage execution pipeline) keeps track of which execution pipe contains the earliest instruction, and provides a stall output and receives a delay input.; FIGS. 1a, 3 and Col. 7, line 38 - 40: the flow of instructions through the pipeline, controlled by the pipe control unit (or pipe controller) 28, operates on an instruction through the following stages: instruction decode stages ID1 and ID2, address calculation stages AC1 and AC2, execution EX, and write-back WB. Each stage has a corresponding unit in the CPU core 20. The ID1 and ID2 stages correspond to the instruction decoder unit 21, which is connected to the AC control unit 25 (AC1 and AC2 stages). The AC control unit is connected to the microcontrol unit 26, which is comprised of mircosequencer circuity 23/ program sequencer circuity. The pipe control unit 28 receives “delay” signals from the various units comprising the pipelines 102 and 104, and issues “stall” signals to the various units (instruction decoder, AC control and microcontrol) to control the flow of instructions through the pipes X and Y; Col. 11, line 55 – Col. 12, line 12: Once an instruction passes from an AC2 (address calculation) stage to an EX (execution) stage, it can complete its execution, unless there is a resource or a data dependency/one associated hazard, such as a, a read-after-write (RAW), which prevents the instruction/a given instruction from executing out-of-order.)
Regarding claim 4, Hervin further teaches the apparatus of claim 3, wherein the at least one associated hazard includes a read-after-write hazard (Col. 11, line 55 – Col. 12, line 12: a read-after-write (RAW) dependency/hazard would prevent an instruction from completing its EX (execution) stage until the dependency is cleared).
Regarding claim 5, Hervin further teaches the apparatus of claim 1, wherein the particular execution circuit includes a plurality of execution sub-circuits, (FIG. 1a and Col. 4, lines 53-56: The CPU core 20 is a superscalar design with two execution pipes X and Y/plurality of execution circuits, including execution units 23X and 23Y/plurality of execution sub-circuits)
wherein to issue the particular instruction, the program sequencer circuit is further configured to issue the particular instruction to a first execution sub-circuit of the plurality of execution sub-circuits and wherein the program sequencer circuit is further configured to issue a given instruction of the plurality of instructions to a second execution sub-circuit of the plurality of executions sub-circuits prior to issuing the particular instruction (Col. 5, lines 27-38: During the instruction decode stages ID1 and ID2, the optimum pipe for executing an instruction is determined, and the instruction is issued into that pipe. In ID1, the length of two instructions is decoded, one instruction/a given instruction for the X execution pipe/second execution sub-circuit and the other instruction/the particular instruction for the Y execution pipe/first execution sub-circuit, to obtain the X and Y instruction pointer; FIG. 1b and Col. 11, line 55 - Col. 12, line 12: An instruction is considered “passed”/issued to the EX (execution) stage once execution begins the completion of the instruction. Once an instruction is issued from an AC2 (address calculation) stage to an EX stage on either the X execution pipe or Y execution pipe/execution sub-circuits, it can complete its execution out-of-order. A junior instruction/the particular instruction is issued to the EX stage of a Y execution pipe/first execution sub-circuit without dependencies on a senior instruction/a given instruction issued to a X execution pipe/second execution sub-circuit may complete. It is possible for many instructions to pass/be issued prior to a senior instruction which requires multiple clock periods in the opposite EX stage of a different execution pipe/a second execution sub-circuit. In this case, the junior instruction can be issued, completed (executed) and continue on to the write back stage before the senior instruction is issued.), and
wherein the second execution sub-circuit is configured to complete the given instruction prior to a completion of the particular instruction (FIG. 6a and Col. 13, line 66 - Col. 14, line 12: At time T1 (senior) instruction I1/a given instruction is in EXx/a second execution sub-circuit, (junior) instruction I2/the particular instruction is in EXy/a first execution sub-circuit, where I2 has a read-after-write dependency on I1 and therefore for instruction I2 to be properly processed in the EXy stage and completed, it must wait for the outcome of instruction I1 in the EXX stage/the given instruction completes prior to the completion of the particular instruction.).
Regarding claim 6, Hervin further teaches the apparatus of claim 1, wherein to issue the particular instruction, the program sequencer circuit is further configured to: perform a decode operation on the particular instruction (Col. 5, lines 10-29: the microprocessor has seven-stage X and Y execution pipelines including two instruction decode stages ID1 and ID2. The decode stages ID1 and ID2 decode the variable length X86 instruction set. In ID1, the length of two instructions is decoded one instruction/the particular instruction for each of the X and Y execution pipes to obtain the X and Y instruction pointer.); and
select the particular execution circuit from the plurality of execution circuits using a result of the decode operation (Col. 5, lines 31-39: In ID1, certain instruction types are determined and immediate and/or displacement operands are separated and in the ID2 stage, the decoding of the X and Y instructions is completed, generating entry points for the microROM and decoding addressing modes and register fields. During the ID stages, the optimum pipe for executing an instruction is determined/using a result of the decode operation, and the instruction is issued into that pipe/the particular execution circuit from the plurality of execution circuits.).
Regarding claims 7-13, Hervin further teaches a method (FIG. 1b and Col. 5, line 10: the method comprises of FIG. 1a showing the steps of the seven-stage instruction pipeline unit; See also FIG. 5 and Col. 13, lines 11-12: the operation of the pipe control unit; See also FIG. 8 and Col. 15, lines 1-3: operation of the pipe control unit with regard to pipe switching), comprising: steps with corresponding limitations to the apparatus of claims 1, 2, 5, 5, 3, 4 and 6, respectively, achieved by a processor circuit (Col. 4, lines 13-19: processor system shown illustrates the basic functional blocks of the exemplary superscalar, superpipelined microprocessor along with the pipe stages of the two execution pipelines and the processor system (motherboard) design using the microprocessor).
Therefore, claims 7-13 with steps with corresponding limitations to the apparatus of claims 1, 2, 5, 5, 3, 4 and 6, respectively, are rejected on the same premises.
Regarding claims 14-20, Hervin further teaches an apparatus (FIGS. 1a, 1b and Col. 4, lines 13-16: the processor system/apparatus is shown in FIGS. 1a and 1b, which respectively illustrate the basic functional blocks of the exemplary superscalar, superpipelined microprocessor along with the pipe stages of the two execution pipelines), comprising:
a memory circuit configured to store a plurality of instructions (FIG. 1a and Col. 4, lines 25-36: A 256 byte instruction line cache 75/instruction memory circuit provides a primary instruction cache and allows a full line of 32 instruction bytes to be transferred/store a plurality of instructions to the instruction line cache in a single clock);
and a plurality of processor cores including a particular processor core configured to: (FIG. 1a and Col. 4, lines 21-22: the major sub-blocks of a microprocessor 10, of the processor system, include CPU core 20/a particular processor core) perform operations with corresponding limitations to the apparatus of claim 1, 2, 5, 5, 3, 4 and 6, respectively.
Therefore, claims 14-20 with steps with corresponding limitations to the apparatus of claims 1, 2, 5, 5, 3, 4 and 6, respectively, are rejected on the same premises.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181