DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 04/27/2026, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Claim Objections
Claim 16 objected to because of the following informalities:
“the first trench separates from” should read “the first trench is separate from” line 2
. Appropriate correction is required.
Claim Interpretation
“width” = dimension in x-direction, “length” = dimension in y-direction in instant application fig. 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6, 9, 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claim 6 line 2, claim 9 line 2, claim 20 line 3 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Third depth (claim 6), fifth depth (claim 9), first step height (claim 20) rendered indefinite by use of term. Examiner interprets “substantially the same” to mean within 100%.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-15, 18, 20 is/are rejected under 35 U.S.C. 102a1/2 as being anticipated by Ikeda (US-20200021083-A1).
Regarding claim 1, Ikeda discloses a semiconductor device, comprising: a substrate comprising a first upper region (fig. 1b + annotated fig. 3 substrate 100+211 comprises first upper region 1UR (top surface of substrate within right half of 114a2 triangle), 0141, 0175), a second upper region a third upper region and a fourth upper region (2UR (portion within groove 111), 3UR (top surface of substrate within right half of triangle (the region equal to and directly opposite 1UR)), 4UR); and a stack structure locating on the fourth upper region of the substrate without overlapping the first upper region, the second upper region and the third upper region (stack structure 212+220+230 located on 4UR without overlapping 1UR, 0119-0122), wherein the stack structure comprises a first end face (stack comprises first end face FEF (front surface of 201 parallel to page)), a top surface (top of 230 in fig. 1b), a first semiconductor layer (212), an active region (220), and a second semiconductor layer comprising a ridge structure (230 comprises ridge structure 201); wherein the first upper region is closer to the first end face than the second upper region is (1UR closer to FEF than 2UR is), and the semiconductor device comprises a first depth between the top surface and the first upper region (first depth between top of 230 and top of 1UR line (shallowest point of 1UR)), and a second depth between the top surface and the second upper region smaller than the first depth (second depth between top of 230 and 2UR smaller than first depth, second depth at same level as 123 in fig. 3).
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Annotated fig. 3
Regarding claim 5, Ikeda discloses the semiconductor device as claimed in claim 1, wherein the second upper region is closer to the first end face than the third upper region is (2UR closer to FEF than 3UR is), and the semiconductor device comprises a third depth between the top surface and the third upper region larger than the second depth (third depth (same as first depth) larger than second depth).
Regarding claim 6, Ikeda discloses the semiconductor device as claimed in claim 5, wherein the third depth is substantially the same as the first depth (third depth equal to first depth, identical regions).
Regarding claim 7, Ikeda discloses the semiconductor device as claimed in claim 1, wherein the substrate further comprises a fifth upper region closer to the first end face than the second upper region (5UR (surface of substrate within bounded line) closer to FEF than 2UR), and the semiconductor device comprises a fourth depth between the top surface and the fifth upper region larger than the second depth (fourth depth between 230 and 5UR (shallowest point) larger than second depth).
Regarding claim 8, Ikeda discloses the semiconductor device as claimed in claim 5, wherein the substrate further comprises a sixth upper region closer to the ridge structure than the third upper region (6UR (surface of substrate within 121 region) closer to ridge structure 201 than 3UR), and the semiconductor device comprises a fifth depth between the top surface and the sixth upper region, and the fifth depth is smaller than third depth (fifth depth between top of 230 and 6UR, fifth depth smaller than third depth).
Regarding claim 9, Ikeda discloses the semiconductor device as claimed in claim 8, wherein the fifth depth is substantially the same as the second depth (112 groove depth (i.e. 6UR/fifth depth) equal to 111 groove depth (i.e. 2UR/second depth), 0130).
Regarding claim 10, Ikeda discloses the semiconductor device as claimed in claim 1, wherein the substrate further comprises a first trench exposing the first upper region (substrate comprises first trench 1TR (left and right align with 1UR, 1TR extends down to surface of substrate), 0190-0192), and the first trench comprises a first trench width and a first trench length (1TR width (x dimension) and 1TR length (y dimension)).
Regarding claim 11, Ikeda discloses the semiconductor device as claimed in claim 10, wherein the substrate further comprises a second trench exposing the second upper region (substrate (211 portion) comprises second trench 111+123(120) exposing 2UR, 0128-0130), and the second trench comprises a second trench width narrower than the first trench width (111+123(120) x-dimension less than 1TR x-dimension (at 111 portion of second trench))), and a second trench length larger than the first trench length (111+123(120) y dimension greater than 1TR y dimension).
Regarding claim 12, Ikeda discloses the semiconductor device as claimed in claim 11, wherein the substrate further comprises a third trench parallel to the second trench (100+211 comprises third trench 3TR (113b2 portion) parallel to 111+123(120) portion of 2UR, 0188-0189), and the third trench comprises a third trench width narrower than the second trench width (3TR comprises third width (x direction) at minimum tapered point (fig. 5b) narrower than 111+123(120) x-dimension at 111 portion, 0201), and a third trench length smaller than the second trench length (3TR length y-dimension smaller than 111+123(120) portion of 2UR).
Regarding claim 13, Ikeda discloses the semiconductor device as claimed in claim 10, wherein the substrate comprises an outer short-side surface (substrate comprises outer short-side surface 110c), an outer long-side surface and a corner between the outer short-side surface and the outer long-side surface, wherein the first trench locates at the corner (outer long-side surface 110b with corner between outer 110c and 110b, with 1TR located at corner).
Regarding claim 14, Ikeda discloses the semiconductor device as claimed in claim 12, wherein the second trench is closer to the ridge structure than the third trench is (2UR trench closer to 201 than 3TR is).
Regarding claim 15, Ikeda discloses the semiconductor device as claimed in claim 11, wherein the first trench connects to the second trench (1TR physically connects to 111+123(120)).
Regarding claim 18, Ikeda discloses the semiconductor device as claimed in claim 12, wherein the third trench width is between 3μm and 7μm.
Ikeda discloses 113 width of 3-8 um (fig. 2j, 0169). Third trench width 113b2 ~half of this (1.5-4 um) after splitting. 3-4 um portion between 3-8 um.
Regarding claim 20, Ikeda discloses the semiconductor device as claimed in claim 10, wherein the first trench comprises a first part, a second part and a first step height between the first part and the second part (1TR comprises first part FP, second part SP, first step height FSH between FP and SP, 0191), and wherein the first step height is substantially the same as the second depth (FSH substantially same as 111+123(120) depth, annotated fig. Z shows example FP, SP, FSH; clearly, an FP and SP combination can be found within 1TR that satisfies FSH = second depth).
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Annotated fig. Z w/ example FP, SP, FSH
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in view of Shigihara (US-20050121682-A1).
Regarding claim 2, Ikeda discloses the semiconductor device as claimed in claim 1.
Ikeda does not disclose wherein the semiconductor device comprises a device width between 130 μm and 260 μm.
Shigihara discloses a semiconductor light emitting device with a device width of 200 um (fig. 3, 0066).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a device width between 130 μm and 260 μm (200 um) to balance cost/footprint benefits (smaller) and improved mounting/thermal dissipation benefits (larger).
Regarding claim 3, Ikeda discloses the semiconductor device as claimed in claim 1.
Ikeda does not disclose wherein the semiconductor device comprises a device length between 840 μm and 1560 μm.
Shigihara discloses a semiconductor laser device with a device length of 1000 um (fig. 3, 0066).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a device length between 840 μm and 1560 μm (1000 um) to balance cost/footprint benefits (smaller) and improved mounting/thermal dissipation benefits (larger).
Regarding claim 17, Ikeda discloses the semiconductor device as claimed in claim 11, wherein the second trench length is roughly equal to the overall device length (111+123(120) y dimension roughly equal to overall y dimension), and the second trench width is between 5μm and 15μm (fig. 2J 113 is 3-8 um wide, 111 width roughly equal (5-8 um within 5-15 um), 0169).
Ikeda does not disclose the second trench length is between 840μm and 1560μm.
Shigihara discloses a semiconductor laser device with a device length of 1000 um (fig. 3, 0066).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a device length between 840 μm and 1560 μm (1000 um), while maintaining second trench length rough equality, to balance cost/footprint benefits (smaller) and improved mounting/thermal dissipation benefits (larger).
Second trench length roughly 1000 um after modification, satisfying claim 17.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in view of Itoh (US-20050058170-A1).
Regarding claim 4, Ikeda discloses the semiconductor device as claimed in claim 1.
Ikeda does not disclose wherein the semiconductor device comprises a device height between 70 μm and 120 μm.
Itoh discloses a semiconductor laser element with a device height of 100-110 um (fig. 1, 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a device height between 70 μm and 120 μm to balance thermal dissipation benefits (thinner) and durability (thicker).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in view of Nagao (US-20200076165-A1).
Regarding claim 19, Ikeda discloses the semiconductor device as claimed in claim 1.
Ikeda does not disclose wherein the ridge structure comprises a ridge width between 35μm and 65μm.
Nagao discloses a semiconductor laser element with a ridge width of 45 um (fig. 1 ridge 4a, 0016, 0047-0069).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the ridge structure comprises a ridge width between 35μm and 65μm (45 um) to balance reduced current density/heating (thinner) and durability (thicker).
Allowable Subject Matter
Claim 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 16: Prior art of record does not disclose trench relationships described in claim 16 in conjunction with limitations from previous claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fukuda US-20130001588-A1
Sato US-11283233-B2
Kawakami JP-2003017791-A
.
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/A.E./Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
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