Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 12/26/25 in response to the Office action dated 9/3/25. Claims 1 and 16 have been amended. Claim 11 has been cancelled. Claims 1-6, 10, 12-14, and 16-18 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, 12, and 16-18 are rejected under 35 U.S.C 103 as being unpatentable over Hashimoto (US 20170262178 A1) in view of Hashimoto (US 20160321010 A1), further in view of Kim et al. (US 20170031626 A1), hereinafter Kim (‘626).
Regarding claim 1, Hashimoto (‘178) teaches a storage device comprising: at least one memory including a plurality of storage blocks (Paragraph 88; Fig. 11, flash memory 16 including block pools 420, 430, and 440);
and a memory controller configured to control an operation of the at least one memory (Paragraph 98; Figs. 1 and 13, controller 14 writes data to flash memory 16)
and to receive a command based on a zone, from among a plurality of zones, that corresponds to a storage block from among the plurality of storage blocks (Paragraphs 103 and 119; Figs. 15 and 16, step 1614, controller 14 writes data to a certain input block pool 420 [zone] and remaps the block to the corresponding active block pool 430 [storage blocks]),
the command including at least one of cell type information and usage frequency information (Paragraph 103, write command includes bit density [cell type information]),
wherein the memory controller sets, according to the cell type information, a cell type of memory cells that are included in the storage block corresponding to the zone (Paragraph 103; Fig. 15, controller 14 uses input block 42 [storage block] from an input block pool 420 [zone] with a bit density [cell type] corresponding to the write command data), and
performs an operation on the storage block according to the command (Paragraphs 107-112; Fig. 16, steps 1603-1608, controller 14 receives a write command and performs an operation to write data to an appropriate input storage block 42),
and the cell type indicates whether the memory cells are first level cells or second level cells, wherein a number of bits stored in the second level cells is greater than a number of bits stored in the first level cells (Paragraph 103, bit density information can specify single-level cells (SLC) [first level] or multi-level cells (MLC) [second level], wherein MLC includes two bits per cell which is greater than SLC which includes one bit per cell).
Hashimoto (‘178) does not explicitly teach a plurality of zones configured by a host device, wherein the cell type information of the zone is configured by the host device, wherein the memory controller is configured to receive an open zone command including the cell type information without data to be written, and to subsequently receive a write command with data to be written without the cell type information, wherein the memory controller is configured to write the data according to the write command in the storage block that corresponds to the zone according to the open zone command and that has a cell type indicated by the cell type information, and wherein when the memory controller receives a write command with a cell type information different from the cell type information included in the open zone command, the memory controller is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command.
However, Hashimoto (‘010) teaches a plurality of zones configured by a host device (Paragraph 98; Fig. 10B, host 3 configures the physical block group for each stream [zone]),
wherein the cell type information of the zone is configured by the host device (Paragraphs 116-117, 121; Fig. 13A, steps 1201 and 1205, host 3 opens [configures] a new stream [zone] and specifies an MLC, SLC, TLC, or QLC [cell type] mode for the input block 42 of the new stream),
wherein the memory controller is configured to receive an open zone command including the cell type information without data to be written (Paragraphs 116-124; Fig. 13A, steps 1201-1208, controller 14 receives an open stream [zone] command that specifies an MLC, SLC, TLC, or QLC [cell type] mode and does not include write data),
and to subsequently receive a write command with data to be written without the cell type information (Paragraphs 126, 128-129, Fig. 13B, steps 1302-1303, controller 14 receives a write command including a UCID (which points to write data) and not including cell type information),
and wherein the memory controller is configured to write the data according to the write command in the storage block that corresponds to the zone according to the open zone command and that has a cell type indicated by the cell type information (Paragraphs 121, 131, 134; Figs. 13A and 13B, steps 1205, 1305, and 1308, controller 14 writes the data from the write command to an input block 42 within the stream [zone] from the open stream [zone] command which specified an MLC, SLC, TLC, or QLC [cell type] mode).
Hashimoto (‘178) and Hashimoto (‘010) are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) to further include the host-configurable zones and the open zone command according to the teachings of Hashimoto (‘010). The motivation for doing so would have been to increase access performance by enabling parallel write operations through the configuration of the streams/zones (Hashimoto (‘010), Paragraphs 98, 101, 135).
Hashimoto (‘178) and Hashimoto (‘010) does not explicitly teach wherein when the memory controller receives a write command with a cell type information different from the cell type information included in the open zone command, the memory controller is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command.
However, Kim (‘626) teaches wherein when the memory controller receives a write command with a cell type information different from the cell type information included in the open zone command (Paragraphs 47, 49, 54-55, 80; Figs. 3 and 4, page buffer 124 (controlled by control logic and voltage generating circuit 123 [controller]) receives a buffer program operation targeting an SLC buffer region BR [open zone command with SLC type] and a direct program operation targeting a TLC main region MR [write command with TLC type]),
the memory controller is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command (Paragraphs 45, 49, 54-55, 80; Figs. 3 and 4, after a direct program operation into TLC main region MR, page buffer 124 performs a migration program operation to migrate data from the blocks of SLC buffer region BR [zone according to the open zone command] to the blocks of TLC main region MR [cell type indicated by write command]).
Hashimoto (‘178), Hashimoto (‘010), and Kim (‘626) are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010) to further include the migration operation according to the teachings of Kim (‘626). The motivation for doing so would have been to increase the lifespan of the memory device (Kim (‘626), Paragraph 57).
Regarding claim 2, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 1, wherein the cell type information is information indicating a cell type of memory cells in the storage block corresponding to the zone (Hashimoto (‘178), Paragraph 103; Fig. 15, controller 14 uses input block 42 [storage block] from an input block pool 420 [zone] with a bit density [cell type] corresponding to the write command data).
Regarding claim 3, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 1, wherein the cell type information is information indicating a single-level cell type or a non-single-level cell type (Hashimoto (‘178), Paragraph 103, write command includes bit density information, which indicates writing to SLC [single-level cell type] or MLC/TLC [non-single-level cell type).
Regarding claim 10, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 1, wherein the memory controller receives a write command based on the zone corresponding to the storage block with memory cells of a single-level cell type (Hashimoto (‘178), Paragraph 103; Fig. 15, controller 14 writes to input block pool 420 with single level cells (SLC)),
and the write command includes cell type information indicating a different cell type from the single-level cell type (Hashimoto (‘178), Paragraph 103; Fig. 15, write command includes bit density BD=2, indicating to write data to multi-level cells (MLC)).
Regarding claim 12, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device of claim 1, wherein the memory controller selects the storage block corresponding to the zone based on usage frequency information for each of the plurality of zones (Hashimoto (‘178), Paragraphs 93 and 96; Fig. 12, controller 14 selects a free block 42 with the lowest erase count [usage frequency] from free block pool 440 [zone], where erase count [usage frequency] is tracked for every block pool [zone] in block mapping table (BMT) 46)
and accumulated usage information for each of the plurality of storage blocks (Hashimoto (‘178), Paragraph 93; Fig. 12, erase count [accumulated usage information] is tracked for every block in BMT 46).
Regarding claim 16, Hashimoto (‘178) teaches a computing system comprising: a storage device including at least one memory (Paragraph 48; Fig. 1, storage device 2 includes flash memory 16); and
a host device configured to transfer, to the storage device, a command based on a zone (Paragraph 103; Figs. 1 and 15, host 3 sends a write command to storage controller 14 specifying a particular input block pool 420 [zone]),
set to correspond to a storage block, among a plurality of storage blocks that are included in the at least one memory (Paragraph 103; Figs. 1 and 15, write command writes data to an input [storage] block 42 of the particular input block pool 420 [zone/plurality of storage blocks] within storage device 2),
the command including at least one of cell type information and usage frequency information (Paragraph 103, write command includes bit density [cell type information]),
the storage device sets, according to the cell type information, a cell type of memory cells that are included in the storage block corresponding to the zone (Paragraph 103; Fig. 15, controller 14 uses input block 42 [storage block] from an input block pool 420 [zone] with a bit density [cell type] corresponding to the write command data), and
performs an operation on the storage block according to the command (Paragraphs 107-112; Fig. 16, steps 1603-1608, controller 14 receives a write command and performs an operation to write data to an appropriate input storage block 42), and
the cell type indicates whether the memory cells are first level cells or second level cells, wherein a number of bits stored in the second level cells is greater than a number of bits stored in the first level cells (Paragraph 103, bit density information can specify single-level cells (SLC) [first level] or multi-level cells (MLC) [second level], wherein MLC includes two bits per cell which is greater than SLC which includes one bit per cell).
Hashimoto (‘178) does not explicitly teach a plurality of zones which are configured by the host device, wherein, the cell type information of the zone is configured by the host device, wherein the storage device receives an open zone command including the cell type information without data to be written from the host device, subsequently receives a write command with data to be written without the cell type information from the host device, wherein the storage device writes the data according to the write command in the storage block that corresponds to the zone according to the open zone command and that has a cell type indicated by the cell type information, and wherein when the storage device receives a write command with a cell type information different from the cell type information included in the open zone command, the storage device is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command.
However, Hashimoto (‘010) teaches a plurality of zones which are configured by the host device (Paragraph 98; Fig. 10B, host 3 configures the physical block group for each stream [zone]),
wherein, the cell type information of the zone is configured by the host device (Paragraphs 116-117, 121; Fig. 13A, steps 1201 and 1205, host 3 opens [configures] a new stream [zone] and specifies an MLC, SLC, TLC, or QLC [cell type] mode for the input block 42 of the new stream),
wherein the storage device receives an open zone command including the cell type information without data to be written from the host device (Paragraphs 116-124; Figs. 1 and 13A, steps 1201-1208, controller 14 of storage device 2 receives an open stream [zone] command from OML 12 of host 3 that specifies an MLC, SLC, TLC, or QLC [cell type] mode and does not include write data),
subsequently receives a write command with data to be written without the cell type information from the host device (Paragraphs 126, 128-129, Figs. 1 and 13B, steps 1302-1303, controller 14 of storage device 2 receives a write command from OML 12 of host 3 including a UCID (which points to write data) and not including cell type information), and
wherein the storage device writes the data according to the write command in the storage block that corresponds to the zone according to the open zone command and that has a cell type indicated by the cell type information (Paragraphs 121, 131, 134; Figs. 13A and 13B, steps 1205, 1305, and 1308, controller 14 of storage device 2 writes the data from the write command to an input block 42 within the stream [zone] from the open stream [zone] command which specified an MLC, SLC, TLC, or QLC [cell type] mode).
Hashimoto (‘178) and Hashimoto (‘010) are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) to further include the host-configurable zones and the open zone command according to the teachings of Hashimoto (‘010). The motivation for doing so would have been to increase access performance by enabling parallel write operations through the configuration of the streams/zones (Hashimoto (‘010), Paragraphs 98, 101, 135).
Hashimoto (‘178) in view of Hashimoto (‘010) does not explicitly teach wherein when the storage device receives a write command with a cell type information different from the cell type information included in the open zone command, the storage device is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command.
However, Kim (‘626) teaches wherein when the storage device receives a write command with a cell type information different from the cell type information included in the open zone command (Paragraphs 49, 54-55, 80; Figs. 3 and 4, page buffer 124 of nonvolatile memory device 120 receives a buffer program operation targeting an SLC buffer region BR [open zone command with SLC type] and a direct program operation targeting a TLC main region MR [write command with TLC type]),
the storage device is configured to migrate the data written in the storage block that corresponds to the zone according to the open zone command to a different storage block that has a cell type indicated by the cell type information included in the write command (Paragraphs 45, 49, 54-55, 80; Figs. 3 and 4, after a direct program operation into TLC main region MR, page buffer 124 performs a migration program operation to migrate data from the blocks of SLC buffer region BR [zone according to the open zone command] to the blocks of TLC main region MR [cell type indicated by write command]).
Hashimoto (‘178), Hashimoto (‘010), and Kim (‘626) are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the computing system of Hashimoto (‘178) in view of Hashimoto (‘010) to further include the migration operation according to the teachings of Kim (‘626). The motivation for doing so would have been to increase the lifespan of the memory device (Kim (‘626), Paragraph 57).
Regarding claim 17, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the computing system according to claim 16, wherein the host device transfers, to the storage device, at least one of an open zone command (Hashimoto (‘101), Paragraphs 116-118; Figs. 1 and 13A, steps 1201-1202, host 3 sends an open stream [zone] command to controller 14 of storage device 2)
and a write command including the cell type information (Hashimoto (‘178), Paragraph 103; Fig. 15, host 3 transfers a write command including bit density [cell type] information to storage controller 14).
Regarding claim 18, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the computing system according to claim 17, wherein the host device transfers the open zone command including the cell type information to the storage device (Hashimoto (‘010), Paragraphs 116-124; Figs. 1 and 13A, steps 1201-1208, OML 12 of host 3 transfers an open stream [zone] command that specifies an MLC, SLC, TLC, or QLC [cell type] mode to controller 14 of storage device 2), and then
transfers a first write command without the cell type information to the storage device (Hashimoto (‘010), Paragraphs 126, 128-129, Figs. 1 and 13B, steps 1302-1303, OML 12 of host 3 transfers a write command including a UCID (which points to write data) and not including cell type information to controller 14 of storage device 2) and
after transferring the first write command to the storage device, the host device transfers a second write command including the cell type information to the storage device, and the cell type information included in the second write command is different from the cell type information included in the open zone command (Hashimoto (‘178), Paragraph 103; Fig. 15, host 3 transfers to storage controller 14 a write command including bit density [cell type] information, which differs from the open zone command cell type information by not including a QLC cell type).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) as applied to claim 1 above, and further in view of Kanteti (US 20220244869 A1).
Regarding claim 4, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 1, but does not explicitly teach wherein the usage frequency information is a frequency of access to data written to the zone.
However, Kanteti teaches wherein the usage frequency information is a frequency of access to data written to the zone (Paragraph 62, file system data 224 of write requests 342 include frequency of modification [access]).
Hashimoto (‘178), Hashimoto (‘010), Kim (‘626), and Kanteti are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) to further include the frequency of access information according to the teachings of Kanteti. The motivation for doing so would have been to improve data classification and segregation, thereby reducing write amplification (Kanteti, Paragraphs 19 and 62).
Claims 5 and 6 are rejected under 35 U.S.C 103 as being unpatentable over Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) as applied to claim 1 above, and further in view of Yang et al. (US 20210223954 A1), hereinafter Yang.
Regarding claim 5, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 1, but does not explicitly teach wherein the command further includes a valid page count information.
However, Yang teaches wherein the command further includes a valid page count information (Paragraphs 7 and 56; Fig. 4, write operation involves receiving physical-characteristic data, which includes valid page count information).
Hashimoto (‘178), Hashimoto (‘010), Kim (‘626), and Yang are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) to further include the valid page count information according to the teachings of Yang. The motivation for doing so would have been to utilize memory characteristic information to maximize data storage performance (Yang, Paragraph 118).
Regarding claim 6, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 5, but does not explicitly teach wherein the usage frequency information changes depending on a number of changes in the valid page count information for the plurality of zones.
However, Yang teaches wherein the usage frequency information changes depending on a number of changes in the valid page count information for the plurality of zones (Paragraphs 7, 56, and 73; Fig. 4 physical characteristic data [usage frequency information] changes depending on the valid page count of LBA ranges [zones]).
Hashimoto (‘178), Hashimoto (‘010), Kim (‘626), and Yang are analogous art because they are in the same field of endeavor, that being writing data to particular memory blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) to further include the usage frequency information changing depending on the valid page count according to the teachings of Yang. The motivation for doing so would have been to utilize memory characteristic information to maximize data storage performance (Yang, Paragraph 118).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) as applied to claim 12 above, and further in view of Kim et al. (US 20210240390 A1).
Regarding claim 13, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 12, but does not explicitly teach wherein, when the usage frequency information of a zone is equal to or greater than a first threshold value, the memory controller selects, from among the plurality of storage blocks, the storage block whose accumulated usage information is smaller than a first reference value, to be set to correspond to the zone.
However, Kim et al. teaches wherein, when the usage frequency information of a zone is equal to or greater than a first threshold value, (Paragraph 186; Fig. 12, step 1240, when the max erase-write count [usage frequency] of the hot data pool [zone] is greater than the max erase-write count of the cold data pool [first threshold])
the memory controller selects, from among the plurality of storage blocks, the storage block whose accumulated usage information is smaller than a first reference value, to be set to correspond to the zone (Paragraphs 187; Fig. 12, step 1240, the memory block with the minimum [smaller than first reference value] erase-write count [accumulated usage] is exchanged from the cold data pool to the hot data pool [zone]).
Hashimoto (‘178), Hashimoto (‘010), Kim (‘626), and Kim et al. are analogous art because they are in the same field of endeavor, that being writing data to particular storage blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) to further include the corresponding of blocks to zones according to usage information according to the teachings of Kim et al. The motivation for doing so would have been to improve garbage collection and wear leveling performance (Kim et al., Paragraph 31).
Regarding claim 14, Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) teaches the storage device according to claim 12, but does not explicitly teach wherein, when the usage frequency information of a zone is smaller than a second threshold value, the memory controller selects, from among the plurality of storage blocks, the storage block whose accumulated usage information is equal to or greater than a second reference value, to be set to correspond to the zone.
However, Kim et al. teaches wherein, when the usage frequency information of a zone is smaller than a second threshold value, (Paragraph 186; Fig. 12, step 1240, when the max erase-write count [usage frequency] of the cold data pool [zone] is smaller than the max erase-write count of the hot data pool [second threshold])
the memory controller selects, from among the plurality of storage blocks, the storage block whose accumulated usage information is equal to or greater than a second reference value, to be set to correspond to the zone (Paragraph 187; Fig. 12, step 1240, the memory block with the maximum [greater than second reference value] erase-write count [accumulated usage] is exchanged from the hot data pool to the cold data pool [zone]).
Hashimoto (‘178), Hashimoto (‘010), Kim (‘626), and Kim et al. are analogous art because they are in the same field of endeavor, that being writing data to particular storage blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Hashimoto (‘178) in view of Hashimoto (‘010), further in view of Kim (‘626) to further include the corresponding of blocks to zones according to usage information according to the teachings of Kim et al. The motivation for doing so would have been to improve garbage collection and wear leveling performance (Kim et al., Paragraph 31).
Response to Arguments
Applicant’s arguments (see pages 6-9 of the remarks) filed 12/26/25, with respect to the rejections of claims 1-3, 10, 12, and 16-18 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim et al. (US 20170031626 A1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137