Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on March 17th, 2026. Claims 1-8, and 10-17 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, and 10-17 are rejected 35 U.S.C. 103 as being unpatentable over GANON et al. (US Pat No. 11687483 B1, hereinafter referred to as Ganon) in view of Kibardin et al. (USPGPUB No. 2023/0071424 A1, hereinafter referred to as Kibardin) and further in view of Yang et al. (USPGPUB No. 2024/0323657 A1, hereinafter referred to as Yang) and further in view of George et al. (US Pat No. 11886365 B2, hereinafter referred to as George) and further in view of Itani et al. (USPGPUB No. 2023/0048836 A1, hereinafter referred to as Itani).
Referring to claim 1, Ganon discloses a device {“system 100 includes a configurable integrated circuit 104 that has a controller 106.”, see Fig. 1, Col 9, lines 36-38}, comprising:
a first channel combination/separation unit {“multiple instantiations of each path to support multiple lanes”, see Fig. 1, Col 8, lines 44-48}, configured to receive first data of a source device {“An application or a device that uses an FPGA as a core controller”, see Fig. 1, Col 7, lines 5-9};
a data processing device {“can use a MIPI PHY interface (e.g., D-PHY and/or M-PHY) to interface with a MIPI device,”, see Fig. 1, Col 7, lines 5-7}, electrically connected to the first channel combination/separation unit {“signaling drive and receive paths are controlled [electrically connected]… can be driven or received by a native D-PHY IO”, see Fig. 1, Col 8, lines 4-9}, and configured to selectively perform at least one of an amplification/down-scale process {“defines the operation burst, the LS signaling (e.g. [pulse width modulation] PWM)”, see Fig. 1, Col 8, line 8}, a data bit number adjustment process {“based on the node (LS or HS)”, see Fig. 1, Col 8, lines 5-6. As HS or LS modes refer to as High Speed or Low Speed in a range of Gears “Each gear specifies a range of speeds (for LS) or a set of fixed [data bit number adjustment] bit rates (for HS). To date, five gears have been defined: Gear1, Gear2, Gear3, Gear4, and Gear5, where Gear5 is the fastest (highest [adjusted] bit-rate) gear. Even higher-speed gears may be defined in the future (e.g., Gear6 and above” (Col 1, lines 35-40)};
Ganon does not appear to explicitly disclose and maintain or change a first channel number corresponding to the first data to output second data;
a shifting process on the second data to generate third data;
wherein an execution sequence of the amplification/down-scale process, data bit number adjustment process and the shifting process and execution times of each of the amplification/down-scale process, data bit number adjustment process and the shifting process are determined by a control selection command; and
a second channel combination/separation unit, electrically connected to the data processing device, configured to receive the third data, and maintain or change a second channel number of the third data to output fourth data to a destination device.
However, Kibardin discloses and maintain or change a first channel number corresponding to the first data {“A color swap bit (↑↓) indicates color c messages”, see Fig. 62, [1214]} to output second data {“egressing port p have their color changed to (c XOR 1) on egress [as second data” per wavelet, see Fig. 62, [1214]};
a shifting process on the second data {“immediate 2534”, see Fig. 25c, [0812] last sentence} to generate third data {“left shift “Immediate 2534 is shifted one bit to the left and sign extended to form a [third data] 15-bit address”, see Fig. 25c [0812] last sentence};
wherein an execution sequence of the amplification/down-scale process {execution sequence “CE 800 performs Fetch/Decode Instruction with DSR(s) 2303”, see Fig. 24 [0770]}, data bit number adjustment process {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) that includes data bit number adjustment “initialized XDSRs and stride registers holding the stride values) are initialized by instructions that move data from memory to the DSRs” (see Fig. 23, [0762], 2nd sentence)} and the shifting process and execution times {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) with shifting and execution times as “the XDSRs and the stride registers are read entirely or partially in parallel, and in other embodiments and/or [execution] usage scenarios” (see Fig. 23, [0763] last sentence)} of each of the amplification/down-scale process {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) specifies amplification/downscale process “Other multidimensional tensor contractions… within this framework, as are convolutions, downsampling, and the other operations of neural network layer processing”, [1107] last sentence}, data bit number adjustment process and the shifting process {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) via “Normalizer 2913 normalizes Mantissa 2955 by detecting Leading Zeros 2955.1 and shifting Other Bits 2955.2 to the left” as instructed by DSR (see Fig. 29, 30C, and 30D, [0883], 4th sentence} are determined by a control selection command {“embodiment of an [control selection] immediate instruction”, see Fig. 25c [0810]};
and a second channel combination/separation unit {“routing is in accordance with a respective virtual channel specifier (e.g. a color”, [0107]}, electrically connected to the data processing device {data processing “a deep learning accelerator, such as a fabric of [processing elements] PEs”, see Figs. 4a and 4c [0820], 1st sentence}, configured to receive the third data {“every layer of neurons receives [plurality of data] activations during one or more forward passes, see Figs. 4a and 4c, [0823], 4th sentence}, and maintain or change a second channel number {“A color swap bit (↑↓) indicates color c messages”, see Fig. 62 [1214]} of the third data to output fourth data to a destination device {“train a neural network, and/or to perform inferences with respect to a trained neural network.”, see Fig. 4c [0820] 1st sentence}.
Ganon and Kibardin are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganon and Kibardin before him or her, to modify Ganon’s device incorporating Kibardin’s “CE 800” (see Fig. 8).
The suggestion/motivation for doing so would have been to implement and incorporate an array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data such that a respective compute element enabled to execute programmed instructions using the data and a respective router enabled to route the wavelets, said routers enables communication via the wavelets with at least nearest neighbor processing elements in a 2D mesh in turn advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency (Kibardin [0107]).
Therefore, it would have been obvious to combine Kibardin with Ganon to obtain the invention as specified in the instant claim(s).
However, neither Ganon or Kibardin appears to explicitly disclose applying to an audio direct memory access.
Furthermore, Yang discloses applying to an audio direct memory access {“RDMA”, “iSER", [0414], “RoCEv2”, ([0416], see Fig. 19), DMA transfers that can include audio “the ITS-S include the relevant users at that level, the relevant HMI (e.g., audio devices” (see Fig. 4, [0254], 1st sentence} via MAC SDUs ([0420]; data “MAC SDUs belonging to one or different logical channels into/from transport blocks (TB) delivered to/from the physical layer on transport channels” ([0421])) said MAC/SDUs with conversion function/functionality “ITS-S gateway 1611, 1811 (see e.g., FIGS. 16 and 18) is capable of converting protocols”, [0253]}.
Ganon/Kibardin and Yang are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganon/Kibardin and Yang before him or her, to modify Ganon/Kibardin’s device incorporating and Yang’s “edge compute node 1240” and corresponding data conversion “ITS-S gateway 1611, 1811” (see Figs. 12, 16, and 18).
The suggestion/motivation for doing so would have been to implement Radio Access Technologies (RATs) may be used for ITS. Cooperative ITS (C-ITS) have been developed to enable an increase in traffic safety and efficiency, and to reduce emissions and fuel consumption. The initial focus of C-ITS was on road traffic safety and especially on vehicle safety by facilitating information sharing among ITS stations. CPS reduces the ambient uncertainty of an ITS-S about its current environment, as other ITS-Ss contribute to context information and consequently reducing ambient uncertainty, it improves efficiency and safety of the ITS (Yang [0003] and [0004] paraphrased respectively).
Therefore, it would have been obvious to combine Yang with Ganon/Kibardin to obtain the invention as specified in the instant claim(s).
However, neither one of the group consisting of Ganon, Kibardin, and Yang appears to explicitly disclose applying to an audio direct memory access device converting audio data.
Furthermore, George discloses applying to an audio direct memory access device {“ DMA transmit and receive channels may include [applying] audio channels.”, see Fig. 2, Col 6, lines 1-4} converting audio data {“ creates the audio sample buffer in memory 120, builds and [converts] writes the sample buffer's transfer descriptors into DMA control circuit 130,”, see Fig. 4B, Col 17, lines 34-36}.
Ganon/Kibardin/Yang and George are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganon/Kibardin/Yang and George before him or her, to modify Ganon/Kibardin/Yang’s device incorporating George’s “DMA control circuit” and respective transmit DMA datapath (see Figs. 3, 4a, 4B).
The suggestion/motivation for doing so would have been to implement a DMA control circuit techniques help enforce desired qualities of service for multiple active peripherals on a per-channel basis, while also providing software increased visibility regarding the timing details of a given transfer (George Col 2, lines 39-50).
Therefore, it would have been obvious to combine George with Ganon/Kibardin/Yang to obtain the invention as specified in the instant claim(s).
However, neither one of the group consisting of Ganon, Kibardin, Yang, and George appears to explicitly disclose wherein the data bit number adjustment process adjust a range of the second data.
Furthermore, Itani discloses wherein the data bit number adjustment process adjust a range {“load an array for a 16 element 32 bit array at byte [range] addresses 4 to 67, the processor may require two memory reads”, see Fig. 3b [0129]} of the second data {“[second data via] access pattern may be achieved via multiple loads or stores”, see Fig. 3b [0129], last sentence}.
Ganon/Kibardin/Yang/George and Itani are analogous because they are from the same field of endeavor, routing stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganon/Kibardin/Yang and George before him or her, to modify Ganon/Kibardin/Yang/George’s system incorporating Itani’s “filtering operation” (see Fig. 3b, [0118]).
The suggestion/motivation for doing so would have been to implement filtering operations/SIMD vectors so that vector processors, may operate on multiple elements in a same operation to gain efficiency that is required to execute these types of parallel processing algorithms in real time, while consuming low power (Itani [0229] paraphrased).
Therefore, it would have been obvious to combine Itani with Ganon/Kibardin/Yang/George to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Kibardin discloses further comprising:
a data import controller {an import controller within “every layer of neurons receives activations during one or more forward passes”, [0823], 4th sentence}, electrically connected to the first channel combination/separation unit and the source device {“, and configured to control the source device to import the first data {“ into the first channel combination/separation unit {“;
and a data export controller {“computations performed during the one or more backward [export] passes associated with the forward passes”, [0823] 4th sentence}, electrically connected to the second channel combination/separation unit and the destination device {“a neural network is trained using continuous propagation of stimuli to perform SGD” per routing destination, [0823] 1st sentence}, configured to control the destination device to export the fourth data {“Continuous propagation enables layer parallelism”, [0822], 3rd sentence} from the second channel combination/separation unit {“ by enabling each layer [and respective channel] to learn concurrently with others without explicit synchronization”, [0822], 3rd sentence}, and configured to generate a count trigger signal {“The mode is a mutually exclusive selected one of a counter mode” with an appropriate count trigger signal”, [0951] last three sentence} to the data processing device so that the data processing device counts a migration number of the fourth data {“[migration number] stimuli are applied to the input layer and activations from the input layer flow to subsequent layers”, see Fig. 4a, [0465]}.
As per claim 3, the rejection of claim 2 is incorporated and Kibardin discloses wherein the data processing device comprises:
an amplification/down-scale unit {“deep learning accelerator is scalable for large deep neural networks”, see Fig. 29, [0429]}, configured to amplify/scale-down the second data based on a gain {“rounding modes that round any result greater in magnitude than the maximum magnitude to the maximum magnitude” in a FP Control register 2925 per accelerator, [0429]};
a gain control unit {“FPU 2901 comprises FP control and execution logic”, see Fig. 29, [0880] 1st sentence}, electrically connected to the amplification/down-scale unit and the data export controller {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) specifies amplification/downscale process “Other multidimensional tensor contractions… within this framework, as are convolutions, downsampling, and the other operations of neural network layer processing”, [1107] last sentence}, wherein the migration number is configured to determine whether the gain control unit is triggered {“During Chain 403, gradients are calculated based on the deltas (e.g., with respect to the weights in the neurons) as they are generated during Delta 402”}, and further to control the gain of the amplification/down-scale unit {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) specifies amplification/downscale process “Other multidimensional tensor contractions… within this framework, as are convolutions, downsampling, and the other operations of neural network layer processing”, [1107] last sentence};
a data bit number adjustment unit {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) that includes data bit number adjustment “initialized XDSRs and stride registers holding the stride values) are initialized by instructions that move data from memory to the DSRs” (see Fig. 23, [0762], 2nd sentence)}, configured to adjust a data bit number of the second data {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) via “Normalizer 2913 normalizes Mantissa 2955 by detecting Leading Zeros 2955.1 and shifting Other Bits 2955.2 to the left” as instructed by DSR (see Fig. 29, 30C, and 30D, [0883], 4th sentence}; and
a shifting unit {“immediate 2534”, see Fig. 25c, [0812] last sentence}, configured to perform a right-shift {Examiner’s interpretation: recitation term “or” renders this dependent claim as a Markush claim, thus the reference needs only disclose one element in the group to address the claim} or a left-shift of at least zero bit on the second data {left shift “Immediate 2534 is shifted one bit to the left and sign extended”, see Fig. 25c [0812] last sentence}.
As per claim 4, the rejection of claim 3 is incorporated and Kibardin discloses wherein after the gain control unit is triggered {“operations performed by FPU 2901 that overflow the FP representation return infinity, while otherwise retaining behavior of the rounding mode specified [triggered]”, see Fig. 30B [0896] 5th sentence}, the gain control unit adjusts the gain based on a comparison result between the gain and a target gain {“FPU 2901 to perform additional FP operations with optional stochastic rounding… [gain] comparison”, see Fig. 29 [0891]}, or based on a comparison result between an intensity of the processed second data and a target intensity {Examiner’s interpretation: recitation term “or” renders this dependent claim as a Markush claim, thus the reference needs only disclose one element in the group to address the claim}.
As per claim 5, the rejection of claim 3 is incorporated and Kibardin discloses wherein the data processing device further comprises:
a route device {“The routing is in accordance with a respective virtual channel specifier (e.g. a color) of each of the wavelets and controlled by routing configuration information of the router”, 4th sentence from bottom of [[0108]}, electrically connected to the first channel combination/separation unit, the second channel combination/separation unit {“routing is in accordance with a respective virtual channel specifier (e.g. a color”, [0107]}, the amplification/down-scale unit {“node performs a [amp/downscale] tensor operation, such as a tensor contraction of some kind”, see Fig. 48 [1115]}, the data bit number adjustment unit and the shifting unit, and configured to control a data flow path {“[data flow] cycles in the graph correspond to trainable neural network model parameter”, see Fig. 48 [1116]} of the second data to determine the sequence and execution times of the amplification/down-scale process {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) specifies amplification/downscale process “Other multidimensional tensor contractions… within this framework, as are convolutions, downsampling, and the other operations of neural network layer processing”, [1107] last sentence}, the data bit number adjustment process and the shifting process {“performs Fetch/Decode Instruction with DSR(s) 2303” ([0770]) via “Normalizer 2913 normalizes Mantissa 2955 by detecting Leading Zeros 2955.1 and shifting Other Bits 2955.2 to the left” as instructed by DSR (see Fig. 29, 30C, and 30D, [0883], 4th sentence} based on the control selection command {“embodiment of an [control selection] immediate instruction”, see Fig. 25c [0810]}.
As per claim 6, the rejection of claim 5 is incorporated and Kibardin wherein the route device comprises a plurality of multiplexers {“Qdistr” multiplexing a single input “Off Ramp 820” (see Fig. 8) to multiple output “scheduling info 896”, see Fig. 8 [0539]}, a plurality of demultiplexers {“Picker 830” behaves as a DEMUX from Scheduling Info 896 to further outputs “RF 842”, “PC 834”, and “I-Seq 836” see Fig. 8 [0544]} and a plurality of buffers {“Data Path 852 is enabled to write one or more wavelets into one of [buffers] Output Queues”, see Figs. 6 and 8 [0561] first sentence}.
As per claim 7, the rejection of claim 4 is incorporated and Kibardin wherein the gain control unit further comprises:
a migration counter, electrically connected to the data export controller {“vector variously represents, e.g., weights of a neural network, inputs or stimuli of a neural network, activations of a neural network, and/or partial [migration count] sums of a neural network”, [0119] last 3 sentences}, and configured to receive the count trigger signal to count the migration number of the fourth data {“every layer of neurons receives [plurality of data] activations during one or more forward passes, see Figs. 4a and 4c, [0823], 4th sentence}, wherein when the migration number is counted to a predetermined number {“respective bit vectors with N entries, one entry for each color” and/or predetermined channel number, [0543], see Fig. 8}, the migration counter outputs a gain-control triggering signal and resets the migration number {“applies functional composition to formulate [and reset] representations in terms of internal state and [the migration number] stimuli the internal state is subjected”, [0841] 1st sentence};
and a gain controller {“FPU 2901 comprises FP control and execution logic”, see Fig. 29, [0880] 1st sentence}, electrically connected to the migration counter, wherein the gain controller is triggered based on the gain-control triggering signal {“regularization is provided by a sampling procedure (e.g., SGD), by [a gain] learning rate”, see Fig. 27D, 3rd sentence from bottom of [0840}, and wherein after the gain-control triggering signal is triggered {“ forward pass operation for SGD or MBGD, activation”, see Fig. 28a, [0852] 1st sentence}, the gain is adjusted {“then Subsequent Layer 2802 computes [gain adjustment up/down] delta Δ.sub.3,t according to the delta rule”, see Figs. 28a and 28b, [0854], 2nd sentence} based on the comparison result between the gain of the amplification/down-scale unit and the target gain {“FPU 2901 to perform additional FP operations with optional stochastic rounding… [gain] comparison”, see Fig. 29 [0891]}, or based on the comparison result between the intensity of the second data after the amplification/down-scale process and the target intensity {Examiner’s interpretation: recitation term “or” renders this dependent claim as a Markush claim, thus the reference needs only disclose one element in the group to address the claim}.
As per claim 8, the rejection of claim 4 is incorporated and Kibardin discloses wherein the direct memory access device is an audio direct memory access device {“speech recognition” [0459]}, wherein each of the first channel combination/separation unit and the second combination/separation unit is a mono/multi-channel audio data conversion unit {“also provides a monotonically decreasing effective utilization function, u.sub.A(Δx, Δy)”, [1193] 3rd sentence}, wherein the intensity is a volume intensity {“physical communication topologies such as a mesh, a 2D mesh, a 3D mesh, a hypercube, a torus” ([0121], 2nd sentence) that can calculate volume “height of the non-overlapping rectangle assignment to update the utilization using u.sub.A(Δx, Δy)” in the z direction/z-axis ([1198], see Fig. 59}, and the target intensity is a target volume intensity {“The δ labelled arcs carry partial derivatives of the [intensity] loss function with respect to node outputs”, see Fig. 54, [1174], last two sentences}, and wherein the first data are first audio data {“Serializer/Deserializer (SerDes), [video/media/audio] I/O drivers”, last two sentences of [0115]}, the second data are second audio data {“usage scenarios, I/O FPGAs 420A elements collectively correspond to FPGAs 121”, see Fig. 1, [0466] last sentence}, the third data are third audio data {“usage scenarios, I/O FPGAs 420B elements collectively correspond to FPGAs 121 of FIG. 1.”, [0471] last sentence}, and the fourth data are fourth audio data {“instances of I/O FPGAs 420C that one or more peripheral portions of the instances of PEs+HBM 483 are coupled”, see Fig. 4c, [0475], 3rd sentence}.
Referring to claims 10-17 are system claims reciting claim functionality corresponding to the device claims of claims 1-8, respectively, thereby rejected under the same rationale as claims 1-8 recited above.
Response to Arguments
Applicant’s arguments filed on 03/17/2026 have been considered but deemed moot in view of the following explanation:
Applicant alleges that there is no motivation for the combination of references including does not teach claim 1’s “converting audio data” specification (Remarks page 7, last full paragraph).
The Examiner respectfully points to George Col 22, lines 55-57: “real-time data is audio data, such as data associated with audio peripherals, such as headsets, speakers, microphones, etc. When audio data is being handled, method 800 involves transferring blocks of audio data between memory 120 and audio peripherals within peripherals 150 and managing transfers of the blocks of audio data over the plurality of DMA channels via intermediate storage buffer 140.” The citation was not referring to the transfer descriptors, but the data referenced by the descriptors sent by the peripherals.
Real-time data has a different rate compare to isochronous, USB known to one of ordinary skill in the art having both isochronous and bursting data; these USB protocols (Col 25, lines 53-55) format/rate/frequency versus the frequency microphone or audible range in “headsets”. George Col 22, lines 55-57: “audio data, such as data associated with audio peripherals”. Naturally some amount of conversion when the claims do not go in further detail what kind of audio data conversion is performed (a first format to a second format, audio to audio, frequency, pitch and the like).
George Col 22, lines 63-67: “Transfer of audio data can be said to be isochronous, meaning that data is transmitted regularly at a desired rate. Isochronous data transfer thus involves close timing coordination between data source and destination, which is particularly important for audio data”. Other rate examples “Target channel data rate and a threshold level” (Col 21, lines 44-47)
For these reasons the current ground of rejection(s) is respectfully maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “DMA”/Direct memory accessing, “first channel number”, or “a control selection command”: US 20260133924 A1, US 20260133923 A1, US 20260010486 A1, US 11822812 B2, US 20230259467 A1, US 20230169025 A1, US 11386029 B2, and US 20220083486 A1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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