DETAILED ACTION
This office action is in response to the application filed on 10/26/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/26/2023 and 12/25/2023 has been considered by the examiner.
Election/Restrictions
Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group 2, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/26/2025.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
In re to claims 18-20, method claims 18-20 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Huang US 2011/0025292.
Regarding Claims 1 and 18, Huang teaches (Figures 7-9) A converter circuit (700), comprising: a plurality of power stage circuits, (modules) configured to output a plurality of output currents according to a plurality of control signals (Vo signals and from 808a-b), and configured to selectively adjust (adjusting done by 811 and 804) a plurality of current sense values (from 810) corresponding to the plurality of output currents according to a comparison result of a plurality of temperature sense values (from 809 and sent to 811) of the plurality of power stage circuits and a highest temperature value (par. 48) of the plurality of power stage circuits (determined by the sharing bus, the comparison is done by 903); and a control circuit (806-808), electrically coupled to the plurality of power stage circuits, wherein the control circuit is configured to output the plurality of control signals to the plurality of power stage circuits (from 808), configured to receive the plurality of current sense values from the plurality of power stage circuits (from 804), and configured to adjust the plurality of control signals according to the plurality of current sense values (with 806), so that the plurality of output currents are changed in magnitude (par. 22). (For Example: Par. 45-51)
Regarding Claims 3 and 20, Huang teaches (Figures 7-9) wherein each of the plurality of power stage circuits (modules) is configured to directly output a corresponding one of the plurality of current sense values (sent to 806) when a corresponding one of the plurality of temperature sense values is equal to the highest temperature value (par. 48). (For Example: Par. 45-51)
Regarding Claim 4, Huang teaches (Figures 7-9) wherein each of the plurality of power stage circuits (module) comprises: a power circuit (803), configured to output a corresponding one of the plurality of output currents according to a corresponding one of the plurality of control signals (producing Io based on signals from 808); a temperature sense circuit (809), configured to sense a temperature of a corresponding one of the plurality of power stage circuits, to output a corresponding one of the plurality of temperature sense values; a current sense circuit (810), configured to sense the corresponding one of the plurality of output currents, to output a corresponding one of the plurality of current sense values; a temperature feedback terminal (with 711); a current feedback terminal (output of 804); and a current feedback control circuit (811 and 804), electrically coupled to the temperature sense circuit (809), the current sense circuit (810), the temperature feedback terminal and the current feedback terminal, wherein the current feedback control circuit is configured to compare the corresponding one of the plurality of temperature sense values with the highest temperature value (at 903), and configured to selectively adjust the corresponding one of the plurality of current sense values (sent to 806) according to a comparison result of the corresponding one of the plurality of temperature sense values and the highest temperature value (for the comparison of 804a). (For Example: Par. 45-51)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 , 5-6, 8-9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang US 2011/0025292 in view of Ouyang US 2015/0002126.
Regarding Claims 2 and 19, Huang teaches (Figures 7-9) a circuit.
Huang does not teach wherein each of the plurality of power stage circuits is configured to reduce and output a corresponding one of the plurality of current sense values when a corresponding one of the plurality of temperature sense values is smaller than the highest temperature value.
Ouyang teaches (Figure 4) wherein each of the plurality of power stage circuits (at 700) is configured to reduce and output a corresponding one of the plurality of current sense values (Iphase) when a corresponding one of the plurality of temperature sense values is smaller than the highest temperature value (with 61-64 a subtraction is done to the iphase and the signal is reduce). (For Example: Par. 27-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein each of the plurality of power stage circuits is configured to reduce and output a corresponding one of the plurality of current sense values when a corresponding one of the plurality of temperature sense values is smaller than the highest temperature value, as taught by Ouyang to improve thermal balancing operation.
Regarding Claim 5, Huang teaches (Figures 7-9)wherein the current feedback control circuit (804 and 811) comprises: a temperature comparison circuit (811 and 804), electrically coupled to the temperature sense circuit (809) and the temperature feedback terminal at a first node and a second node respectively (see fig. 9, at 711 and 812a), and configured to compare the corresponding one of the plurality of temperature sense values with the highest temperature value (par. 48). (For Example: Par. 45-51)
Huang does not teach a sense value adjusting circuit, electrically coupled to the current sense circuit, the temperature comparison circuit and the current feedback terminal, and configured to output the corresponding one of the plurality of current sense values or the adjusted corresponding one of the plurality of current sense values to the current feedback terminal.
Ouyang teaches (Figure 4) a sense value adjusting circuit (61-64), electrically coupled to the current sense circuit (generating Iphase), the temperature comparison circuit (at 705) and the current feedback terminal (output of 61-64), and configured to output the corresponding one of the plurality of current sense values or the adjusted corresponding one of the plurality of current sense values to the current feedback terminal (with 61-64). (For Example: Par. 27-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include a sense value adjusting circuit, electrically coupled to the current sense circuit, the temperature comparison circuit and the current feedback terminal, and configured to output the corresponding one of the plurality of current sense values or the adjusted corresponding one of the plurality of current sense values to the current feedback terminal, as taught by Ouyang to improve thermal balancing operation.
Regarding Claim 6, Huang teaches (Figures 7-9) wherein under a condition that the corresponding one of the plurality of temperature sense values is smaller than the highest temperature value (determined by 804a), the temperature comparison circuit (with 804 and 811) outputs a compensation value according to a voltage difference generated between the first node and the second node (812a and 711 nodes, Fig. 9 and par. 49-50). (For Example: Par. 45-51)
Huang does not teach the sense value adjusting circuit reduces the corresponding one of the plurality of current sense values by the compensation value and outputs reduced corresponding one of the plurality of current sense values.
Ouyang teaches (Figure 4) the sense value adjusting circuit (61-64) reduces the corresponding one of the plurality of current sense values (Iphase) by the compensation value (Ioffset) and outputs reduced corresponding one of the plurality of current sense values (with 61-64 subtraction). (For Example: Par. 27-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include the sense value adjusting circuit reduces the corresponding one of the plurality of current sense values by the compensation value and outputs reduced corresponding one of the plurality of current sense values, as taught by Ouyang to improve thermal balancing operation.
Regarding Claim 8, Huang teaches (Figures 7-9) a circuit.
Huang does not teach wherein the plurality of control signals (from ) are a plurality of pulse width modulation signals, and the control circuit is configured to adjust a plurality of duty ratios of the plurality of pulse width modulation signals according to the plurality of current sense values.
Ouyang teaches (Figures 2-4) wherein the plurality of control signals are a plurality of pulse width modulation signals (PWM see fig. 2), and the control circuit is configured to adjust a plurality of duty ratios of the plurality of pulse width modulation signals according to the plurality of current sense value (with 106 and 107 of fig. 2). (For Example: Par. 15-18)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the plurality of control signals are a plurality of pulse width modulation signals, and the control circuit is configured to adjust a plurality of duty ratios of the plurality of pulse width modulation signals according to the plurality of current sense values, as taught by Ouyang to improve thermal balancing operation.
Regarding Claim 9, Huang teaches (Figures 7-9) a circuit.
Huang does not teach wherein the control circuit is configured to average the plurality of current sense values of the plurality of power stage circuits to obtain a current average value, and is configured to compare the plurality of current sense values of the plurality of power stage circuits with the current average value.
Ouyang teaches (Figures 2-4) wherein the control circuit (controller, fig. 4) is configured to average the plurality of current sense values of the plurality of power stage circuits to obtain a current average value (par. 21, 104), and is configured to compare the plurality of current sense values of the plurality of power stage circuits with the current average value (Fig. 3, at 602). (For Example: Par. 22-25)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the control circuit is configured to average the plurality of current sense values of the plurality of power stage circuits to obtain a current average value, and is configured to compare the plurality of current sense values of the plurality of power stage circuits with the current average value, as taught by Ouyang to improve thermal balancing operation.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang US 2011/0025292 in view of Ouyang US 2015/0002126 and further in view of Mirjafari US 2018/0269786.
Regarding Claim 7, Huang teaches (Figures 7-9) wherein under a condition that the corresponding one of the plurality of temperature sense values is equal to the highest temperature value (717 value of one of the modules). (For Example: Par. 45-51)
Huang does not teach the temperature comparison circuit outputs a compensation value being a zero value according to a voltage difference generated between the first node and the second node, and the sense value adjusting circuit directly outputs the corresponding one of the plurality of current sense values.
Ouyang teaches (Figure 4) the temperature comparison circuit (at 705) outputs a compensation value (with Ioffset), and the sense value adjusting circuit (61-64) directly outputs the corresponding one of the plurality of current sense values (61-64 output). (For Example: Par. 27-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include the temperature comparison circuit outputs a compensation value, and the sense value adjusting circuit directly outputs the corresponding one of the plurality of current sense values, as taught by Ouyang to improve thermal balancing operation.
Huang as modified does not teach a compensation value being a zero value according to a voltage difference generated between the first node and the second node.
Mirjafari (Figures 2-3) a compensation value (from 246-248) being a zero value (par. 52) according to a voltage difference generated between the first node and the second node (between 252 and 254). (For Example: Par. 27-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include a compensation value being a zero value according to a voltage difference generated between the first node and the second node, as taught by Mirjafari to prevent the voltage regulator controller shutdown all of the power stages, causing a power disruption .
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang US 2011/0025292 in view of Ouyang US 2015/0002126 and further in view of Soleno US 2023/0238882.
Regarding Claim 1, Huang teaches (Figures 7-9) a converter.
Huang does not teach wherein the control circuit is configured to raise the duty ratio of a corresponding one of the plurality of pulse width modulation signals when a corresponding one of the plurality of current sense values is smaller than the current average value, and is configured to reduce the duty ratio of the corresponding one of the plurality of pulse width modulation signals when the corresponding one of the plurality of current sense values is greater than the current average value.
Soleno teaches (Figures 3-4) wherein the control circuit (400) is configured to raise (claim 19) the duty ratio of a corresponding one of the plurality of pulse width modulation signals (PWM signal fig. 4) when a corresponding one of the plurality of current sense values is smaller than the current average value (at 420, signals 419 and 412), and is configured to reduce (claim 18) the duty ratio of the corresponding one of the plurality of pulse width modulation signals (PWM signal) when the corresponding one of the plurality of current sense values is greater than the current average value (at 420 with signals 419 and 412). (For Example: Par. 28-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the control circuit is configured to raise the duty ratio of a corresponding one of the plurality of pulse width modulation signals when a corresponding one of the plurality of current sense values is smaller than the current average value, and is configured to reduce the duty ratio of the corresponding one of the plurality of pulse width modulation signals when the corresponding one of the plurality of current sense values is greater than the current average value, as taught by Soleno to avoid unequal currents between the rails produces unequal power dissipations between the rails, which results in unequal thermal management and reduction of power supply efficiency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838