DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-9, 11-12, and 14-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cain (US 2018/0330880) in view of Ritter et al (US 2004/0090732).
Regarding claim 1, Cain discloses a multilayer capacitor (Fig. 1-4) comprising: a body (Fig. 1, 10) having a top surface (Fig. 1, top of 10), a bottom surface (Fig. 1, bottom of 10) opposing the top surface, a pair of side surfaces (Fig. 1D, top side and bottom side) opposing one another along a lateral direction (Fig. 1D, up and down), and a pair of end surfaces (Fig. 1, 1D, left and right sides) opposing one another along a longitudinal direction (Fig. 1D, left to right), the body also having side edges (Fig. 1D, top and bottom edges) defining lateral boundaries of the top and bottom surfaces and including a first top side edge, a second top side edge, a first bottom side edge, and a second bottom side edge each extending along the longitudinal direction between the pair of end surfaces (Fig. 1D), the first top side edge and the second top side edge opposing each other along the lateral direction (Fig. 1D), the first bottom side edge and the second bottom side edge opposing each other along the lateral direction (Fig. 1D), the body containing alternating dielectric layers and internal electrode layers ([0077]), the internal electrode layers including first internal electrode layers (Fig. 1C, 105) and second internal electrode layers (Fig. 1C, 115), each internal electrode layer including: a main body having a top edge (Fig. 1C, top of 105), a bottom edge (Fig. 1C, bottom of 105) opposite the top edge, and two side edges (Fig. 1C, sides of 105) extending between the top edge and the bottom edge (Fig. 1C), at least one lead tab (Fig. 1C, 120) extending from the top edge of the main body of the internal electrode layer and at least one lead tab (Fig. 1C, 130) extending from the bottom edge of the main body of the internal electrode layer (Fig. 1C); and external terminals (Fig. 1A, 12/14) including a first external terminal (Fig. 1A, 12) disposed on at least one of the top surface or the bottom surface and electrically connected to the first internal electrode layers (Fig. 1) and a second external terminal (Fig. 1A, 14) disposed on at least one of the top surface or the bottom surface and electrically connected to the second internal electrode layers (Fig. 1) each external terminal having two sides extending parallel (Fig. 1A), wherein the external terminals are arranged in a linear fashion on at least one of the top surface or the bottom surface of the body and are spaced apart from the side edges of the body such that only dielectric material is disposed between the external terminals and the side edges of the body (Fig. 1A).
However, Cain fails to teach that each external terminal having two sides extending parallel and adjacent to the side edges of the body, wherein the external terminals are arranged in a linear fashion in a single row on at least one of the top surface or the bottom surface of the body and are spaced apart from the side edges of the body such that only dielectric material is disposed between the two sides of each external terminals and the side edges of the body.
Ritter teaches that each external terminal (Fig. 7B, 50) having two sides (Fig. 7B, top and bottom) extending parallel and adjacent to the side edges (Fig. 7B, top and bottom sides of 44) of the body, wherein the external terminals are arranged in a linear fashion in a single row on at least one of the top surface (Fig. &b, when face with 50s is facing up) or the bottom surface of the body and are spaced apart from the side edges of the body such that only dielectric material is disposed between the two sides of each external terminals and the side edges of the body (Fig. 7B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ritter to the invention of Cain, in order to form electrical connections to next level components on multiple locations on the capacitor (Ritter [0004]).
Regarding claim 2, Cain, as modified by Ritter, further teaches that the first external terminal (Fig. 1A, bottom 12) is disposed adjacent a first end surface (Fig. 1A, bottom left side) of the pair of end surfaces of the body and the second external terminal (Fig. 1A, top right 14) is disposed adjacent a second end surface (Fig. 1A, far end of 10) of the pair of end surfaces of the body, wherein the first external terminal and the second external terminal are spaced apart in the longitudinal direction on the top surface by an end external terminal spacing distance (Fig. 1A), wherein the body has a body length in the longitudinal direction, and wherein a ratio of the body length to the end external terminal spacing distance is 1.1 or more (Fig. 1A, spacing can be equal distances [0050] so ratio would have to be at least 3).
Regarding claim 3, Cain, as modified by Ritter, further teaches that the ratio of the body length to the end external terminal spacing distance is within a range of 2 to 500 ([0050] and [0070-0071]).
Regarding claim 4, Cain, as modified by Ritter, further teaches that the ratio of the body length to the end external terminal spacing distance is within a range of 10 to 100 ([0050] and [0070-0071]).
Regarding claim 6, Cain, as modified by Ritter, further teaches that the external terminals are arranged in at least two columns (Fig. 1A), the at least two columns spaced apart from one another along the longitudinal direction (Fig. 1A).
Regarding claim 7, Cain, as modified by Ritter, further teaches that the number of columns of external terminals equals a number of lead tabs extending from the top edge of the main body of a respective one internal electrode layer (Fig. 1).
Regarding claim 8, Cain, as modified by Ritter, further teaches that the body has end edges defining longitudinal boundaries of the top and bottom surfaces and including a first top end edge, a second top end edge, a first bottom end edge, and a second bottom end edge each extending along the lateral direction between the pair of side surfaces (Fig. 1A, edges of the body), the first top end edge and the second top end edge opposing each other along the longitudinal direction (Fig. 1A), the first bottom end edge and the second bottom end edge opposing each other along the longitudinal direction (Fig. 1A), and wherein the external terminals are spaced apart from the end edges of the body such that only dielectric material is disposed between the external terminals and the end edges of the body (Fig. 1A).
Regarding claim 9, Cain, as modified by Ritter, further teaches that the external terminals include adjacent terminals spaced apart from one another in the longitudinal direction on the top surface by an adjacent external terminal spacing distance (Fig. 1A), wherein the body has a body length in the longitudinal direction, and wherein a ratio of the body length to the adjacent external terminal spacing distance is 1.1 or more (Fig. 1A, spacing can be equal distances [0050] so ratio would have to be at least 3).
Regarding claim 11, Cain, as modified by Ritter, further teaches that the ratio of the body length to the adjacent external terminal spacing distance is within a range of 10 to 100 ([0050] and [0070-0071]).
Regarding claim 12, Cain, as modified by Ritter, further teaches that the external terminals include an adjacent terminal adjacent the first external terminal on a same surface of the body (Fig. 1A), wherein the first external terminal and the adjacent terminal are spaced apart from one another in the longitudinal direction on the same surface by an adjacent external terminal spacing distance (Fig. 1A), and wherein a ratio of the end external terminal spacing distance to the adjacent external terminal spacing distance is 1.1 or more (Fig. 1A, spacing can be equal distances [0050] so ratio would have to be at least 3).
Regarding claim 14, Cain, as modified by Ritter, further teaches that the ratio of the end external terminal spacing distance to the adjacent external terminal spacing distance is within a range of 10 to 100 ([0050] and [0070-0071]).
Regarding claim 15, Cain, as modified by Ritter, further teaches that a pitch is defined between adjacent external terminals ([0070-0071]), wherein the body has a body length in the longitudinal direction, and wherein a ratio of the body length to the pitch is 1.1 or more (Fig. 1A, spacing can be equal distances [0050] so ratio would have to be at least 3).
Regarding claim 16, Cain, as modified by Ritter, further teaches that the ratio of the body length to the pitch is within a range of 2 to 500 ([0070-0071]).
Regarding claim 17, Cain, as modified by Ritter, further teaches that the ratio of the body length to the pitch is within a range of 10 to 100 ([0070-0071]).
Regarding claim 18, Cain, as modified by Ritter, further teaches that the first external terminal is disposed on the top surface of the body and the second external terminal is disposed on the top surface of the body (Fig. 1A), and wherein the external terminals further comprise a third external terminal disposed on the bottom surface and electrically connected to the first internal electrode layers (Fig. 1 and 4 [0086]) and a fourth external terminal disposed on the bottom surface and electrically connected to the second internal electrode layers (Fig. 1 and 4 [0086]).
Regarding claim 19, Cain, as modified by Ritter, further teaches that the first internal electrode layers and the second internal electrode layers are interleaved in an opposed relation and a dielectric layer is positioned between each first internal electrode layer and second internal electrode layer ([0077]).
Regarding claim 20, Cain, as modified by Ritter, further teaches that the dielectric layers comprise a ceramic ([0112]).
Regarding claim 21, Cain, as modified by Ritter, further teaches that each internal electrode layer includes at least two lead tabs (Fig. 1B), the at least two lead tabs extending from the top edge of the main body, the bottom edge of the main body, or both the top edge and the bottom edge of the main body (Fig. 1B), the two lead tabs including a first lead tab and a second lead tab (Fig. 1B).
Regarding claim 22, Cain, as modified by Ritter, further teaches that the first lead tab extends from the top edge and the second lead tab extends from the bottom edge (Fig. 1B), and wherein at least one lateral edge of the first lead tab is substantially aligned with at least one lateral edge of the second lead tab (Fig. 6B).
Regarding claim 23, Cain, as modified by Ritter, further teaches that the first lead tab extends from the top edge and the second lead tab extends from the bottom edge (Fig. 1B), wherein each of the first lead tab and the second lead tab include two lateral edges (Fig. 6B), and wherein both lateral edges of the first lead tab are substantially aligned with respective lateral edges of the second lead tab (Fig. 6B).
Regarding claim 24, Cain, as modified by Ritter, further teaches that at least one lateral edge of the lead tab on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge (Fig. 6B).
Regarding claim 25, Cain, as modified by Ritter, further teaches that both lateral edges of the lead tab on the top edge are substantially aligned with respective lateral edges of the lead tab on the bottom edge (Fig. 6B).
Regarding claim 26, Cain, as modified by Ritter, further teaches that the at least one top lead tab extending from the top edge of the main body of the internal electrode layer and the at least one bottom lead tab extending from the bottom edge of the main body of the internal electrode layer includes a lateral edge aligned with a side edge of the main body of the internal electrode layer (Fig. 6B).
Regarding claim 27, Cain, as modified by Ritter, further teaches that the internal electrode layers comprise a conductive metal ([0114]).
Regarding claim 28, Cain, as modified by Ritter, further teaches that the external terminals include an electroplated layer ([0116]).
Regarding claim 29, Cain, as modified by Ritter, further teaches that the external terminals include an electroless plated layer ([0117]).
Regarding claim 30, Cain, as modified by Ritter, further teaches that the external terminals include an electroless plated layer and an electroplated layer ([0116]).
Regarding claim 31, Cain, as modified by Ritter, further teaches that the external terminals include a first electroless plated layer, a second electroplated layer, and a third electroplated layer ([0131]).
Regarding claim 32, Cain, as modified by Ritter, further teaches that the first electroless plated layer includes copper ([0132]), the second electroplated layer includes nickel ([0132]), and the third electroplated layer includes tin ([0132]).
Regarding claim 33, Cain, as modified by Ritter, further teaches that the capacitor includes at least three sets of alternating dielectric layers and internal electrode layers (Fig. 3B).
Regarding claim 34, Cain, as modified by Ritter, further teaches a circuit board including the multilayer capacitor of claim 1 positioned on the circuit board (Fig. 4, 406).
Regarding claim 35, Cain, as modified by Ritter, further teaches that the board further comprises an integrated circuit package (Fig. 4, 402) and wherein the multilayer capacitor is positioned between the circuit board (Fig. 4, 406) and the integrated circuit package in a vertical direction such that the circuit board, the multilayer capacitor, and the integrated circuit package are present in a stacked arrangement (Fig. 4).
Regarding claim 36, Cain, as modified by Ritter, further teaches that the multilayer capacitor is directly connected to the circuit board and the integrated circuit package (Fig. 4).
Regarding claim 37, Cain, as modified by Ritter, further teaches an integrated circuit package containing the multilayer capacitor of claim 1 (Fig. 4).
Regarding claim 38, Cain, as modified by Ritter, further teaches that the external terminals are spaced apart from the first top side edge and the first bottom side edge to define a first edge gap (Fig. 1), wherein the external terminals are spaced apart from the second top side edge and the second bottom side edge to define a second edge gap (Fig. 1), and wherein each of the first edge gap and the second edge gap is greater than a thickness of an individual dielectric layer or an individual internal electrode layer (can be 2-10x the thickness of the dielectric layer [0038]).
Regarding claim 39, Cain, as modified by Ritter, further teaches that each of the first edge gap and the second edge gap is at least five times the thickness of the individual dielectric layer or the individual internal electrode layer (can be 2-10x the thickness of the dielectric layer [0038]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cain (US 2018/0330880) in view of Ritter et al (US 2004/0090732) in further view of Sutardja (US 2004/0223290).
Regarding claim 5, Cain further teaches that the first external terminal is disposed adjacent a first end surface of the pair of end surfaces of the body and the second external terminal is disposed adjacent a second end surface of the pair of end surfaces of the body (Fig. 1A), wherein the first external terminal is formed on the top surface (Fig. 1A), the bottom surface ([0076]) such that the first external terminal is disposed on the top surface (Fig. 1A), the bottom surface ([0076]), and wherein the second external terminal is formed on the top surface (Fig. 1A), the bottom surface ([0076]), such that the second external terminal is disposed on the top surface (Fig. 1A) and the bottom surface ([0076]).
However, Cain fails to teach that a first lateral edge of the at least one top lead tab and a first lateral edge of the at least one bottom lead tab are aligned with a first side edge of the two side edges of the main body of each internal electrode layer, the first external terminal is formed on the top surface, the bottom surface, and the first end surface from the top surface to the bottom surface such that the first external terminal is disposed on the top surface, the bottom surface, and the first end surface, and wherein the second external terminal is formed on the second end surface from the top surface to the bottom surface such that the second external terminal is disposed on the top surface, the bottom surface, and the second end surface.
Ritter teaches that the first external terminal (Fig. 8, 72) is formed on the top surface (Fig. 8, top of 74), the bottom surface (Fig. 8, bottom of 74), and the first end surface (Fig. 8, left side surface of 74) from the top surface to the bottom surface such that the first external terminal is disposed on the top surface, the bottom surface, and the first end surface (Fig. 8), and wherein the second external terminal (Fig. 8, 72 on opposite side) is formed on the second end surface (Fig. 8, right side of 74) from the top surface to the bottom surface such that the second external terminal is disposed on the top surface, the bottom surface, and the second end surface (Fig. 8).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ritter to the invention of Cain, in order to form electrical connections to next level components on multiple locations on the capacitor (Ritter [0004]).
Sutardja teaches that that a first lateral edge (Fig. 9A, left edge of 908) of the at least one top lead tab (Fig. 9A, 908) and a first lateral edge (Fig. 9A, left edge of 910) of the at least one bottom lead tab (Fig. 9A, 910) are aligned with a first side edge (Fig. 9A, left side of 904) of the two side edges of the main body of each internal electrode layer (Fig. 9A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sutardja to the invention of Cain, in order to have low parasitic inductance (Sutardja [0030]).
Additional Relevant Prior Art:
Prymak (US 2005/0231890) teaches relevant art in Fig. 1-8.
Mosley et al (US 2008/0001253) teaches relevant art in Fig. 1-10.
Randall et al (US 2008/0123247) teaches relevant art in Fig. 1-6.
Galvagni (US 2010/0188799) teaches relevant art in Fig. 1-14.
Oh et al (US 2016/0196921) teaches relevant art in Fig. 1-14.
Cain et al (US 2018/0330881) teaches relevant art in Fig. 1-4.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-38 have been considered but are moot because the new ground of rejection does not rely on only the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL P MCFADDEN/ Primary Examiner, Art Unit 2848