DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mlinar et al. (U.S. Pub. No. 20170324917).
An image sensor comprising:
a pixel (pixel circuit, par. 92 and Fig. 11C) including a first photodiode (PD1, par. 92-96 and Fig. 11C), a second photodiode (PD2 in the inner sub-pixel, par. 92-96 and Fig. 11C), a storage capacitor connected to the second photodiode (overflow capacitor Cov 1112, where second transfer transistor 1196 is used (during the interval D3) to route charges (overflow charge while charge is accumulating in the photodiode PD2) to the overflow capacitor Cov 1112, par. 92-96, 99, and Figs. 11C), an overflow transistor connected to the second photodiode (second transfer transistor 1196 is used (during the interval D3) to route charges (overflow charge while charge is accumulating in the photodiode PD2) to the overflow capacitor Cov 1112, par. 92-96, 99, and Figs. 11C), and a read circuit (each sub-pixel in an image pixel 22 may have a photodiode or photodiode region and readout circuitry for the photodiode or photodiode region, where readout circuitry associated with each photodiode or photodiode region in a given sub-pixel may include transfer gates, floating diffusion regions, and reset gates, par. 31);
a driver configured to provide control signals to the pixel (control circuitry, where image sensor 16 may be provided with control circuitry that provides the pixel supply voltage (such as VAA), pixel ground voltage, intermediate fixed voltages (i.e., fixed voltages between VAA and the pixel ground voltage), and control signals to the transistors of the pixel circuits in each of the image pixels 22, where the sensor control circuitry may provide control signals for the transfer transistors, charge overflow transfer transistors, reset transistors, row select transistors, anti-blooming transistors, or generally, any transistors in the pixel circuit or pixel readout circuitry coupled to the pixels, par. 32);
wherein the first photodiode has at least one of a larger light-receiving area or a greater sensitivity than the second photodiode (the inner sub-pixel (and photodiode in the inner sub-pixel) generally having a smaller light collecting region area than the outer sub-pixel or sub-pixel (and the photodiode(s) therein), meaning the outer sub-pixel has a larger light collecting region area, where outer sub-pixel includes photodiode PD1, par. 58, 59, 92-96, Fig. 2 and Fig. 11C), and
wherein some of the electric charge generated by the second photodiode during the exposure period is removed by the overflow transistor (region 1182 of the timing diagram represents signal behavior during a portion of the charge accumulation period of a pixel photodiode, where steps 1208 and 1210 are performed for selectively routing overflow charge while charge is accumulating in the photodiode PD2 such that overflow charge is allowed to pass from photodiode PD2 through storage gate 1102 to temporary storage node 1193, where overflow charge may be selectively routed from temporary storage node 1193 either to pixel voltage supply VAA through storage gate reset transistor 1192, or to the overflow capacitor 1112 (in an interval D3 as shown in FIG. 11B, where second transfer transistor 1196 may be used (during the interval D3) to route charges to an overflow capacitor Cov 1112) (in an interval D4 as shown in FIG. 11B), par. 89, 92, 99, 100, and Figs. 11B and 11C).
Mlinar is silent with regards to an analog-to-digital converter (ADC) configured to generate sub-digital signals by comparing an output signal of the pixel with a ramp signal; and a controller configured to control operations of the driver and the ADC. Official Notice is taken that it was well known before the effective filing date of the claimed invention to include using an analog-to-digital converter (ADC) configured to generate sub-digital signals by comparing an output signal of a pixel with a ramp signal (for example using a comparator); and a controller (for example a CPU) configured to control operations of a driver and the ADC. This is advantageous in that digital image signals can be recorded for later reproduction. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include to an analog-to-digital converter (ADC) configured to generate sub-digital signals by comparing an output signal of the pixel with a ramp signal; and a controller configured to control operations of the driver and the ADC.
Allowable Subject Matter
Claim 16-20 are allowed.
Regarding claim 16, no prior art could be located that teaches or fairly suggests each of the first and second pixels includes a first photodiode, a first floating node, a first transfer transistor, which is connected between the first photodiode and the first floating node, a conversion gain transistor, which is connected to the first floating node, a reset transistor, which is connected between the conversion gain transistor and a first voltage, a second photodiode, a second transfer transistor, which is connected between the second photodiode and the second floating node, a storage capacitor, which stores some of electric charge generated by the second photodiode, an overflow transistor, which removes some of the electric charge generated by the second photodiode, a third floating node, which is connected in common to the conversion gain transistor and the reset transistor, a connection transistor, which is connected to the second and third floating nodes, and a read circuit, which outputs an output signal to the column line in response to a voltage of the first floating node, wherein the pixel connection transistor is connected between the third floating nodes of the first and second pixels, wherein the first photodiode has at least one of a larger light-receiving area or a greater sensitivity than the second photodiode, wherein the first pixel outputs first, second, and third sub-output signals, which are obtained by converting electric charge generated by the first photodiode during an exposure period, with first, second, and third conversion gains, respectively, first, second, and third reset signals corresponding to the first, second, and third sub-output signals, respectively, fourth and fifth sub-output signals, which are obtained by converting some of electric charge generated by the second photodiode during the exposure period, with fourth and fifth conversion gains, respectively, and fourth and fifth reset signals corresponding to the fourth and fifth sub-output signals, respectively, and wherein as the pixel connection transistor is turned on, the first pixel generates the third and fifth sub-output signals with the third floating nodes of the first and second pixels electrically connected, in combination with the rest of the limitations of the claim.
Claims 17-18 depend on claim 16 and therefore are allowed.
Regarding claim 19, no prior art could be located that teaches or fairly suggests the first photodiode having at least one of a larger light-receiving area or a greater sensitivity than the second photodiode, the operating method comprising: removing first portions of electric charge generated by the second photodiode during an exposure period, via the overflow transistor; storing second portions of the electric charge in the storage capacitor, and transmitting third portions of the electric charge to the second floating node; outputting first and second sub-output signals, which are obtained by converting electric charge generated by the first photodiode, with first and second conversion gains, respectively; outputting first and second reset signals corresponding to the first and second sub-output signals, respectively, via the read circuit; and sequentially outputting third and fourth sub-output signals, which are obtained by converting the electric charge generated by the first photodiode, with third and fourth conversion gains, respectively, and fourth and third reset signals corresponding to the fourth and third sub-output signals, respectively, via the read circuit, in combination with the rest of the limitations of the claim.
Claim 20 depends on claim 19 and therefore is allowed.
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, no prior art could be located that teaches or fairly suggests output a first sub-output signal, which is obtained by converting electric charge generated by the first photodiode during an exposure period, with first conversion gain, output a second sub-output signal, which is obtained by converting the electric charge generated by the first photodiode during the exposure period, with second conversion gain, output a first reset signal corresponding to the first sub-output signal and a second reset signal corresponding to the second sub-output signal, output a third sub-output signal, which is obtained by converting a portion of electric charge generated by the second photodiode during the exposure period, with third conversion gain, output a fourth sub-output signal, which is obtained by converting the electric charge generated by the second photodiode and stored in the storage capacitor during the exposure period, with fourth conversion gain, and output a third reset signal corresponding to the third sub-output signal and a fourth reset signal corresponding to the fourth sub-output signal, in combination with the rest of the limitations of the claim and parent claim.
Claims 3-9 depend on claim 2 and therefore are objected to.
Regarding claim 10, no prior art could be located that teaches or fairly suggests a second transfer transistor, which is connected between the second photodiode and the second floating node, a capacitor connection transistor, which connects the second photodiode and the storage capacitor, a third floating node, which is connected in common to the conversion gain transistor and the reset transistor, and first and second connection transistors, which form an additional floating node between the second and third floating nodes and are connected in series, a connection transistor, which is connected between the second and third floating nodes, the read circuit generates the output signal to a column line in response to a voltage of the first floating node, first portions of the electric charge generated by the second photodiode during the exposure period are repeatedly removed by the overflow transistor, second portions of the electric charge generated by the second photodiode during the exposure period are repeatedly stored in the storage capacitor via the second transfer transistor and the capacitor connection transistor, third portions of the electric charge generated by the second photodiode during the exposure period are repeatedly transmitted to the additional floating node via the second transfer transistor and the first connection transistor, and the pixel converts electric charge transmitted to the additional floating node, among the electric charge generated by the second photodiode during the exposure period, with the third conversion gain, and converts electric charge stored in the storage capacitor, among the electric charge generated by the second photodiode during the exposure period, with the fourth conversion gain, in combination with the rest of the limitations of the claim and parent claim.
Claims 11 and 12 depend on claim 10 and therefore are objected to.
Regarding claim 13, no prior art could be located that teaches or fairly suggests a second transfer transistor, which is connected between the second photodiode and the second floating node, a capacitor connection transistor, which connects the second photodiode and the storage capacitor, a second floating node, which is connected in common to the conversion gain transistor and the reset transistor, and a connection transistor, which is connected between the second floating node and the second photodiode, the read circuit generates the output signal to a column line in response to a voltage of the first floating node, first portions of the electric charge generated by the second photodiode during the exposure period are repeatedly removed by the overflow transistor, second portions of the electric charge generated by the second photodiode during the exposure period are repeatedly stored in the storage capacitor via the second transfer transistor and the capacitor connection transistor, third portions of the electric charge generated by the second photodiode during the exposure period are repeatedly transmitted to the second floating node via the connection transistor, and the pixel converts electric charge transmitted to the second floating node, among the electric charge generated by the second photodiode during the exposure period, with the third conversion gain, and converts electric charge stored in the storage capacitor, among the electric charge generated by the second photodiode during the exposure period, with the fourth conversion gain, in combination with the rest of the limitations of the claim and parent claim.
Claims 14 and 15 depend on claim 13 and therefore are objected to.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639