Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3,7-11,13-15,19,20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al (PG Pub 2019/0198637 A1).
Regarding claim 1, Li teaches a semiconductor structure, comprising: a substrate structure (106, figs. 1-13); an epitaxial structure (paragraph [0056]) on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer (102) and a barrier layer (104); the epitaxial structure comprises a gate region; and in each of the at least one heterojunction structure, a part of the barrier layer corresponding to the gate region is removed to form a hole (figs. 3 and 13); a gate electrode (802/1300) on the gate region, wherein the gate electrode fills up the hole, and surrounds the channel layer; and a source electrode and a drain electrode (not shown: paragraph [0074]) respectively at two sides of the gate electrode.
Regarding claim 2, Li teaches the semiconductor structure according to claim 1, wherein the hole penetrates through the barrier layer in a direction parallel to the substrate structure; or the hole partially penetrates the barrier layer in a direction parallel to the substrate structure (fig. 3).
Regarding claim 3, Li teaches the semiconductor structure according to claim 1, wherein a side of the hole close to the channel layer is at the barrier layer, an interface of the barrier layer and the channel layer, or the channel layer (fig. 3).
Regarding claim 7, Li teaches the semiconductor structure according to claim 1, wherein the substrate structure comprises silicon on insulator (106/108, paragraph [0051]), silicon, sapphire, or silicon carbide.
Regarding claim 8, Li teaches the semiconductor structure according to claim 1, wherein the substrate structure comprises a base and a dielectric layer (108, paragraph [0051], fig. 2) on the base, and the epitaxial structure is bonded to the dielectric layer.
Regarding claim 9, Li teaches the semiconductor structure according to claim 1, wherein the channel layer and/or barrier layer comprise an N-type doped layer or (paragraph [0048]) a P-type doped layer.
Regarding claim 10, Li teaches the semiconductor structure according to claim 1, wherein the source electrode and the drain electrode are at a top (paragraph [0074]) of the epitaxial structure; or the source electrode and drain electrode are in an arched structure, on a top and sides of the epitaxial structure.
Regarding claim 11, Li teaches the semiconductor structure according to claim 1, further comprising an N-type heavily doped layer (1200, fig. 13, paragraph [0070]) on both sides of the epitaxial structure, wherein the N-type heavily doped layer is on a top and sides of the epitaxial structure, and the source electrode and/or the drain electrode are electrically connected to the epitaxial structure through (paragraph [0074]) the N-type heavily doped layer.
Regarding claim 13, Li teaches the semiconductor structure according to claim 1, further comprising a protecting layer (900, fig. 13A) on the epitaxial structure.
Regarding claim 14, Li teaches the semiconductor structure according to claim 1, wherein the at least one heterojunction structure is a nanowire structure (paragraph [0077]) or a nanosheet structure.
Regarding claim 15, Li teaches (see claim 1) a manufacturing method for a semiconductor structure, comprising: providing a substrate structure; forming an epitaxial structure on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer and a barrier layer; and the epitaxial structure comprises a gate region; and a hole is formed at a part of the barrier layer corresponding to the gate region; forming a gate electrode on the gate region, wherein the gate electrode fills the hole, and surrounds the channel layer; and forming a source electrode and a drain electrode respectively at two sides of the gate electrode.
Regarding claim 19, Li teaches (see claim 10) the manufacturing method according to claim 15, wherein the source electrode and the drain electrode are at a top of the epitaxial structure; or the source electrode and drain electrode are in an arched structure, on a top and sides of the epitaxial structure.
Regarding claim 20, Li teaches (see claim 2) the manufacturing method according to claim 15, wherein the hole penetrates through the barrier layer in a direction parallel to the substrate structure; or the hole partially penetrates the barrier layer in a direction parallel to the substrate structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (PG Pub 2019/0198637 A1) as applied to claim 1 above, and further in view of Rachmady et al (PG Pub 2020/0098757 A1).
Regarding claim 5, Li remains as applied in claim 1.
Li does not teach there are a plurality of the epitaxial structures formed on the substrate structure.
In the same field of endeavor, Rachmady teaches there are a plurality of the epitaxial structures (134, fig. 7) formed on the substrate structure (110), and the plurality of epitaxial structures are parallel and spaced (fig. 7), for the known benefit of integrating plural semiconductor structures to increase functionality of the overall device.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a plurality of the epitaxial structures formed on the substrate structure, and the plurality of epitaxial structures were parallel and spaced, for the known benefit of integrating plural semiconductor structures to increase functionality of the overall device.
Regarding claim 6, Rachmady teaches a plurality of the gate electrodes for the plurality of epitaxial structures are electrically connected (144, fig. 7) or separated from each other; and/or a plurality of the source electrodes (126, fig. 12) for the plurality of epitaxial structures are electrically connected or separated from each other; and/or a plurality of the drain electrodes (126) for the plurality of epitaxial structures are electrically connected or separated from each other, for the known benefit of individually or collectively turn the transistors on/off.
Claim(s) 1,12,15,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al (PG Pub 2013/0341704 A1) and Li et al (PG Pub 2019/0198637 A1).
Regarding claim 1, Rachmady teaches a semiconductor structure, comprising: a substrate structure (202, figs. 2-5); a structure (208) on the substrate structure, wherein the structure comprises at least one heterojunction structure (Si210/SiGe212) sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer (210) and a barrier layer (212); the structure comprises a gate region (240); and in each of the at least one heterojunction structure, a part of the barrier layer corresponding to the gate region is removed to form a hole (fig. 2F); a gate electrode (244, fig. 2K; 544, fig. 5C) on the gate region, wherein the gate electrode fills up the hole, and surrounds the channel layer; and a source electrode and a drain electrode (558, paragraph [0071], fig. 5C) respectively at two sides of the gate electrode, for the known benefit of turning the transistor on/off.
Rachmady does not teach the structure to be an epitaxial structure.
In the same field of endeavor, Li teaches a semiconductor structure, comprising: a substrate structure (106, figs. 1-13); an epitaxial structure (paragraph [0056]) on the substrate structure, for the known benefit of providing the structure with excellent crystallinity.
Regarding claim 12, Rachmady teaches the semiconductor structure according to claim 1, further comprising a gate insulating layer (243, fig. 2K and 543, fig. 5C) between the channel layer surrounded by the gate electrode and the gate electrode.
Regarding claim 15, Rachmady in view of Li teaches (see claim 1) a manufacturing method for a semiconductor structure, comprising: providing a substrate structure; forming an epitaxial structure on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer and a barrier layer; and the epitaxial structure comprises a gate region; and a hole is formed at a part of the barrier layer corresponding to the gate region; forming a gate electrode on the gate region, wherein the gate electrode fills the hole, and surrounds the channel layer; and forming a source electrode and a drain electrode respectively at two sides of the gate electrode.
Regarding claim 18, Rachmady teaches the manufacturing method according to claim 15, wherein forming the hole at the part of the barrier layer corresponding to the gate region comprises: forming a protecting layer (238/234/230, fig. 2D) covering the epitaxial structure; removing (figs. 2E and 2F) the protecting layer on a sidewall of the barrier layer in the gate region; and etching the barrier layer at the gate region by using the protecting layer as a mask, to form the hole (figs. 2E and 2F).
Allowable Subject Matter
Claims 4,16,17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities” (claim 4);
“bonding the epitaxial structure to the substrate structure; and removing the growth base” (claim 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Prosecution Insights