Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3,7-11,13-15,19,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (PG Pub 2019/0198637 A1) and Romancyk et al (PG Pub 2019/0348532 A1).
Regarding claim 1, Li teaches a semiconductor structure, comprising: a substrate structure (106, figs. 1-13); an epitaxial structure (paragraph [0056]) on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer (102) and a barrier layer (104); the epitaxial structure comprises a gate region; and in each of the at least one heterojunction structure, a part of the barrier layer corresponding to the gate region is removed to form a hole (figs. 3 and 13); a gate electrode (802/1300) on the gate region, wherein the gate electrode fills up the hole, and surrounds the channel layer; and a source electrode and a drain electrode (not shown: paragraph [0074]) respectively at two sides of the gate electrode, wherein materials of the channel layer and the barrier layer comprise group III nitride materials (paragraphs [0046][0047]).
Li does not teach surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities.
In the same field of endeavor, Romancyk teaches surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities (N-polar orientation, claim 15), for the benefit of improving high-frequency and high-power performance (paragraphs [0075][0181]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the channel layer and the barrier layer far from the substrate structure to be N-face polarities, for the benefit of improving high-frequency and high-power performance.
Regarding claim 2, Li teaches the semiconductor structure according to claim 1, wherein the hole penetrates through the barrier layer in a direction parallel to the substrate structure; or the hole partially penetrates the barrier layer in a direction parallel to the substrate structure (fig. 3).
Regarding claim 3, Li teaches the semiconductor structure according to claim 1, wherein a side of the hole close to the channel layer is at the barrier layer, an interface of the barrier layer and the channel layer, or the channel layer (fig. 3).
Regarding claim 7, Li teaches the semiconductor structure according to claim 1, wherein the substrate structure comprises silicon on insulator (106/108, paragraph [0051]), silicon, sapphire, or silicon carbide.
Regarding claim 8, Li teaches the semiconductor structure according to claim 1, wherein the substrate structure comprises a base and a dielectric layer (108, paragraph [0051], fig. 2) on the base, and the epitaxial structure is bonded to the dielectric layer.
Regarding claim 9, Li teaches the semiconductor structure according to claim 1, wherein the channel layer and/or barrier layer comprise an N-type doped layer or (paragraph [0048]) a P-type doped layer.
Regarding claim 10, Li teaches the semiconductor structure according to claim 1, wherein the source electrode and the drain electrode are at a top (paragraph [0074]) of the epitaxial structure; or the source electrode and drain electrode are in an arched structure, on a top and sides of the epitaxial structure.
Regarding claim 11, Li teaches the semiconductor structure according to claim 1, further comprising an N-type heavily doped layer (1200, fig. 13, paragraph [0070]) on both sides of the epitaxial structure, wherein the N-type heavily doped layer is on a top and sides of the epitaxial structure, and the source electrode and/or the drain electrode are electrically connected to the epitaxial structure through (paragraph [0074]) the N-type heavily doped layer.
Regarding claim 13, Li teaches the semiconductor structure according to claim 1, further comprising a protecting layer (900, fig. 13A) on the epitaxial structure.
Regarding claim 14, Li teaches the semiconductor structure according to claim 1, wherein the at least one heterojunction structure is a nanowire structure (paragraph [0077]) or a nanosheet structure.
Regarding claim 15, Li teaches (see claim 1) a manufacturing method for a semiconductor structure, comprising: providing a substrate structure; forming an epitaxial structure on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer and a barrier layer; and the epitaxial structure comprises a gate region; and a hole is formed at a part of the barrier layer corresponding to the gate region; forming a gate electrode on the gate region, wherein the gate electrode fills the hole, and surrounds the channel layer; and forming a source electrode and a drain electrode respectively at two sides of the gate electrode.
Li does not teach surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities.
In the same field of endeavor, Romancyk teaches surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities (N-polar orientation, claim 15), for the benefit of improving high-frequency and high-power performance (paragraphs [0075][0181]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the channel layer and the barrier layer far from the substrate structure to be N-face polarities, for the benefit of improving high-frequency and high-power performance.
Regarding claim 19, Li teaches (see claim 10) the manufacturing method according to claim 15, wherein the source electrode and the drain electrode are at a top of the epitaxial structure; or the source electrode and drain electrode are in an arched structure, on a top and sides of the epitaxial structure.
Regarding claim 20, Li teaches (see claim 2) the manufacturing method according to claim 15, wherein the hole penetrates through the barrier layer in a direction parallel to the substrate structure; or the hole partially penetrates the barrier layer in a direction parallel to the substrate structure.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (PG Pub 2019/0198637 A1) and Romancyk et al (PG Pub 2019/0348532 A1) as applied to claim 1 above, and further in view of Rachmady et al (PG Pub 2020/0098757 A1).
Regarding claim 5, the previous combination remains as applied in claim 1.
Li teaches there are a plurality of the epitaxial structures formed on the substrate structure (plural fins, paragraph [0053]).
Li does not teach the plurality of epitaxial structures are parallel.
In the same field of endeavor, Rachmady teaches there are a plurality of the epitaxial structures (134, fig. 7) formed on the substrate structure (110), and the plurality of epitaxial structures are parallel and spaced (fig. 7), for the known benefit of integrating plural semiconductor structures to increase functionality of the overall device.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a plurality of the epitaxial structures formed on the substrate structure, and the plurality of epitaxial structures were parallel and spaced, for the known benefit of integrating plural semiconductor structures to increase functionality of the overall device.
Regarding claim 6, Rachmady teaches a plurality of the gate electrodes for the plurality of epitaxial structures are electrically connected (144, fig. 7) or separated from each other; and/or a plurality of the source electrodes (126, fig. 12) for the plurality of epitaxial structures are electrically connected or separated from each other; and/or a plurality of the drain electrodes (126) for the plurality of epitaxial structures are electrically connected or separated from each other, for the known benefit of individually or collectively turn the transistors on/off.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (PG Pub 2019/0198637 A1) and Romancyk et al (PG Pub 2019/0348532 A1) as applied to claim 15 above, and further in view of Sharma et al (PG Pub 2023/0268410 A1).
Regarding claim 16, the previous combination remains as applied in claim 15.
The previous combination does not teach forming the epitaxial structure on the substrate structure comprises: forming the epitaxial structure on a growth base; bonding the epitaxial structure to the substrate structure; and removing the growth base.
In the same field of endeavor, Sharma teaches forming the epitaxial structure on the substrate structure comprises: forming the epitaxial structure (520-540, figs 5) on a growth base (growth substrate, paragraph [0103]); bonding the epitaxial structure to the substrate structure (target substrate, paragraph [0103]); and removing the growth base (paragraph [0103]), for the benefit of increasing functionality of the device (paragraph [0103]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make forming the epitaxial structure on the substrate structure to comprise: forming the epitaxial structure on a growth base; bonding the epitaxial structure to the substrate structure; and removing the growth base, for the benefit of increasing functionality of the device.
Regarding claim 17, Li teaches the manufacturing method according to claim 16, wherein before bonding the epitaxial structure to the substrate structure, or after bonding the epitaxial structure to the substrate structure, the manufacturing method further comprises: patterning the epitaxial structure to form a plurality of the epitaxial structures that are spaced (plural fins but only one is shown, paragraph [0053]).
Claim(s) 1,12,15,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al (PG Pub 2013/0341704 A1), Li et al (PG Pub 2019/0198637 A1), and Romancyk et al (PG Pub 2019/0348532 A1).
Regarding claim 1, Rachmady teaches a semiconductor structure, comprising: a substrate structure (202, figs. 2-5); a structure (208) on the substrate structure, wherein the structure comprises at least one heterojunction structure (Si210/SiGe212) sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer (210) and a barrier layer (212); the structure comprises a gate region (240); and in each of the at least one heterojunction structure, a part of the barrier layer corresponding to the gate region is removed to form a hole (fig. 2F); a gate electrode (244, fig. 2K; 544, fig. 5C) on the gate region, wherein the gate electrode fills up the hole, and surrounds the channel layer; and a source electrode and a drain electrode (558, paragraph [0071], fig. 5C) respectively at two sides of the gate electrode, for the known benefit of turning the transistor on/off.
Rachmady does not teach the structure to be an epitaxial structure.
In the same field of endeavor, Li teaches a semiconductor structure, comprising: a substrate structure (106, figs. 1-13); an epitaxial structure (paragraph [0056]) on the substrate structure, for the known benefit of providing the structure with excellent crystallinity.
Rachmady does not teach surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities.
In the same field of endeavor, Romancyk teaches surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities (N-polar orientation, claim 15), for the benefit of improving high-frequency and high-power performance (paragraphs [0075][0181]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the channel layer and the barrier layer far from the substrate structure to be N-face polarities, for the benefit of improving high-frequency and high-power performance.
Regarding claim 12, Rachmady teaches the semiconductor structure according to claim 1, further comprising a gate insulating layer (243, fig. 2K and 543, fig. 5C) between the channel layer surrounded by the gate electrode and the gate electrode.
Regarding claim 15, Rachmady in view of Li teaches (see claim 1) a manufacturing method for a semiconductor structure, comprising: providing a substrate structure; forming an epitaxial structure on the substrate structure, wherein the epitaxial structure comprises at least one heterojunction structure sequentially stacked in a direction away from the substrate structure; each of the at least one heterojunction structure comprises a channel layer and a barrier layer; and the epitaxial structure comprises a gate region; and a hole is formed at a part of the barrier layer corresponding to the gate region; forming a gate electrode on the gate region, wherein the gate electrode fills the hole, and surrounds the channel layer; and forming a source electrode and a drain electrode respectively at two sides of the gate electrode.
Rachmady does not teach surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities.
In the same field of endeavor, Romancyk teaches surfaces of the channel layer and the barrier layer far from the substrate structure are N-face polarities (N-polar orientation, claim 15), for the benefit of improving high-frequency and high-power performance (paragraphs [0075][0181]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the channel layer and the barrier layer far from the substrate structure to be N-face polarities, for the benefit of improving high-frequency and high-power performance.
Regarding claim 18, Rachmady teaches the manufacturing method according to claim 15, wherein forming the hole at the part of the barrier layer corresponding to the gate region comprises: forming a protecting layer (238/234/230, fig. 2D) covering the epitaxial structure; removing (figs. 2E and 2F) the protecting layer on a sidewall of the barrier layer in the gate region; and etching the barrier layer at the gate region by using the protecting layer as a mask, to form the hole (figs. 2E and 2F).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 and 5-20 have been considered but are moot because the new ground of rejection presented above.
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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