Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 objected to because of the following informalities:
Claim 7 recites “and the hafnium oxide is doped” however the earlier part of the line indicates that hafnium oxide is one of 3 choices. Appropriate correction is required.
Allowable Subject Matter
Claims 10-13, 16-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katoh (US 6087687 A).
In regard to claim 1 Katoh teaches a field effect transistor [see Fig. 16 “The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device with a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) a gate insulator of which includes a ferroelectric, and a fabrication method of the device” “A semiconductor device with a MISFET according to a sixth embodiment is shown in FIGS. 5 and 16, in which the substrate 3, the device region 1, the isolation region 2, and the field oxide layer 10 are the same in configuration as those in the first embodiment”], comprising:
a source region [“A source region 5 and a drain region 6 of the MISFET are formed in the surface region of the substrate 3 in the device region 1. The source and drain regions 5 and 6 are symmetrically located at each side of the gate electrode 13. In other words, the gate electrode 13 is placed between the source and drain regions 5 and 6”];
a drain region [“drain region 6”];
a channel [“A channel region is formed in the surface region of the substrate 3 between the source and drain regions 5 and 6 beneath the gate electrode 13”] between the source region and the drain region;
a gate insulating layer [“A SiO.sub.2 layer 8 is formed on the whole exposed surface of the substrate 10 to be contacted therewith in the device region 1. The periphery of the layer 8 is joined to the opposing end of the field oxide layer 10” “A patterned ferroelectric PZT layer 7 is formed on the substrate 3 to be buried in the window Ba of the SiO.sub.2 layer 8”] configured to cover an upper surface of the channel; and
a gate electrode [see Fig. 16 “gate electrode 19 extends along the longitudinal axis of the device region 1 to be contacted with the underlying layers 7 and B”] configured to cover an upper surface of the gate insulating layer,
wherein the gate insulating layer includes a first region [“A patterned ferroelectric PZT layer 7 is formed on the substrate 3 to be buried in the window Ba of the SiO.sub.2 layer 8”] where a ferroelectric crystal structure is dominant, and a second region [“SiO.sub.2 layer 8”] where a non-ferroelectric structure is dominant, and
wherein the gate electrode includes a first pattern region facing the first region [see Fig. 16 “gate electrode 19 extends along the longitudinal axis of the device region 1 to be contacted with the underlying layers 7 and B”] of the gate insulating layer, and a second pattern region [see Fig. 16] facing the second region of the gate insulating layer.
In regard to claim 7 Katoh teaches wherein the gate insulating layer comprises at least one of [see claim 1, see Katoh teaches PZT] hafnium oxide, lead zirconate titanate (PZT), or zinc oxide, and the hafnium oxide is doped with at least one element selected from zirconium (Zr), silicon (Si), aluminum (Al), lanthanum (La), gadolinium (Gd), and yttrium (Y).
Claim(s) 18, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katoh (US 6087687 A).
In regard to claim 18 Katoh teaches a capacitor [see Fig. 14 “The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device with a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) a gate insulator of which includes a ferroelectric, and a fabrication method of the device”, the Examiner notes that a MISFET is a capacitor under broadest reasonable interpretation, “A semiconductor device with a MISFET according to a fifth embodiment is shown in FIGS. 5 and 14, in which the substrate 3, the device region 1, the isolation region 2, and the field oxide layer 10 are the same in configuration as those in the first embodiment” ], comprising:
a first electrode [either the channel or the gate electrode see “A channel region is formed in the surface region of the substrate 3 between the source and drain regions 5 and 6 beneath the gate electrode 19”];
a second electrode [the other of either the channel or the gate electrode] facing the first electrode; and
a dielectric layer [ “A dielectric PZT layer 8 is formed on the SiO.sub.2 layer 9. The layer 8 has a rectangular plan shape covering the whole device region 1 except for the area where the ferroelectric PZT layer 7 is located” see can also include any part of “a thin dielectric layer 9 of SiO.sub.2 is formed to be contacted with the exposed surface of the substrate 3 in the device region 1”] between the first electrode and the second electrode, wherein the dielectric layer includes a first region where a ferroelectric crystal structure [see the “ferroelectric PZT layer 7”] is dominant, and a second region where a non-ferroelectric structure [see the “dielectric PZT layer 8”] is dominant, and
wherein the second electrode includes a first pattern region [see Fig. 14 both channel and gate electrode face the 7, 8, 9] facing the first region of the dielectric layer, and a second pattern region [see Fig. 14 both channel and gate electrode face the 7, 8, 9] facing the second region of the dielectric layer.
In regard to claim 19 Katoh teaches further comprising a non-ferroelectric layer [“a thin dielectric layer 9 of SiO.sub.2 is formed to be contacted with the exposed surface of the substrate 3 in the device region 1”] that is between [see Fig. 14 see that 9 is between substrate 3 and (PZT 7, 8) ] the first electrode and the dielectric layer, or between the second electrode and the dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-9, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katoh (US 6087687 A) in view of Heo et al. (US 20200055134 A1) hereafter referred to as Heo
In regard to claim 2 Katoh does not specifically teach wherein the gate insulating layer includes a plurality of first regions that are spaced apart from each other and two-dimensionally arranged in a horizontal direction that is parallel to the upper surface of the channel or a lower surface of the gate electrode, the plurality of first regions including the first region, and the second region of the gate insulating layer is between the plurality of first regions on a same plane as the plurality of first regions.
See Heo teaches use of ferroelectric in a transistor, see Fig. 6 “Referring to FIG. 6, a domain switching layer 300D may have a structure in which a plurality of ferroelectric material regions F and a plurality of anti-ferroelectric material regions AF are alternately arranged in a horizontal direction (laterally). The ratio and size of the ferroelectric material regions F and the anti-ferroelectric material regions AF are illustrative and may vary” “The ferroelectric material region F and the anti-ferroelectric material region AF may be formed by controlling doping concentration or a dopant differently as well as the annealing (annealing) control. For example, a part of the HfO-based amorphous thin film may have a first doping concentration and the other part may have a second doping concentration and, by annealing (heat-treating) them under a certain condition, a region having the first doping concentration may be made into the ferroelectric material region F and a region having the second doping concentration may be made into the anti-ferroelectric material region AF” “In at least one example embodiment, the domain switching layer 300A may be made to have no hysteresis characteristic by performing capacitance matching using a combination of at least one ferroelectric material region F and at least one anti-ferroelectric material region AF that are in contact with each other. Therefore, domain switching occurs in each of the ferroelectric material region F and at least one anti-ferroelectric material region AF and a switching characteristic of the logic switching device (logic transistor) may be improved by voltage amplification occurring during the domain switching. For example, an effect of further lowering a subthreshold swing (SS) value of the logic switching device (logic transistor) may be obtained. Since the domain switching layer 300A has a non-hysteretic behavior characteristic, an improved switching element with an ON/OFF non-memory characteristic may be obtained”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Katoh to include wherein the gate insulating layer includes a plurality of first regions that are spaced apart from each other and two-dimensionally arranged in a horizontal direction that is parallel to the upper surface of the channel or a lower surface of the gate electrode, the plurality of first regions including the first region, and the second region of the gate insulating layer is between the plurality of first regions on a same plane as the plurality of first regions.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to improve switching and hysteresis.
In regard to claim 3 Katoh and Heo as combined teaches wherein the second region of the gate insulating layer is between at least two adjacent first regions [see combination Heo] of the plurality of first regions, such that the at least two adjacent first regions are separated from each other by at least the second region.
In regard to claim 4 Katoh and Heo as combined does not specifically teach wherein a cross-sectional area of each first region of the plurality of first regions in a horizontal plane that is parallel to the upper surface of the channel or the lower surface of the gate electrode is greater than or equal to about 0.25 nm2 and less than or equal to about 1 μm2.
However see that the switching of the transistor depends on the dimensions of the gate i.e. for example wider gate means more current and longer gate helps higher voltage and see that the number of strips are adjustable for best performance, see determination of threshold behavior. See Katoh mentions sample dimensions “The Al layer and the underlying ferroelectric layer 12 are then patterned by a dry etching or milling process to have the same linear plan shape with a width of approximately 1 .mu.m as that of the gate electrode 13” “The two layers 15 and 16 are then patterned to have a rectangular plan shape with a width of approximately 1.5 .mu.m”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a cross-sectional area of each first region of the plurality of first regions in a horizontal plane that is parallel to the upper surface of the channel or the lower surface of the gate electrode is greater than or equal to about 0.25 nm2 and less than or equal to about 1 μm2 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 5 Katoh and Heo as combined teaches wherein the gate insulating layer includes a plurality of first regions having a stripe shape extending in a first direction [see combination Heo, see Heo Fig. 6], the plurality of first regions including the first region, and a plurality of second regions having a stripe shape extending in the first direction, the plurality of second regions including the second region, wherein the plurality of first regions and the plurality of second regions are alternately arranged [see combination Heo, see Heo Fig. 6] in a second direction that is perpendicular to the first direction within a plane of the gate insulating layer.
In regard to claim 6 Katoh and Heo as combined does not specifically teach wherein a width of each region of the plurality of first regions and the plurality of second regions in the second direction is about 0.5 nm or more and about 1 μm or less.
However see that the switching of the transistor depends on the dimensions of the gate i.e. for example wider gate means more current and longer gate helps higher voltage and see that the number of strips are adjustable for best performance, see determination of threshold behavior. See Katoh mentions sample dimensions “The Al layer and the underlying ferroelectric layer 12 are then patterned by a dry etching or milling process to have the same linear plan shape with a width of approximately 1 .mu.m as that of the gate electrode 13” “The two layers 15 and 16 are then patterned to have a rectangular plan shape with a width of approximately 1.5 .mu.m”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a width of each region of the plurality of first regions and the plurality of second regions in the second direction is about 0.5 nm or more and about 1 μm or less”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 7 Katoh teaches PZT [see claim 1, see Katoh teaches PZT] but does not teach hafnium oxide wherein the gate insulating layer comprises hafnium oxide, and the hafnium oxide is doped with at least one element selected from zirconium (Zr), silicon (Si), aluminum (Al), lanthanum (La), gadolinium (Gd), and yttrium (Y).
See Heo paragraph 0085 “The ferroelectric material region F and the anti-ferroelectric material region AF may be formed by controlling doping concentration or a dopant differently as well as the annealing (annealing) control. For example, a part of the HfO-based amorphous thin film may have a first doping concentration and the other part may have a second doping concentration and, by annealing (heat-treating) them under a certain condition, a region having the first doping concentration may be made into the ferroelectric material region F and a region having the second doping concentration may be made into the anti-ferroelectric material region AF. This effect may be obtained by using a different dopant instead of the doping concentration. Accordingly, in some cases, the ferroelectric material region F and the anti-ferroelectric material region AF may have different doping concentrations, and/or may include different dopants. When at least one of the ferroelectric material region F and the anti-ferroelectric material region AF includes a dopant, the dopant may include at least one of Si, aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), strontium (Sr), and hafnium (Hf)” .
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Katoh to include wherein the gate insulating layer comprises hafnium oxide, and the hafnium oxide is doped with at least one element selected from zirconium (Zr), silicon (Si), aluminum (Al), lanthanum (La), gadolinium (Gd), and yttrium (Y).
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that hafnium oxide is known to give good results to obtain controllable ferroelectric behavior.
In regard to claim 8 Katoh and Heo as combined in claim 7 does not specifically teach wherein, in the first region, a proportion of the ferroelectric crystal structure is about 65 at% or more and a proportion of the non-ferroelectric structure is about 35 at% or less, and in the second region, a proportion of the ferroelectric crystal structure is about 35 at% or less and a proportion of the non-ferroelectric structure is about 65 at% or more.
See Heo paragraph 0087 “In the above example embodiments, a volume ratio (vol %) of the ferroelectric material region F and the anti-ferroelectric material region AF in the domain switching layers 300A to 300E may be determined within a range from about 0.1:99.9 to about 99.9:0.1. For example, the vol % of the ferroelectric material region F and the anti-ferroelectric material region AF in the domain switching layers 300A to 300E may be determined within a range from about 10:90 to about 90:10. The vol % may be determined such that the domain switching layers 300A to 300E satisfy conditions that substantially do not have hysteresis characteristics”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein, in the first region, a proportion of the ferroelectric crystal structure is about 65 at% or more and a proportion of the non-ferroelectric structure is about 35 at% or less, and in the second region, a proportion of the ferroelectric crystal structure is about 35 at% or less and a proportion of the non-ferroelectric structure is about 65 at% or more ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 9 Katoh and Heo as combined in claim 7 does not specifically teach wherein, in the first region, a proportion of orthorhombic crystals is about 65 at% or more and a proportion of a sum of monoclinic crystals, tetragonal crystals, and amorphous structure is about 35 at% or less, and in the second region, a proportion of orthorhombic crystals is about 35 at% or less and a proportion of a sum of monoclinic crystals, tetragonal crystals, and amorphous structure is about 65 at% or more.
See Heo paragraph 0084 “In the above example embodiments, the ferroelectric material region F and the anti-ferroelectric material region AF include an identical base material, but may have different crystalline phases. The ferroelectric material region F and the anti-ferroelectric material region AF may include an identical material and may have different crystalline phases so that the ferroelectric material region F may exhibit a ferroelectric property and the anti-ferroelectric material region AF may exhibit an anti-ferroelectric property. For example, the ferroelectric material region F may have an orthorhombic crystalline phase, and the anti-ferroelectric material region AF may have a tetragonal crystalline phase. For example, the ferroelectric material region F and the anti-ferroelectric material region AF may include a Hf-based oxide or a Zr-based oxide. For example, an HfO-based amorphous thin film is formed and then, through annealing (heat treatment) control, a part thereof may be made into the ferroelectric material region F having an orthorhombic crystalline phase and another part thereof may be made into the anti-ferroelectric material region AF having a tetragonal crystalline phase”, “In the above example embodiments, a volume ratio (vol %) of the ferroelectric material region F and the anti-ferroelectric material region AF in the domain switching layers 300A to 300E may be determined within a range from about 0.1:99.9 to about 99.9:0.1. For example, the vol % of the ferroelectric material region F and the anti-ferroelectric material region AF in the domain switching layers 300A to 300E may be determined within a range from about 10:90 to about 90:10. The vol % may be determined such that the domain switching layers 300A to 300E satisfy conditions that substantially do not have hysteresis characteristics”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein, in the first region, a proportion of orthorhombic crystals is about 65 at% or more and a proportion of a sum of monoclinic crystals, tetragonal crystals, and amorphous structure is about 35 at% or less, and in the second region, a proportion of orthorhombic crystals is about 35 at% or less and a proportion of a sum of monoclinic crystals, tetragonal crystals, and amorphous structure is about 65 at% or more ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 14 Katoh does not specifically teach further comprising: a non-ferroelectric layer between the channel and the gate insulating layer, wherein the non-ferroelectric layer comprises at least one of a paraelectric material, an antiferroelectric material, or an amorphous material.
However see Katoh embodiment of Fig. 14 see “In the semiconductor device according to the fifth embodiment, similar to the first embodiment, a thin dielectric layer 9 of SiO.sub.2 is formed to be contacted with the exposed surface of the substrate 3 in the device region 1. However, unlike the first embodiment, the dielectric layer 9 has no penetrating window”.
See Heo Fig. 7 uses not only F and AF alternately in the horizontal direction, but also has and addintional AF and F in the vertical direction isolating the Gate 500, and see paragraphs 0084-0087 the material is based on Hf-based oxide and characteristics are based on “In the above example embodiments, the ferroelectric material region F and the anti-ferroelectric material region AF include an identical base material, but may have different crystalline phases” “The ferroelectric material region F and the anti-ferroelectric material region AF may be formed by controlling doping concentration or a dopant differently as well as the annealing (annealing) control”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Katoh to include further comprising: a non-ferroelectric layer between the channel and the gate insulating layer, wherein the non-ferroelectric layer comprises at least one of a paraelectric material, an antiferroelectric material, or an amorphous material.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that adding a horizontal layers in addition to vertical stripes gives finer control of threshold and also leakage.
In regard to claim 15 Katoh does not specifically teach further comprising a non-ferroelectric layer between the gate insulating layer and the gate electrode, wherein the non-ferroelectric layer comprises at least one of a paraelectric material, an antiferroelectric material, or an amorphous material.
However see Katoh embodiment of Fig. 14 see “In the semiconductor device according to the fifth embodiment, similar to the first embodiment, a thin dielectric layer 9 of SiO.sub.2 is formed to be contacted with the exposed surface of the substrate 3 in the device region 1. However, unlike the first embodiment, the dielectric layer 9 has no penetrating window”.
See Heo Fig. 7 uses not only F and AF alternately in the horizontal direction, but also has and addintional AF and F in the vertical direction isolating the Gate 500, and see paragraphs 0084-0087 the material is based on Hf-based oxide and characteristics are based on “In the above example embodiments, the ferroelectric material region F and the anti-ferroelectric material region AF include an identical base material, but may have different crystalline phases” “The ferroelectric material region F and the anti-ferroelectric material region AF may be formed by controlling doping concentration or a dopant differently as well as the annealing (annealing) control”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Katoh to include further comprising a non-ferroelectric layer between the gate insulating layer and the gate electrode, wherein the non-ferroelectric layer comprises at least one of a paraelectric material, an antiferroelectric material, or an amorphous material.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that adding a horizontal layers in addition to vertical stripes gives finer control of threshold and also leakage.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katoh (US 6087687 A) in view of Huang et al. (CN 111291877 A) hereafter referred to as Huang
In regard to claim 20 Katoh teaches an electronic apparatus [see Fig. 16 “The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device with a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) a gate insulator of which includes a ferroelectric, and a fabrication method of the device” “A semiconductor device with a MISFET according to a sixth embodiment is shown in FIGS. 5 and 16, in which the substrate 3, the device region 1, the isolation region 2, and the field oxide layer 10 are the same in configuration as those in the first embodiment”], comprising:
a field effect transistor [see Fig. 16]; and
wherein the field effect transistor includes a source region [“A source region 5 and a drain region 6 of the MISFET are formed in the surface region of the substrate 3 in the device region 1. The source and drain regions 5 and 6 are symmetrically located at each side of the gate electrode 13. In other words, the gate electrode 13 is placed between the source and drain regions 5 and 6”], a drain region [“drain region 6”], a channel [“A channel region is formed in the surface region of the substrate 3 between the source and drain regions 5 and 6 beneath the gate electrode 13”] between the source region and the drain region,
a gate insulating layer [“A SiO.sub.2 layer 8 is formed on the whole exposed surface of the substrate 10 to be contacted therewith in the device region 1. The periphery of the layer 8 is joined to the opposing end of the field oxide layer 10” “A patterned ferroelectric PZT layer 7 is formed on the substrate 3 to be buried in the window Ba of the SiO.sub.2 layer 8”] configured to cover an upper surface of the channel, and a gate electrode [see Fig. 16 “gate electrode 19 extends along the longitudinal axis of the device region 1 to be contacted with the underlying layers 7 and B”] configured to cover an upper surface of the gate insulating layer,
wherein the gate insulating layer includes a first region [“A patterned ferroelectric PZT layer 7 is formed on the substrate 3 to be buried in the window Ba of the SiO.sub.2 layer 8”] where a ferroelectric crystal structure is dominant, and a second region [“SiO.sub.2 layer 8”] where a non-ferroelectric structure is dominant, and
the gate electrode includes a first pattern region facing the first region [see Fig. 16 “gate electrode 19 extends along the longitudinal axis of the device region 1 to be contacted with the underlying layers 7 and B”] of the gate insulating layer, and a second pattern region [see Fig. 16] facing the second region of the gate insulating layer
but does not specifically state a capacitor electrically connected to the field effect transistor.
However the Examiner notes that the claim is very broad and is satisfied by Katoh because inherently a MISFET contains at least 4 capacitors i.e. gate to channel, gate to source, gate to drain and gate to body and they are all electrically connected to the MISFET.
In the interest of compact prosecution, the Examiner provides a secondary reference.
See Huang teaches a neuron circuit see Fig. 1 see “As shown in FIG. 1, the embodiment is based on HfO2 doped lateral inhibition neuron circuit realize ferroelectric transistor FeFET of the Zr (HZO), comprises a capacitor Cmem, a reset tube M1, tube M2 positive feedback, two-stage serially connected inverters I1 and I2, wherein Ferroelectric transistor FeFET is an N-type FeFET device, for realizing lateral inhibition function” “the input current of the neuron N2 is higher, the charge accumulated on the film capacitor after a period of time, the more the membrane potential N2Vmem is higher, i.e., the gate voltage of the FeFET is higher, the larger the channel conductance of the FeFET. charge accumulated on the film capacitor Cmem of the neuron N1 through FeFET discharge more”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Katoh to include a capacitor electrically connected to the field effect transistor.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to store charge for use in a circuit, such as a neuron circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SITARAMARAO S YECHURI/Primary Examiner, Art Unit 2893