DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group II, claims 14-21 in the reply filed on 3/4/2026 is acknowledged.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “270” in Figure 2B and 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“optical hardware configured to obtain positions” in claim 14 and “second optical hardware configured to measure positions” in claim 16 and 18. The specification discloses in paragraph 0027 that the corresponding structure to perform the recited function is that “Thereafter, metrology can be performed by using an optical device 420 such as a microscope, camera, or beam splitter that is capable of seeing through the source substrate 1030. This may include an Infrared (IR) microscope or a vision system to look through IR transparent substrates”
“control unit configured to determined” in claim 14 and 16 and 18. The specification discloses in paragraph 0052 that the corresponding structure to perform the recited function is that “The controller 160 can include a processor (for example, a central processing unit of a microprocessor or microcontroller), a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like.” See also specification paragraph 0076, further detail as to the controller including one or more processor, ASIC and storage elements.
“pickup hardware configured to transfer” in claim 16. The specification discloses in paragraph 0037-47 that the corresponding structure to perform the recited function can include “pick-up heads 144” and “pick-up head carriage 142”.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "the controller" in line 1. There is insufficient antecedent basis for this limitation in the claim. Parent claims 16 and 14 make reference to “a control unit” and do not reference “a controller”. It appears that the term “the controller” is actually intended to reference the previously introduce control unit. The examiner suggests amending claim 20 to recite “the control unit”.
Claim 21 is rejected based on its dependency from claim 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (US 20210313211 A1) and Crespin (US 20110058731 A1).
As to claim 14, Yamauchi discloses a bonding system (chip supply device 10 and bonding device 30) comprising:
a stage (a frame holder 119 that holds the sheet holding frame 112) configured to hold a source substrate (a sheet holding frame 112 that holds a sheet TE on which a plurality of chips CP is stuck), the source substrate includes alignment marks (“alignment marks MC1a, MC1b, MC2a, and MC2b”);
an optical hardware (“chip imaging device 15” and “imaging devices 35a and 35b, an imaging device 41, camera F-direction drivers 365, and a camera Z-direction driver 363”) configured to obtain positions of the alignment marks (“[0092] The supplied chip imaging device 15 is arranged above (+Z-direction) the chip supply 11 in the chip supply device 10. The supplied chip imaging device 15 images an image of the chip CP pushed out above the cover 114 by the pick-up mechanism 111.”); and
a control unit (controller 90, controller 7090, etc.) configured to determine alignment marks placement errors (“a relative positional error”) based on offsets between the positions of the alignment marks in the X, Y, and θ directions. See paragraph 0108, 0119-0120 and 0162, disclosing:
[0108] The imaging devices 35a and 35b acquire imaged images including images of the alignment marks MC2a and MC2b, which are disposed on the chip CP, and images of alignment marks (first alignment marks) MC1a and MC1b that are disposed on the substrate WT. The controller 90 recognizes a relative position of the chip CP with respect to the substrate WT in a direction parallel with a surface of the substrate WT on which the chip CP is mounted, based on the image data acquired by the imaging devices 35a and 35b. The imaging devices 35a and 35b include image sensors 351a and 351b, optical systems 352a and 352b, and coaxial illumination systems (not illustrated), respectively. The imaging devices 35a and 35b respectively acquire image data relating to reflected light of illuminating light (for example, infrared light) that is emitted from light sources (not illustrated) of the coaxial illumination systems. Note that illuminating light emitted in horizontal directions from the coaxial illumination systems of the imaging devices 35a and 35b is reflected by the inclined surfaces 337a and 337b of the mirror 337, respectively, and the traveling directions thereof are changed to the vertically upward direction. The light reflected by the mirror 337 travels toward imaging target portions including the chip CP, which is held by the head 33H, and the substrate WT, which is arranged in such a manner as to face the chip CP and is reflected by the respective imaging target portions. Note that the alignment marks MC2a and MC2b are disposed on the imaging target portions of the chip CP and the alignment marks MC1a and MC1b are disposed on the imaging target portions of the substrate WT. The reflected light from the respective imaging target portions of the chip CP and the substrate WT travels vertically downward, is subsequently reflected by the inclined surfaces 337a and 337b of the mirror 337 again, has traveling directions thereof changed to horizontal directions, and reaches the imaging devices 35a and 35b. In this way, the imaging devices 35a and 35b acquire image data of the respective imaging target portions of the chip CP and the substrate WT.
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[0119] The controller 90 includes a micro processing unit (MPU), a main storage, an auxiliary storage, an interface, and a bus connecting the components to one another. In this configuration, the main storage is constituted by a volatile memory and is used as a working area for the MPU. The auxiliary storage is constituted by a nonvolatile memory and stores programs that the MPU executes. The auxiliary storage also stores information indicating first distance and second distance, which will be described later. The controller 90 is connected to the supplied chip imaging device 15, the imaging devices 35a and 35b, the imaging device 41, the cleaned chip imaging device 54, the Z-direction driver 34, the θ-direction driver 37, the piezo-actuators 333, the support driver 432b, the X-direction drivers 321, the Y-direction drivers 323, the plate driver 392, the arm drivers 395, the pick-up mechanism 111, the holding frame driver 113, the chip stage driver 53, the support driver 512, and the cleaning head 52, as illustrated in FIG. 11. The interface converts imaged image signals input from the supplied chip imaging device 15, the imaging devices 35a and 35b, the imaging device 41, and the cleaned chip imaging device 54 to imaged image information and outputs the imaged image information to the bus. In addition, the MPU, by reading programs stored in the auxiliary storage into the main storage and executing the programs, respectively outputs control signals to the Z-direction driver 34, the θ-direction driver 37, the piezo-actuators 333, the support driver 432b, the X-direction drivers 321, the Y-direction drivers 323, the plate driver 392, the arm drivers 395, the pick-up mechanism 111, the holding frame driver 113, the chip stage driver 53, the support driver 512, and the cleaning head 52 via the interface.
[0120] The controller 90 calculates a relative positional error between a substrate WT and a chip CP from images that are acquired by imaging alignment marks MC1a, MC1b, MC2a, and MC2b with the substrate WT and the chip CP in contact with each other. The controller 90 makes the Z-direction driver 34 and the θ-direction driver 37 of the head driver 36 and the X-direction drivers 321 and the Y-direction drivers 323 of the stage 31 correct the position and attitude of the chip CP with respect to the substrate WT according to the calculated relative positional error. The controller 90 also makes the holding frame driver 113 correct the position and the inclination about the Z-axis of the sheet holding frame 112 according to the position and attitude of a chip CP to be cut out by the pick-up mechanism 111. In this processing, the controller 90 recognizes the position and attitude of the chip CP, based on image data input from the supplied chip imaging device 15. Further, the controller 90 further makes the chip stage driver 53 correct the position and the inclination about the Z-axis of the chip stage 51 according to the position and attitude of a chip CP placed on the chip stage 51. In this processing, the controller 90 recognizes the position and attitude of the chip CP, based on image data input from the cleaned chip imaging device 54.
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[0162] The controller 7090 calculates a relative positional error between the flexible substrate FT and a chip CP from images that are acquired by imaging the alignment marks MC1a and MC1b on the flexible substrate FT and the alignment marks MC2a and MC2b on the chip CP, using the imaging devices 7351, with the light path converting member 7353, which is held by the transportation head 7394, arranged between the flexible substrate FT and the chip CP. The controller 7090 makes the head driver 36 and the support driver 7320 correct the position and attitude of the chip CP with respect to the flexible substrate FT by outputting a control signal to the head driver 36 and the support driver 7320. The controller 7090 calculates a relative positional error between the flexible substrate FT and a chip CP from images that are acquired by imaging the alignment marks MC1a and MC1b on the flexible substrate FT and the alignment marks MC2a and MC2b on the chip CP, using the imaging devices 7411, with the flexible substrate FT and the chip CP in contact with each other. The controller 7090 makes the head driver 36 and the support driver 7320 correct the position and attitude of the chip CP with respect to the flexible substrate FT by outputting a control signal to the head driver 36 and the support driver 7320.
See also marked up Figure 2, below:
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Yamauchi, however, does not disclose the source substrate includes active side alignment marks on an active side, first non-active side alignment marks and second non-active side alignment marks on a non-active side, or that the optical hardware is configured to obtain positions of the active side alignment marks and positions of the first non-active side alignment marks of the source substrate, or that the control unit configured to determine alignment marks placement errors based on offsets between the positions of the active-side alignment marks and the positions of the first non-active side alignment marks in the X, Y, and θ directions.
However, Crespin, which is directed to alignment metrology for semiconductor manufacturing, especially for semiconductor exposure, and also discloses and makes obvious that the source substrate includes active side alignment marks on an active side, first non-active side alignment marks and second non-active side alignment marks on a non-active side (“The substrate has a frontside with frontside alignment marks and a backside with backside alignment marks.”), and thus also make obvious that the optical hardware (via a “lower optical system 66” and an “upper optical system 76”) is configured to obtain positions of the active side alignment marks and positions of the first non-active side alignment marks of the source substrate, and that the control unit (controller 80) is configured to determine alignment marks placement errors based on offsets between the positions of the active-side alignment marks and the positions of the first non-active side alignment marks in the X, Y, and θ directions.
See Figures 2 and 9, below:
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See especially paragraphs 0011-12, disclosing:
[0002] The present invention relates to alignment metrology, and in particular to apparatus and methods for measuring alignment and/or overlay accuracy of images formed in or on a substrate.
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[0011] A first aspect of the invention is an apparatus that includes a stage assembly capable of movably supporting a substrate. The substrate has a frontside with frontside alignment marks and a backside with backside alignment marks. An upper optical system is movably arranged above the stage assembly and the frontside of the substrate so as to be in optical communication with the frontside of the substrate to form an image of one or more of the frontside alignment marks. A lower optical system is arranged relative to the upper optical system and beneath the stage assembly so as to be in optical communication with the backside of the substrate to form an image of one or more of the backside alignment marks. The images of the frontside and backside alignment marks are captured by a frame grabber coupled to the upper and lower optical systems. The images are then processed (e.g., in a central processing unit connected to the frame grabber) to determine the relative positions (i.e., the alignment) of the alignment marks, and hence the quality of the alignment and/or overlay performance of the tool that formed the alignment marks on the substrate.
[0012] A second aspect of the invention is a method of measuring a substrate having a frontside with frontside alignment marks and a backside with backside alignment marks. The method includes capturing a first image of a select frontside alignment mark with a an upper optical system arranged adjacent the frontside of the substrate. The method also includes capturing a second image of a select backside alignment mark with a lower optical system arranged adjacent the backside of the substrate and aligned relative to the upper optical system. The method also includes processing the first and second images to determine a lateral offset between the select frontside and backside alignment marks.
See also paragraphs 0030-31 and 41, disclosing:
[0030] FIG. 2 is a side view of an example substrate 50. Substrate 50 includes front-side alignment marks 60 on frontside 52 and corresponding backside alignment marks 62 (not shown in FIG. 1) on backside 54. In an example embodiment, frontside and backside alignment marks have a size on the scale of microns or tens of microns.
[0031] With reference again to FIG. 1, residing above (i.e., adjacent) substrate frontside 52 (or platen upper surface 42 when the substrate is absent) is an upper optical system 66 with an axis A1. Residing beneath (i.e., adjacent) substrate backside 54 (or platen lower surface 44 when the substrate is absent) is a lower optical system 76 with an axis A2. In an example embodiment, a controller 80 controls the operation of apparatus 10 and/or processing information therefrom coupled to at least one of upper optical system 66, lower optical system 76, and stage assembly 18. Further in an example embodiment, a display 84 and an input device 86 are coupled to controller 80.
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[0041] Stage assembly 18 must permit backside alignment marks 62 to be viewed by lower optical system 76. Accordingly, in one example embodiment substrate stage 20 includes an aperture 127 (the inner walls of which are illustrated by dashed lines 128 in FIG. 3) through which backside 54 of substrate 50 can be viewed by lower optical system 76.
Crespin teaches the benefits of these additional measurement in paragraphs 0099-0100, teaching that:
[0099] In an example embodiment, the alignment measurement data for each set of frontside and backside alignment marks is stored in memory unit 504. Once the measurement data for the desired number of sites has been collected, the data is processed by controller 80 (e.g., by microprocessor 502 therein). The data processing includes, for example, listing the displacement values (.DELTA.X, .DELTA.Y) for each site, and calculating the average and the standard deviation for displacement values.
[0100] An advantage of performing more than just a few measurements per substrate is that enough data can be taken to ascertain the root causes of any alignment and/or overlay errors, such as from mask run-out, coating non-uniformities, substrate non-flatness, and grid errors. The ability to characterize and quantify alignment and/or overlay is important in modern semiconductor manufacturing because it allows one to redress the source of the errors to improve tool performance, and improved tool performance generally leads to improved semiconductor device performance.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized wherein the source substrate includes active side alignment marks on an active side, first non-active side alignment marks and second non-active side alignment marks on a non-active side, and that the optical hardware is configured to obtain positions of the active side alignment marks and positions of the first non-active side alignment marks of the source substrate, and that the control unit configured to determine alignment marks placement errors based on offsets between the positions of the active-side alignment marks and the positions of the first non-active side alignment marks in the X, Y, and θ directions as taught by Crespin because the ability to characterize and quantify alignment and/or overlay is important in modern semiconductor manufacturing because it allows one to redress the source of the errors to improve tool performance, and improved tool performance generally leads to improved semiconductor device performance such as from errors from mask run-out, coating non-uniformities, substrate non-flatness, and grid errors.
As to claim 15, Yamauchi discloses wherein the source substrate is singulated to form a plurality of dies (see paragraph 0089, disclosing “The chip supply device 10 cuts a chip CP out of a plurality of chips CP that was produced by dicing a substrate and supplies the bonding device 30 with the chip CP.”),
Yamauchi does not disclose wherein each of the dies of the plurality of dies includes at least one of the second non-active side alignment marks, although Yamauchi does disclose that the dies include a plurality of alignment marks, such as marks MC1a and MC1b on chip CP (see paragraph 0108, disclosing “alignment marks MC2a and MC2b, which are disposed on the chip CP”).
However, Crespin as incorporated above discloses wherein each of the dies of the plurality of dies includes at least one of the second non-active side alignment marks. See the citations in claim 14 above, such as especially Figure 2.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized wherein each of the dies of the plurality of dies includes at least one of the second non-active side alignment marks as taught by Crespin because the ability to characterize and quantify alignment and/or overlay is important in modern semiconductor manufacturing because it allows one to redress the source of the errors to improve tool performance, and improved tool performance generally leads to improved semiconductor device performance such as from errors from mask run-out, coating non-uniformities, substrate non-flatness, and grid errors.
Claim(s) 16 and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (US 20210313211 A1) and Crespin (US 20110058731 A1) as applied to claims 14-15 above, and further in view of Nagatomo (US 20220216077 A1) and Mochizuki (US 20130068824 A1).
As to claim 16, Yamauchi discloses a bonding head (bonder 33 which includes head driver 36 and head 33H), pickup hardware (“The chip transportation device 39 includes two long plates 391, two arms 394, two chip holders 393 each of which is disposed at a tip portion of one of the arms 394, and a plate driver 392 that rotation-drives the two plates 391 at the same time”) configured to transfer the plurality of dies to the bonding head, and a second optical hardware configured to measure positions of the alignment mark (“chip imaging device 15” and “imaging devices 35a and 35b, an imaging device 41, camera F-direction drivers 365, and a camera Z-direction driver 363”, in essence, four pieces of optical hardware, any pair of which can be a first and second optical hardware), wherein the control unit (controller 90 or 7090) estimates alignment marks placement errors based on the alignment marks (“a relative positional error”).
Additionally, Crespin discloses using optical hardware configured to measure positions of second non-active side alignment marks on the plurality of dies, and provide the positions of the second non-active side alignment marks to the control unit, wherein the control unit estimates second alignment mark placement errors of the second non-active side alignment marks based on the alignment mark placement errors, and wherein the control unit determines die placement errors based on offsets between the positions of the second non-active side alignment marks in the X, Y, and θ directions.
However, while Yamauchi and Crespin disclose many of the features of claim 16, Yamauchi and Crespin do not disclose a plurality of bonding heads, wherein each of the bonding heads includes one or more bonding head alignment marks, or a plurality of pickup hardware, Therefore, Yamauchi and Crespin do not disclose the full limitation of further comprising: a plurality of bonding heads, wherein each of the bonding heads includes one or more bonding head alignment marks; a plurality of pickup hardware configured to transfer the plurality of dies to the plurality of bonding heads; a second optical hardware configured to measure positions of second non-active side alignment marks on the plurality of dies and positions of bonding head alignment marks, and provide the positions of the second non-active side alignment marks and the positions of the bonding head alignment marks to the control unit, wherein the control unit estimates second alignment mark placement errors of the second non-active side alignment marks based on the alignment mark placement errors, and wherein the control unit determines die placement errors based on offsets between the positions of the second non-active side alignment marks and the positions of bonding head alignment marks in the X, Y, and θ directions.
However, Mochizuki discloses using a plurality of bonding heads (“bonding heads 41A and 41B.”) and a plurality of pickup hardware (pickup heads 21A and 21B). See especially Figure 7, below:
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See also paragraphs 0061-0068, describing the second embodiment and its benefits:
Second Embodiment
[0061] FIG. 7 is a top view schematically showing a die bonder 10A according to a second embodiment of the present invention. The die bonder 10A includes a plurality of conveyance lanes (two in the second embodiment) and a plurality of bonding heads (two in the second embodiment). The first difference between the die bonder 10A and the die bonder 10 is that the conveyance unit 5 of the die bonder 10A has two conveyance lanes 51 and 52. The second difference is that the die bonder 10A has two mount units 20A and 20B each formed of the pickup unit 2, the alignment unit 3 and the bonding unit 4. Each code of the respective mount units 20A and 20B includes the one that denotes the same structure or function as that of the die bonder 10, and the suffix A or B indicating each line. That is, the die bonder 10A includes a plurality of conveyance lanes 51 and 52, and a plurality of bonding heads 41A and 41B. As the operations of the bonding heads and the pickup heads which constitute the mount units 20A and 20B according to the second embodiment are the same as those of the first embodiment, all the operations of the mount unit will be expressed compehensively, for example, as "mounted in the mount unit" for the purpose of simplifying the explanation so long as no problem occurs.
[0062] The third difference is that the pickup heads 21A and 21B of the die bonder 10A pick up the dies D from the wafer 11, and move in the X direction to place the dies D on alignment stages 31A and 31B provided at an intersection of trajectories of the bonding heads 41A and 41B.
[0063] The die bonder is provided with substrate conveyance pallets 91, 92 and 93, and bonding stages BS1, BS2 and BS3.
[0064] Likewise the first embodiment, the second embodiment makes each moving distance of the bonding heads 41A and 41B short, and includes the alignment stages 31A and 31B for reducing the processing time. However, the die D may be picked up from the wafer directly by the bonding head 41 without providing the alignment stages 31A and 31B.
[0065] The first characteristic of the second embodiment is the classification control unit or classification control step capable of efficiently operating two lines of the mount units on one of the two conveyance lanes.
[0066] As a result, the die bonder with two conveyance lanes and two bonding heads is capable of efficiently performing the grade processing of the wafer without being removed.
[0067] The second characteristic is that the classification control unit or the classification control step which returns the class die D (class substrate P) at least at one side to the supply side on at least one of the two conveyance lanes for carry out as described in the first embodiment.
[0068] As a result, the die bonder with two conveyance lanes and two bonding heads is capable of performing the grade processing although the wafer has two to four grades (classes) or the wafer has two types of dies with two corresponding grades (classes).
Additionally, Nagatomo disclose that wherein each of the bonding head includes one or more bonding head alignment marks (paragraph 0035, disclosing “the chip carrying unit 300 may include a Y-axis slider 301, a bonding head or bonding head system 310, a vision head or vision head system 320, and a fiducial mark arrangement unit or system 330.”) Nagatomo discloses in paragraph 0044 that these marks allow for “A position error of the semiconductor chip 2 may be detected by using an image obtained by capturing the semiconductor chip 2 supported by the bonding head 310.”
See marked up Figure 1, below:
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See paragraph 0035 and 0040-45, disclosing:
[0035] Referring to FIGS. 2 and 3, the chip carrying unit 300 may include a Y-axis slider 301, a bonding head or bonding head system 310, a vision head or vision head system 320, and a fiducial mark arrangement unit or system 330. The Y-axis slider 301 is a moving unit movable in the Y-axis direction, and may include, for example, a slider having a gantry structure. The bonding head 310, the vision head 320, and the fiducial mark arrangement unit 330 may be fixed to the Y-axis slider 301. The Y-axis slider 301 may move the bonding head 310, the vision head 320, and the fiducial mark arrangement unit 330 simultaneously in the Y-axis direction.
…
[0040] The fiducial mark arrangement unit 330 may include a fiducial mark 331. The fiducial mark 331 is a mark indicating a fiducial position for correcting a position and a posture of each of the semiconductor chip 2 and the substrate 3.
[0041] The fiducial mark arrangement unit 330 includes the fiducial mark 331, a mark fixing part 332, and a mirror 333. The fiducial mark 331 may be configured to move together with the camera 321. From the time of picking up the semiconductor chip 2 to the time of bonding the same to the substrate 3, the fiducial mark 331 may be included within a field of view (that is, a capturing range) of the camera 321, and may be arranged in a position in which an image thereof is always able to be captured by the camera 321. The fiducial mark 331 is held by a structure in which a relative positional variation with the Y-axis linear encoder 302 for grasping a Y-coordinate of the camera 321 is sufficiently suppressed. That is, the fiducial mark 331 may be fixed at a certain position so that a distance from the Y-axis linear encoder 302 does not change (that is, a relative position to the Y-axis linear encoder 302 becomes constant). For example, the mark fixing part 332 may be arranged at a position at a certain distance from the Y-axis linear encoder 302, and the fiducial mark 331 may be arranged on an end of the mark fixing part 332. For example, the mark fixing part 332 extends from the Y-axis slider 301 in the Z-axis direction, and the fiducial mark 331 arranged on the mark fixing part 332 moves in the Y-axis direction together with the mark fixing part 332. The mirror 333 may be arranged on an optical path of the camera 321, and may branch an optical path from a portion of the field of view of the camera 321 so that an image of the fiducial mark 331 may be captured by the camera 321. In addition, an auxiliary lighting device for illuminating the fiducial mark 331 may be included. The auxiliary lighting device may include at least one light source. For example, the auxiliary lighting device may illuminate the fiducial mark 331 from a back side. The auxiliary lighting device may be controlled independently of a lighting for capturing the semiconductor chip 2.
[0042] FIG. 4 is a configuration diagram of the fiducial mark 331 and the mirror 333. FIG. 5 is a schematic diagram showing an image including the fiducial mark 331 captured by the camera 321.
[0043] Referring to FIGS. 4 and 5, the mirror 333 may be mounted on an end of the camera lens 322, and the camera lens 322 may capture the image of the fiducial mark 331 through the mirror 333. The fiducial mark 331 is arranged at a position spaced apart from the camera 321 by a certain distance. In particular, the fiducial mark 331 may be arranged at a position that becomes a focal length of the camera 321. For example, as shown in FIG. 5, a field of view 329 of the camera 321 may include an image of a bottom surface of the semiconductor chip 2 or an image of the substrate 3, and an image of the fiducial mark 331. That is, an image obtained by capturing, by the camera 321, the semiconductor chip 2 held by the bonding head 310 may include the semiconductor chip 2 and the fiducial mark 331, and an image obtained by capturing, by the camera 321, the substrate 3 mounted on the bonding stage 600 may include the substrate 3 and the fiducial mark 331. In FIG. 5, the fiducial mark 331 is illustrated in an upper left portion of the field of view 329 of the camera 321 as an example, but may be at other positions in the field of view 329 of the camera 321 as long as a fiducial position may be indicated. In addition, the fiducial mark 331 is illustrated as a cross mark as an example, but may be a round mark or a mark having other arbitrary shape as long as a reference position may be indicated.
[0044] Referring back to FIGS. 1 and 2, the optical unit 400 may include an optical system adjusting the optical path of the camera 321. In example embodiments, while the bonding head 310 picks up and holds the semiconductor chip 2, the camera 321 may capture an image of the mounting surface of the semiconductor chip 2 through the optical unit 400. A position error of the semiconductor chip 2 may be detected by using an image obtained by capturing the semiconductor chip 2 supported by the bonding head 310.
[0045] The camera 321 of the vision head 320 is arranged to capture an image in the same direction (that is, the Z-axis direction) as the mounting direction of the bonding head 310, and the optical unit 400 enables the camera 321 to capture the mounting surface opposite to an adsorbing surface of the semiconductor chip 2 adsorbed by the bonding head 310. The optical unit 400 may enable the camera 321 to capture the mounting surface in a direction from the lower side to the upper side in the Z-axis direction. The optical unit 400 may be fixed to the base 100 and may be or may not be connected to an actuator. The optical unit 400 may be arranged below a movement path of the chip carrying unit 300 in the Y-axis direction, wherein the movement path of the chip carrying unit 300 may be extending from the flip chip unit 200 to the bonding stage 600. The flip chip unit 200 picks up the semiconductor chip 2 at a pick-up position, and also the optical unit 400 may be arranged near the pick-up position of the flip chip unit 200 to capture the image of the semiconductor chip 2 held by the bonding head 310. An optical system inside the optical unit 400 may include a telecentric relay optical system, and may transmit an image of the bottom surface of the semiconductor chip 2 with the same optical performance as when an image is captured directly from below by the camera 321. The optical unit 400 may include a prism and/or a telecentric feature to transmit light or images. In addition, the optical unit 400 may be implemented with an optical system other than a telecentric system by designing the camera lens 322 mounted on the camera 321 and the optical unit 400 exclusively. In example embodiments, the optical unit 400 may also include an optical system having a variable optical magnification. For example, the optical unit 400 may include an optical system capable of adjusting an optical magnification as necessary.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized the full limitation of further comprising: a plurality of bonding heads, wherein each of the bonding heads includes one or more bonding head alignment marks; a plurality of pickup hardware configured to transfer the plurality of dies to the plurality of bonding heads; a second optical hardware configured to measure positions of second non-active side alignment marks on the plurality of dies and positions of bonding head alignment marks, and provide the positions of the second non-active side alignment marks and the positions of the bonding head alignment marks to the control unit, wherein the control unit estimates second alignment mark placement errors of the second non-active side alignment marks based on the alignment mark placement errors, and wherein the control unit determines die placement errors based on offsets between the positions of the second non-active side alignment marks and the positions of bonding head alignment marks in the X, Y, and θ directions by utilizing the plurality of bonding heads and pickup hardware of Mochizuki because Mochizuki discloses that using a plurality of bonding heads and pickup hardware would be capable of efficiently performing the grade processing of the wafer without being removed and the bonding heads includes one or more bonding head alignment marks of Nagatomo such that a position error of the semiconductor chip may be detected by using an image obtained by capturing the semiconductor chip supported by the bonding head.
As to claim 18, Yamauchi and Crespin does not disclose wherein, the second optical hardware further configured to measures positions of bonding head fiducials on the plurality of bonding heads and positions of destination fiducials on a destination substrate; and the control unit further configured to determine bonding head alignment errors based on offsets between the positions of the bonding head fiducials and the positions of the destination fiducials in the X, Y, and θ directions. Yamauchi, however, does disclose optical hardware for imaging positions of destination fiducials on a destination substrate teaching “simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP)” (see abstract, et al).
However, Nagatomo as combined in claim 16 would function wherein, the second optical hardware further configured to measures positions of bonding head fiducials on the plurality of bonding heads and positions of destination fiducials on a destination substrate; and the control unit further configured to determine bonding head alignment errors based on offsets between the positions of the bonding head fiducials and the positions of the destination fiducials in the X, Y, and θ directions. See especially Nagatomo, which discloses a substrate capturing position in paragraph 0074 that:
[0074] For example, in operation S105, the Y-axis slider 301 of the chip carrying unit 300 is moved in the Y-axis direction, the bonding stage 600 is moved in the X-axis direction, and the bonding head 310 and the vision head 320 are stopped at a certain position above the bonding stage 600. That is, the bonding head 310 and the bonding stage 600 are moved so that the semiconductor chip 2 held by the bonding head 310 and the substrate 3 on the bonding stage 600 are side by side on the Z-axis. When the semiconductor chip 2 held by the bonding head 310 and the substrate 3 on the bonding stage 600 are arranged side by side on the Z-axis, a position of the chip carrying unit 300 in the Y-axis direction (or positions of the bonding head 310 and the vision head 320 in the Y-axis direction) may be referred to as a “substrate capturing position”, and a state of the bonding head 310 and the vision head 320 in the substrate capturing position may be referred to as a “substrate capturing state”. In the substrate capturing position, the camera 321 of the vision head 320 captures an image of a surface (mounting surface) of the substrate 3 on the bonding stage 600. The controller 700 obtains a position of the substrate 3 or a rotation angle around the Z-axis from the captured image of the substrate 3. An error which may occur due to positional deviation of the camera 321 may be removed by using a distance from the fiducial mark 331 reflected in the field of view of the camera 321 in an operation of obtaining the position of the substrate 3 or the rotation angle around the Z-axis from the image of the substrate 3, which is captured.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized wherein, the second optical hardware further configured to measures positions of bonding head fiducials on the plurality of bonding heads and positions of destination fiducials on a destination substrate; and the control unit further configured to determine bonding head alignment errors based on offsets between the positions of the bonding head fiducials and the positions of the destination fiducials in the X, Y, and θ directions by using the bonding head fiducial marks of Nagatomo such that a position error of the semiconductor chip may be detected by using an image obtained by capturing the semiconductor chip supported by the bonding head.
As to claim 19, Yamauchi, Crespin, Nagatomo and Mochizuki as combined in claim 16 would function wherein in a case where the destination fiducials are not available, the bonding head alignment errors are measured by one or more displacement sensors (on the bonding head and a destination chuck. See the citations above. See also Yamauchi, paragraph 0173, disclosing “an imaging device constituted by a so-called dual view camera is inserted and alignment marks on a flexible substrate FT and the chip CP are imaged by the imaging device”
As to claim 20, Yamauchi, Crespin, Nagatomo and Mochizuki as combined in claim 16 would function such that wherein the controller is further configured to: determine a total correction based on the second alignment marks placement error, the die placement errors, and the bonding head alignment errors; and providing instructions to an alignment hardware to perform adjustment of at least one of the plurality of bonding heads, a destination chuck, and/or a destination carriage in an X, Y, and θ directions based on the total correction.
See for example, Yamauchi, paragraph 0019, 0127, 0132, 0138, disclosing:
[0019] a first position correction step of, by relatively moving the component with respect to the substrate in a direction that is parallel with the mounting surface and in which the positional deviation amount decreases, based on the positional deviation amount calculated in the first step of calculating amount of positional deviation, correcting a relative position of the component with respect to the substrate.
[0127] Subsequently, the chip mounting system 1 performs a second position correction step of performing correction of the position of the chip CP with respect to the substrate WT by moving the stage 315 in a horizontal direction with respect to the head 33H in such a way as to eliminate the calculated positional deviation amounts (step S3). In this step, the chip mounting system 1 moves the stage 315 in the X-direction, Y-direction, and the rotational direction about the Z-axis with the head 33H fixed in such a way as to eliminate positional deviation amounts Δx, Δy, and Δθ. Specifically, the controller 90 controls the stage driver 320 to relatively move the chip CP with respect to the substrate WT in a horizontal direction, that is, in a direction parallel with the mounting surface WTf of the substrate WT, based on the calculated positional deviation amounts.
[0132] Returning to FIG. 15, succeedingly, the chip mounting system 1 performs a first position correction step of correcting the position of the chip CP with respect to the substrate WT by relatively moving the chip CP with respect to the substrate WT in such a way as to reduce the calculated positional deviation amounts Δx, Δy, and Δθ (step S7). In this step, the chip mounting system 1 moves the stage 315 in the X-direction, Y-direction, and the rotational direction about the Z-axis with the head 33H fixed in such a way as to eliminate the positional deviation amounts Δx, Δy, and Δθ. Specifically, the controller 90 controls the stage driver 320 to relatively move the chip CP with respect to the substrate WT in a horizontal direction, that is, in a direction parallel with the mounting surface WTf of the substrate WT, based on the calculated positional deviation amounts. This processing causes each of the pair of the alignment marks MC1a and MC2a and the pair of alignment marks MC1b and MC2b to be aligned with each other in the Z-axis direction, as illustrated in, for example, FIG. 18A.
[0138] Returning to FIG. 15, next, the chip 1 calculates relative correction movement amounts of the chip CP with respect to the substrate WT required to decrease all of the calculated positional deviation amounts Δx, Δy, and Δθ to the positional deviation amount threshold values Δxth, Δyth, and Δθth or less, respectively (step S16). In this step, the controller 90 calculates correction movement amounts that cause the chip CP to relatively move by movement amounts that are equivalent to differences between the positional deviation amounts Δx, Δy, and Δθ between the chip CP and the substrate WT with the chip CP in contact with the substrate WT and the positional deviation amounts between the chip CP and the substrate WT with the chip CP separated from the substrate WT. Aligning the chip CP with the substrate WT with the positions thereof offset from each other by the movement amounts equivalent to differences between positional deviation amounts with the chip CP in contact with the substrate WT and positional deviation amounts with the chip CP not in contact with the substrate WT as described above enables positional deviation of the chip CP with respect to the substrate WT to be eliminated if similar positional deviation caused by contact of the chip CP with the substrate WT occurs when the chip CP is brought into contact with the substrate WT again.
See Crespin, paragraph 0040, which discloses:
[0040] Further in an example embodiment, substrate stage 20 is capable of providing 180.degree. rotation about any point on substrate frontside 52 or substrate backside 54. An advantage of such capability is that an alignment mark can be imaged and rotated without the image leaving the field of view of the particular optical system. The ability to image and measure an alignment mark at different orientations allows for the measurement and reduction or elimination of orientation-dependent errors. This in turn provides apparatus 10 with improved measurement capability.
See also Nagatomo, paragraph 0061, which discloses:
[0061] Referring FIGS. 1 to 5, the bonding stage 600 may movably mount the substrate 3 to be bonded. The bonding stage 600 may move in the X-axis direction and/or the Y-axis direction to designate a bonding position of the semiconductor chip 2. In addition, the bonding stage 600 may rotate in a rotation direction (e.g., θ direction) having a rotation axis (e.g., θ-axis) that is parallel to the Z-axis direction. In addition, the bonding stage 600 may rotate in a rotation direction (e.g., Tx direction) having a rotation axis (e.g., Tx-axis) that is parallel to the X-axis direction, and may be configured to rotate in a rotation direction (e.g., Ty direction) having as a rotation axis (e.g., Ty-axis) that is parallel to the Y-axis direction. The bonding stage 600 may be driven based on a correction value calculated based on angle information in the θ-axis and position information of the semiconductor chip 2 obtained by the camera 321, angle information in the θ-axis and position information of the substrate 3 obtained by the camera 321, height information and inclination information of the semiconductor chip 2 obtained by the measuring apparatus 500, and/or height information and inclination information of the substrate 3 obtained by the measuring apparatus 500, thereby correcting a bonding position between the semiconductor chip 2 and the substrate 3.
As to claim 21, Yamauchi, Crespin, Nagatomo and Mochizuki as combined in claim 20 would function such that wherein upon adjustment of the plurality of bonding heads, the destination chuck, and/or the destination carriage in the X, Y, and θ directions, the plurality of bonding heads places the plurality of dies onto a destination substrate. See especially Yamauchi, paragraph 0103, disclosing “Therefore, bringing the bonding surface CPf of the chip CP into contact with the mounting surface WTf of the substrate WT causes the chip CP to be bonded to the substrate WT. Note that the bonding surface CPf of the chip CP may be, for example, a surface on which planar metal electrodes are exposed.”:’
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (US 20210313211 A1) and Crespin (US 20110058731 A1) and Nagatomo (US 20220216077 A1) and Mochizuki (US 20130068824 A1) as applied to claims 16 and 18-21 above, and further in view of Sreenivasan (WO 2023137181 A2).
As to claim 17, Yamauchi, Crespin, Nagatomo and Mochizuki do not disclose wherein the bonding head alignment marks are complementary Moiré interference marks to the second non-active side alignment marks.
However, Sreenivasan discloses and makes obvious wherein the bonding head alignment marks are complementary Moiré interference marks to the second non-active side alignment marks. See, for example, paragraph 0092 (“…during bonding, in-situ metrology is performed using one or more of the following methods: moire metrology…”), 00158 (“…an optional complimentary mark 1206 on transfer substrate 104 for moire metrology is utilized”), 00183, disclosing:
[0092] Bonding, as used herein, is a process for temporary or permanent attachment of one die/substrate with another die/substrate. The bonding may be bump bonding, micro-bump bonding, eutectic bonding, thermocompression bonding, hybrid bonding, anodic bonding, fusion bonding, solder bump bonding, wire bonding, etc. In one embodiment, during bonding, in-situ metrology is performed using one or more of the following methods: moire metrology or optionally using an imaging-based system (monitoring the absolute position of the dies, optionally with an interferometric stage, and a sensor monitoring any global motion of the two bonding bodies with respect to each other). Also, during bonding, the die being bonded could be curved in a concave or convex manner fashion (for ease of optional adhesive curing and escape of volatiles).
[00158] Additionally, as shown in Figure 12A, an optional mirror assembly 706 is utilized to sense multiple marks using a single imager assembly. In connection with such sensing, an optional complimentary mark 1206 on transfer substrate 104 for moire metrology is utilized.
[00183] Referring to Figures 11, 12A-12B, 13A-13B, 14A-14B, 15A-15B and 16A-16C, in one embodiment, the alignment system for measuring the alignment of dies 106 on a substrate (e.g., transfer substrate 104, source substrate 105, product substrate 1604, intermediate substrate) lies underneath the respective chuck of said substrate. In one embodiment, one or more of the following alignment schemes are utilized for measurement of the die alignment: relative alignment measurement (for instance, using moire-based alignment schemes) and absolute alignment measurement (for instance, using imaging-based alignment schemes). In one embodiment, the microscopes used in the alignment metrology are low numerical aperture (NA) microscopes. In one embodiment, the microscopes used in the alignment metrology are very low numerical aperture (NA) microscopes. In one embodiment, the microscopes used in the alignment metrology have an NA less than 0.05. In one embodiment, the microscopes used in the alignment metrology have an NA less than 0.01. In one embodiment, the die alignment is measured relative to corresponding marks on a substrate (for instance, transfer substrate 104) that are arranged in a grid with x and y pitches being the SPPx and SPPY. In one embodiment, the marks are moire alignment marks. In one embodiment, the substrate with the alignment mark grid is also referred to as the golden reference wafer and composed of one or more of therm o- mechanically stable materials (for instance, sapphire, fused silica, glass and silicon). In one embodiment, die pick-and-place is implemented using one or more AMS-es that are mounted onto a gantry stage 1102. In one embodiment, gantry stage 1102 further contains one or more source substrates 105, each of which could be of a unique size and form factor. One or more of the wafers (e g., source wafers 105, product wafers 1604, transfer wafers 104, intermediate wafers) and corresponding chucks are mounted on an independent XY0 wafer stage.
[00285] In one embodiment, dies 106 are picked-and-placed onto transfer wafer 104' (“transfer wafer 1”). In one embodiment, dies 106 contain alignment marks on their front-side or back-side created, for instance, using sub-micrometer plasma dicing, or sub -micrometer MACE, or etched marks on the die back-side registered to the front-side. In one embodiment, the marks are moire type, bob-in-box type, etc. In one embodiment, transfer wafer 1 104' is transparent. In one embodiment, transfer wafer 1 104' contains a set of alignment marks that are complementary to the die alignment marks. In one embodiment, a light-switchable adhesive (e.g., adhesive 206) is present between dies 106 and transfer wafer 104'. In one embodiment, LSA 206 (light- switchable adhesive), along with the complementary die and wafer marks, are used to precisely register dies 106 to transfer wafer 1 104'. In one embodiment, if dies 106 are facing down on transfer wafer 1 104', a bonding step is performed onto product substrate 1604 in a wafer-to- wafer manner from transfer wafer 1 104' to product 1604. If dies 106 on transfer wafer 1 104' are facing up, dies 106 could be transferred to an another transfer wafer 104" (“transfer wafer 2”). Subsequently, a bonding step is performed onto a product substrate 1604 in a wafer-to- wafer manner from transfer wafer 2 104" to product wafer 1604 In one embodiment, the bonding is one or more of the following types: eutectic bonding, thermocompression bonding, direct bonding, hybrid bonding, anodic bonding, fusion bonding and bonding using a thin layer of dispensed adhesive In one embodiment, product wafer 1604 has nanopillar arrays. In one embodiment, the nanopillar arrays are sparse (for instance, 1% to 4% of the substrate surface area), such that the bonding occurs in sparse locations, reducing the likelihood of particle hotspots. In one embodiment, metal interconnections between the assembled die 106 on product wafer 1604 are made using conventional semiconductor fabrication processes (metal deposition, dielectric deposition, planarization, etching, lithography, etc.).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized wherein the bonding head alignment marks are complementary Moiré interference marks to the second non-active side alignment marks as taught by Sreenivasan because such Moire interference marks can be used for bonding of dies.
Conclusion
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/GEORGE R KOCH/Primary Examiner, Art Unit 1745
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