Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation “to produce a reference signal based on the reference signal”. It is unclear how the reference signal produced can be based on itself. For purposes of examination, this limitation will be read as “to produce a reference signal based on a signal”. By their dependency, the following claims are also rejected: 17/16, 18/17/16, 19/18/17/16, 20/16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki et al. (WO 2022/176896 A1), hereinafter Aoki, in view of Mokhtari-Koushyar et al. (U.S. Patent Application No. 2023/0130434 A1), hereinafter Mokhtari-Koushyar, in view of Jeon et al. (KR 2012/0129215 A), hereinafter Jeon.
Regarding Claim 1, Aoki teaches a laser controller integrated circuit (Fig. 2) comprising: a first input port (Fig. 2, see left vertical edge of “43”); a second input port (Fig. 2, see left vertical edge of “62”); a sideband direct digital synthesizer (Fig. 2, “4”) coupled to the first input port (Fig. 2, see left vertical edge of “43” coupled to other components within “4”) and configured to produce a modulation signal (see paragraph [0022] of Examiner provided translation, component of “SDF1” corresponding to “L0mod”, where “SDF1” is the negative superposition of “L1” and “L0mod”) based on an input signal (Fig. 2, “L0”) received via the first input port (Fig. 2, see arrow from “11” to left vertical edge of “43” including “L0”); a reference signal (see paragraph [0022] of Examiner provided translation, component of “SDF1” corresponding to “L1”, where “SDF1” is the negative superposition of “L1” and “L0mod”), the modulation signal and the reference signal having a same frequency (see explanation below); a frequency-locking control loop (Fig. 2, “6”; see paragraph [0033] of Examiner provided Translation, “lock function”, “wavelength control”) coupled to the second input port (Fig. 2, see “6” including left vertical edge of “62”), and the sideband direct digital synthesizer (Fig. 2, left vertical edge of “62” coupled to other components within “6”), and configured to produce a corrected DC bias current signal (Fig. 2, “Serr1”) based on the reference signal and a measurement signal (Fig. 2, “SDF1”) received via the second input port (Fig. 2, “SDF1”; see paragraph [0022] of Examiner provided translation, where “SDF1” is the negative superposition of “L1” and “L0mod”).
Aoki does not explicitly disclose: the modulation signal and the reference signal having a same frequency. However, Aoki discloses: the input signal and the modulation signal having a same frequency (see paragraph [0031] of Examiner provided translation, “v0”); the wavelength of the reference signal is 2.05 µm (see paragraph [0027] of Examiner provided translation, the frequency of the component of “L1” in “SDF1” has the same frequency as “L1”); the wavelength of the input signal is 2.05 µm (see paragraph [0027] of Examiner provided translation, 2050.967 nm
=
2.05 µm when rounded to the nearest hundredth). Therefore, it can be necessarily understood to someone of ordinary skill in the art that: the modulation signal and the reference signal having a same frequency, in the sense that the reference signal and the input signal have a same frequency since they have the same wavelength, and the modulation signal and the input signal have a same frequency as disclosed by Aoki.
Aoki does not explicitly disclose: the frequency-locking control loop is a Pound-Drever-Hall control loop. However, Aoki discloses: wavelength control and stabilization by the Pound-Drever-Hall method (see paragraph [0019] of Examiner provided translation). Therefore, it can be necessarily understood to someone of ordinary skill in the art that: the frequency-locking control loop of Aoki can be considered a Pound-Drever-Hall control loop, in the sense that frequency-locking is wavelength control and stabilization in the device of Aoki. Aoki does not teach: that the sideband direct digital synthesizer is configured to produce the modulation signal and reference signal; a thermal management circuit is configured to produce at least one thermal control signal.
Mokhtari-Koushyar teaches: the direct digital synthesizer (Fig. 2, “210”) is configured to produce a signal (Fig. 2, “212”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have the sideband direct digital synthesizer configured to produce the modulation signal and reference signal in the device of Aoki, for the benefit of phase accumulation (paragraph [0012]) and frequency resolution (paragraph [0070]). Aoki and Mokhtari-Koushyar do not teach: a thermal management circuit is configured to produce at least one thermal control signal.
Jeon teaches: a thermal management circuit (Fig. 2, “230”) is configured to produce at least one thermal control signal (see p. 3, sixteenth paragraph of Examiner provided translation, “comparison result”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a thermal management circuit configured to produce at least one thermal control signal as taught by Jeon in the device of Aoki and Mokhtari-Koushyar, for the benefit of temperature sensing.
Regarding Claim 2, Aoki, Mokhtari-Koushyar, and Jeon teach the device of Claim 1. Mokhtari-Koushyar further teaches: a digital programming interface (Fig. 2, “204”) coupled to the sideband direct digital synthesizer (Fig. 2, see “204” coupled to “210”), wherein the digital programming interface comprises one or more configuration registers (Fig. 2, “218”) coupled to a serial configuration interface (Fig. 2, see “218” coupled to “216”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a digital programming interface in the device of Aoki, Mokhtari-Koushyar, and Jeon, for the benefit of containing configuration parameters (paragraph [0078]). It can be necessarily understood to someone of ordinary skill in the art that: the digital programming interface is coupled to the Pound-Drever-Hall frequency-locking control loop and the thermal management circuit in the device of Aoki, Mokhtari-Koushyar, and Jeon, in the sense that they are connected components within the laser controller integrated circuit.
Regarding Claim 9, Aoki teaches a laser controller (Fig. 2, “20”) comprising: laser bias current circuitry (Fig. 2, arrow from “65” to “12”); and a laser controller integrated circuit (Fig. 2) including, a first input port (Fig. 2, see left vertical edge of “43”), a second input port (Fig. 2, see left vertical edge of “62”), a sideband direct digital synthesizer (Fig. 2, “4”) coupled to the first input port (Fig. 2, see left vertical edge of “43” coupled to other components within “4”) and configured to produce a reference signal (Fig. 2, “Lmod”) based on an input signal received via the first input port (Fig. 1, “L0”), a frequency-locking control loop (Fig. 2, “6”; see paragraph [0033] of Examiner provided Translation, “lock function”, “wavelength control”) coupled to the second input port (Fig. 2, see “6” including left vertical edge of “62”), the sideband direct digital synthesizer (Fig. 2, left vertical edge of “62” coupled to other components within “6”), and to the laser bias current circuitry (Fig. 2, see “6” including left vertical edge of “62” coupled to arrow from “65” to “12”), the frequency-locking loop configured to produce a corrected DC bias current signal (Fig. 2, “Serr1”) based on the reference signal and a measurement signal (Fig. 2, “SDF1”) received via the second input port (Fig. 2, “SDF1”; see paragraph [0022] of Examiner provided translation, “SDF1” is the negative superposition of “L1” and “L0mod”), and to provide the corrected DC bias current signal to the laser bias current circuitry (see paragraph [0009] of Examiner provided translation, “error signal”).
Aoki does not explicitly disclose: the frequency-locking control loop is a Pound-Drever-Hall control loop. However, Aoki discloses: wavelength control and stabilization by the Pound-Drever-Hall method (see paragraph [0019] of Examiner provided translation). Therefore, it can be necessarily understood to someone of ordinary skill in the art that: the frequency-locking control loop of Aoki can be considered a Pound-Drever-Hall control loop, in the sense that frequency-locking is wavelength control and stabilization in the device of Aoki. Aoki does not teach: a digital programming interface; that the sideband direct digital synthesizer is also configured to produce a reference signal based on one or more first control signals received via the digital programming interface; that the Pound-Drever-Hall frequency-locking loop is also configured to produce a corrected DC bias current signal based on one or more second control signals received via the digital programming interface; thermal control circuitry; a thermal management circuit coupled to the thermal control circuitry, the thermal management circuit configured to provide at least one thermal control signal to the thermal control circuitry based on one or more thermal control signals received via the digital programming interface.
Mokhtari-Koushyar teaches: a digital programming interface (Fig. 2, “204”); that the sideband direct digital synthesizer is also configured to produce a reference signal (Fig. 2, “212”) based on one or more first control signals received via the digital programming interface (Fig. 2, arrow between “204” and “210”); one or more second control signals produced by the digital programming interface (Fig. 2, arrow from “204” to “206”, arrow from “204” to “222”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a digital programming interface in the device of Aoki, for the benefit for the benefit of containing configuration parameters (paragraph [0078]); that the sideband direct digital synthesizer is also configured to produce a reference signal based on one or more first control signals received via the digital programming interface in the device of Aoki, in order to select the output frequency (paragraph [0075]); that the Pound-Drever-Hall frequency-locking loop is also configured to produce a corrected DC bias current signal based on one or more second control signals received via the digital programming interface, in the device of Aoki, for the benefit of feedback control (paragraph [0079]). It can be necessarily understood that the Pound-Drever-Hall frequency-locking control loop is coupled to the digital programming interface, in the sense they are connected components in the device of Aoki and Mokhtari-Koushyar. Aoki and Mokhtari-Koushyar do not teach: thermal control circuitry; a thermal management circuit coupled to the thermal control circuitry; the thermal management circuit configured to provide at least one thermal control signal to the thermal control circuitry.
Jeon teaches: thermal control circuitry (Fig. 2, “250”); a thermal management circuit (Fig. 2, “230”) coupled to the thermal control circuitry (Fig. 2, see “230” and “250” connected), the thermal management circuit configured to provide at least one thermal control signal to the thermal control circuitry (see p. 3, sixteenth paragraph of Examiner provided translation, “comparison result”).Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have thermal control circuitry in the device of Aoki and Mokhtari-Koushyar, for the benefit of controlling the temperature of a laser diode (see p. 3, seventeenth paragraph of Examiner provided translation, “temperature control signal”); have a thermal management circuit coupled to the thermal control circuitry, the thermal management circuit configured to provide at least one thermal control signal to the thermal control circuitry based on one or more thermal control signals received via the digital programming interface, for the benefit of temperature sensing. It can be necessarily understood to someone having ordinary skill in the art that: that the thermal management circuit is coupled to the digital programming interface, in the sense they are connected components in the device of Aoki, Mokhtari-Koushyar, and Jeon.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Aoki, in view of Mokhtari-Koushyar, in view of Jeon, in view of Stewart et al. (U.S. Patent Application No. 2007/0297468 A1), hereinafter Stewart.
Regarding Claim 12, Aoki, Mokhtari-Koushyar, and Jeon teach the device of Claim 9. Aoki, Mokhtari-Koushyar, and Jeon do not teach: the thermal control circuitry comprises: at least one thermoelectric cooler ; at least one thermoelectric cooler driver coupled to the at least one thermoelectric cooler and configured to provide a drive current to the at least one thermoelectric cooler, the drive current being based on the at least one thermal control signal; and a temperature sensor coupled to the at least one thermoelectric cooler and configured to provide a sensor signal representative of a temperature of a controlled device.
Stewart teaches: at least one thermoelectric cooler (Fig. 3, “114”); at least one thermoelectric cooler driver (Fig. 3, “116”) coupled to the at least one thermoelectric cooler (Fig. 3, see arrows between “116” and “114”) and configured to provide a drive voltage to the at least one thermoelectric cooler (Fig. 3, “VTec”), the drive voltage being based on the at least one thermal control signal (paragraph [0048]); and a temperature sensor (Fig. 3, “110”) coupled to the at least one thermoelectric cooler (Fig. 3, see “110” coupled to “112”) and configured to provide a sensor signal representative of a temperature of a controlled device (paragraph [0043]). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a thermoelectric cooler in the device of Aoki, Mokhtari-Koushyar, and Jeon, for the benefit of heat sinking the laser diode (paragraph [0044]); to have a temperature sensor in the device of Aoki, Mokhtari-Koushyar, and Jeon, in order to sense the temperature variation of the laser diode (paragraph [0043]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Aoki, in view of Mokhtari-Koushyar, in view of Jeon, in view of Gunn et al. (U.S. Patent Application No. 2008/0001062 A1), hereinafter Gunn.
Regarding Claim 16, Aoki teaches a laser system (Fig. 2, “20”) comprising: a laser diode (Fig. 2, “12”) configured to produce a laser signal (Fig. 2, “L1”); a phase modulator (Fig. 2, “43”) configured to modulate a laser signal (Fig. 2, “L0”) to produce a clock signal (Fig. 2, “L0mod”); and a laser controller integrated circuit (Fig. 2) comprising a first input port (Fig. 2, see left vertical edge of “43”), a second input port (Fig. 2, see left vertical edge of “62”), a sideband direct digital synthesizer (Fig. 2, “4”) coupled to the first input port (Fig. 2, see left vertical edge of “43” coupled to other components within “4”) and configured to receive an input signal (Fig. 2, “L0” via the first input port (Fig. 2, see “L0” into left vertical edge of “62”) and to produce a reference signal (Fig. 2, “L0”) based on a signal; a frequency-locking control loop (Fig. 2, “6”; see paragraph [0033] of Examiner provided Translation, “lock function”, “wavelength control”) coupled to the second input port (Fig. 2, see “6” including left vertical edge of “62”), the sideband direct digital synthesizer (Fig. 2, see “6” connected to “4”), the frequency-locking control loop configured to receive, via the second input port, a sample of the clock signal, and to produce, based on the reference signal and the sample of the clock signal (Fig. 2, “SDF1”; see paragraph [0022] of Examiner provided translation) a corrected DC bias current signal for the laser diode (Fig. 2, “Serr1”). Aoki does not explicitly disclose: the frequency-locking control loop is a Pound-Drever-Hall control loop. However, Aoki discloses: wavelength control and stabilization by the Pound-Drever-Hall method (see paragraph [0019] of Examiner provided translation). Therefore, it can be necessarily understood to someone of ordinary skill in the art that: the frequency-locking control loop of Aoki can be considered a Pound-Drever-Hall control loop, in the sense that frequency-locking is wavelength control and stabilization in the device of Aoki. Aoki does not teach: a digital programming interface; a photonic integrated circuit coupled to the laser diode and comprising a micro-resonator; that the Pound-Drever-Hall frequency locking control loop is configured to produce a corrected DC bias current signal for the laser diode to lock a frequency of the laser signal to a resonance frequency of the micro-resonator; and a thermal management circuit coupled to the digital programming interface and configured to produce, based on one or more first control signals received via the digital programming interface, at least one thermal control signal to tune a temperature of at least one of the laser diode or the photonic integrated circuit.
Mokhtari-Koushyar teaches: a digital programming interface (Fig. 2, “204”) configured to produce one or more first control signals (Fig. 2, see arrows from “204” to “”210”, “22” and “206”); a photonic integrated circuit (Fig. 2, “206”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a digital programming interface in the device of Aoki, for the benefit of containing configuration parameters (paragraph [0078]); to have a photonic integrated circuit in the device of Aoki, for the benefit of outputting pulses (paragraph [0069]). Aoki and Mokhtari-Koushyar do not teach: that the photonic integrated circuit comprises a micro-resonator; a thermal management circuit coupled to the digital programming interface and configured to produce, based on one or more first control signals received via the digital programming interface, at least one thermal control signal to tune a temperature of at least one of the laser diode or the photonic integrated circuit.
Jeon teaches: a thermal management circuit (Fig. 2, “250”) configured to produce at least one thermal control signal (see p. 3, seventeenth paragraph of Examiner provided translation) to tune a temperature of at least one of the laser diode or the photonic integrated circuit (see p. 3, seventeenth paragraph of Examiner provided translation). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a thermal management circuit configured to produce at least one thermal control signal as taught by Jeon in the device of Aoki and Mokhtari-Koushyar, for the benefit of temperature sensing. It can be necessarily understood to someone having ordinary skill in the art that: the Pound-Drever-Hall frequency-locking control loop is coupled to the digital programming interface, in the sense they are connected components in the device of Aoki, Mokhtari-Koushyar, and Jeon; the thermal management circuit is coupled to the digital programming interface, in the sense they are connected components in the device of Aoki, Mokhtari-Koushyar, and Jeon. Aoki, Mokhtari-Koushyar, and Jeon do not teach: that the photonic integrated circuit comprises a micro-resonator.
Gunn teaches: a micro-resonator (Fig. 1, “940”). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a micro-resonator in the device of Aoki, Mokhtari-Koushyar, and Jeon, for the benefit of high-Q energy storage and lowering phase noise (paragraph [0030]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Aoki, in view of Mokhtari-Koushyar, in view of Jeon, in view of Gunn, in view of Stewart.
Regarding Claim 17, Aoki, Mokhtari-Koushyar, Jeon, and Gunn teach the device of Claim 16.
Aoki, Mokhtari-Koushyar, Jeon, and Gunn do not teach: the photonic integrated circuit further comprises at least one thermoelectric cooler, the laser system further comprising: a temperature sensor configured to provide a sensor signal representative of the temperature of at least one of the laser diode or the photonic circuit; and at least one thermoelectric cooler driver coupled to the at least one thermoelectric cooler and configured to provide a drive current to the at least one thermoelectric cooler to tune the temperature of at least one of the laser diode or the photonic integrated circuit.
Stewart teaches: at least one thermoelectric cooler (Fig. 3, “114”); a temperature sensor (Fig. 3, “110”) configured to provide a sensor signal representative of the temperature of at least one of the laser diode or the photonic circuit (paragraph [0043]) and at least one thermoelectric cooler driver (Fig. 3, “116”) coupled to the at least one thermoelectric cooler (Fig. 3, see arrows between “116” and “114”) and configured to provide a drive voltage to the at least one thermoelectric cooler to tune the temperature of at least one of the laser diode or the photonic integrated circuit (paragraph [0048]). Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have a thermoelectric cooler in the device of Aoki, Mokhtari-Koushyar, Jeon, and Gunn, for the benefit of heat sinking the laser diode (paragraph [0044]); to have a temperature sensor in the device of Aoki, Mokhtari-Koushyar, Jeon, and Gunn, in order to sense the temperature variation of the laser diode (paragraph [0043]).
Allowable Subject Matter
Claims 3-8, 10-11, 13-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sanchez (US 2006/0153256 A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASMIN KAUR MUNDI whose telephone number is (571)272-9755. The examiner can normally be reached Monday - Thursday, 7:30 a.m. - 6 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.K.M./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
Prosecution Insights