DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 9, 10, and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hanson et al (US Patent 6668031).
Regarding claim 1, Figure 6 of Hanson discloses a buffer circuit comprising:
a driving control circuit configured to receive an input signal, configured to change a voltage level of a first node to a voltage level lower by a first voltage level lower than a high boundary voltage level of the input signal and configured to change a voltage level of a second node to a voltage level higher by a second voltage level higher than a low boundary voltage level of the input signal [604]
a driving circuit configured to pull-up drive an output node based on the voltage level of the first node and configured to pull-down drive the output node based on the voltage level of the second node [606]
Regarding claim 7, Figure 6 of Hanson discloses a buffer circuit comprising:
a driving control circuit configured to receive an input signal swinging between a high boundary voltage level and a low boundary voltage level and configured to convert the swing range of the input signal to generate a pull-up control signal swinging within a first swing range and a pull-down control signal swinging within a second swing range [604]
a driving circuit configured to pull-up drive an output node based on the pull-up control signal and configured to pull-down drive the output node based on the pull-down control signal [606]
Regarding claim 9, Figure 6 of Hanson discloses wherein the driving control circuit is configured to generate the pull-up control signal and the pull-down control signal from the input signal when the first control signal is enabled [Figure 6].
Regarding claim 10, Figure 6 of Hanson discloses a voltage fixing circuit configured to fix, when the first control signal is disabled, the first node to a first off-voltage and the second node to a second off-voltage [608 and 610].
Regarding claim 12, Figure 6 of Hanson discloses a voltage adjusting circuit configured to additionally convert the first swing range and the second swing range based on a second control signal [608 and 610].
Regarding claim 13, Figure 6 of Hanson discloses a buffer circuit comprising:
a driving control circuit configured to receive an input signal and configured to generate, when a first control signal is enabled, a pull-up control signal having a voltage level lower than a high boundary voltage level of the input signal and a pull-down control signal having a voltage level higher than a low boundary voltage level of the input signal [604]
a driving circuit configured to pull-up drive an output node based on the pull-up control signal and configured to pull-down drive the output node based on the pull-down control signal [606]
Regarding claim 14, Figure 6 of Hanson discloses a voltage fixing circuit configured to fix, when the first control signal is disabled, the pull-up control signal to a first off-voltage and the pull-down control signal to a second off-voltage [608 and 610].
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al (US Patent 7586339).
Regarding claim 17, Figure 4 of Oh discloses a buffer circuit comprising:
a first N-channel MOS transistor configured to receive a first control signal through a gate thereof and configured to receive an input signal through one of source and drain thereof and connected to a first node through the other of the source and the drain thereof [1430; inherent in inverter]
a first P-channel MOS transistor configured to receive a complementary signal of the first control signal through a gate thereof and configured to receive the input signal through one of source and drain thereof and connected to a second node through the other of the source and the drain thereof [1440; inherent in inverter]
a second P-channel MOS transistor configured to pull-up drive an output node based on a voltage level of the first node [1470]
a second N-channel MOS transistor configured to pull-down drive the output node based on a voltage level of the second node [1480]
Regarding claim 18, Figure 4 of Oh discloses
a third P-channel MOS transistor configured to receive the first control signal through a gate thereof, configured to receive a first power voltage through a source thereof and connected to the first node through a drain thereof [1430; inherent in inverter]
a third N-channel MOS transistor configured to receive the complementary signal of the first control signal through a gate thereof, configured to receive a second power voltage through a source thereof and connected to the second node through a drain thereof [1440; inherent in inverter]
Allowable Subject Matter
Claims 2-6, 8, 11, 15, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Applicant argues that Hanson fails to disclose “(i) a driving control circuit that converts the swing range of an input signal to generate reduced-swing internal control signals, (ii) internal control nodes having voltage levels shifted inward from the input signal boundary voltages, and (iii) generation of a full-swing output signal based on those internally shifted node voltages.” However, none of the currently rejected claims recite any of these limitations. Given broadest reasonable interpretation, the control circuit of Hanson converts the input signal by inverting it twice. When the input signal is converted the first time, the swing range is inverted, and when it is inverted the second time the swing range is inverted again. Nothing in the rejected claims explicitly requires that the swing range is reduced. Regarding claim 1 specifically, the outputs of the inverters lower a voltage at a node to be lower than or higher than the input (i.e. VDD goes to Ground, and Ground goes to VDD). Ground is lower than the high boundary voltage and VDD is higher than the low boundary. Additionally, the gate inputs of the driver of Hanson are based on the outputs of the inverters of the control circuit. Therefore, Hanson discloses all of the claimed limitations of the rejected claims. Thus, the applicant’s arguments are not persuasive.
Applicant argues that Figure 4 of Oh does not disclose all the claim limitations of claims 17 and 18. The examiner disagrees. The top inverter of 1430 inherently includes an NMOS transistor that receives the input of 1430 (LO) at its gate, an input signal (supply voltage and output of the PMOS of the inverter) at its drain, and a first node (Ground) at its source. The top inverter of 1440 includes an PMOS transistor that receives a complement of the input of 1430 (LOB) at its gate, the input signal (supply voltage) at its source, and a second node (DOKB) at its drain. The PMOS transistor 1470 pulls-up the output node based on the voltage level of the first node (Ground voltage at the Ground node causes the PMOS 1470 to pull-up the output) and the NMOS transistor 1480 pulls-down the output node based on the voltage level of the second node (when the voltage level at DOKB is high, 1480 pulls the output node down). Nothing in the claims explicitly requires that the first and second nodes both be directly connected to the gates of the second NMOS and PMOS transistors or that the signals be shifted by a threshold voltage, as argued by the applicant. Additionally, since claim 18 does not require that the drain of the third PMOS transistor be directly connected to the first node, the drain of the third PMOS transistor (the inherent PMOS transistor in the top inverter of 1430) is connected to the first node (Ground) through the NMOS transistor of the top inverter of 1430. Therefore, given broadest reasonable interpretation, Oh discloses all the claim limitations of claims 17 and 18. Thus, the applicant’s argument is not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2842