DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 8, 10-12, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kakaiya et al. (US 20230289229 A1) hereafter Kakaiya in view of Raisch et al. (US 20200249944 A1) hereafter Raisch.
Regarding claim 1, Kakaiya teaches:
generating, by a host system, a work descriptor (Paragraph 30; “Software client 118 creates a work descriptor and invokes the accelerator to process the descriptor” the software client running on the CPU corresponds to the host system and expressly generates the work descriptor) identifying a plurality of workflow tasks to be performed by a hardware device (Paragraph 30; “Accelerator hardware will then: (i) validate the descriptor, (ii) issue DMA read(s) to read the source buffer(s), (iii) complete the required processing per the operation specified in the descriptor”, where the descriptor specifies operations for the accelerator hardware which involves several processing steps such as validation, DMA reads/writes, and processing, thereby identifying workflow tasks for the hardware device), wherein the work descriptor corresponds to a performance completion message generated by the hardware device in response to completing performance of the work descriptor (Paragraph 30; “At operation 4, the accelerator hardware will generate a completion interrupt, a completion record DMA write, or both to notify the software client about the completion of the work.” The completion interrupt is generated in response to completing execution of the descriptor. Thus the work descriptor corresponds to a completion message generated by the hardware device upon completion.);
adding one or more completion indicators to the work descriptor (Paragraph 68; “a work-descriptor TEE tag is used” teaches adding an indicator to the work descriptor.), wherein each completion indicator of the one or more completion indicators instructs the hardware device (Paragraphs 68-69; “DMA request(s) are tagged with the same TEE tag”, and “it is determined whether the TEE tag of DMA read completion(s) match the original TEE tag of the request(s)” show that hardware behavior changes based on the tag, satisfying instructing the hardware to change behavior in response to the completion indicia.);
causing the work descriptor to be available to the hardware device for execution (Paragraphs 30-35; “Software client 118 creates a work descriptor and invokes the accelerator to process the descriptor” and “either by writing the descriptor directly into the address associated with the WQ or by writing the descriptor into a ring-buffer and updating the tail pointer associated with the WQ. During this process, the Central Processing Unit (CPU) or processor core would consult a memory management unit to translate virtual address associated with the WQ to a physical address to perform the MMIO write. (2) Accelerator hardware (HW) (at operation 2) will be notified about the new descriptor or update of the tail pointer, and in the event that descriptor is not provided directly it would issue a Direct Memory Access (DMA) read to read the descriptor from the ring-buffer.” Writing the descriptor into the WQ/ring buffer and updating the tail pointer makes the descriptor accessible to the accelerator hardware, which then retrieves and executes it.).
Kakaiya does not teach generate one or more additional completion messages during performance of the work descriptor in response to a trigger criterion.
However, Raisch teaches:
generate one or more additional completion messages during performance of the work descriptor in response to a trigger criterion (Paragraph 109; “the input/output bus controller sending a completion message to the system nest; the system nest forwarding the completion message to the originating aggregation buffer; the aggregation buffer forwarding completion to the asynchronous core-nest interface; the asynchronous core-nest interface storing the completion status in the input/output status buffer for the input/output status buffer index and signaling completion of operation to the system firmware”, where the bus controller sending the completion message necessitates the generation of the completion message. The criterion for response is the actual completion of the task(s) as reported by the aggregation buffer, corresponding to occurring during performance of the work descriptor and in response to a trigger criterion.).
Kakaiya and Raisch are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya to incorporate the teachings of Raisch and generate additional completion messages during performance of the work descriptor in response to trigger conditions. A person of ordinary skill in the art would have understood checkpointing as a known method in the art, and the implementation would ensure that tasks that can be carried out partway through execution may properly execute without waiting for the entire task to complete.
Claim 11 recites similar limitations as those of claim 1, additionally reciting a memory; and
one or more processing units coupled to the memory. Kakaiya further teaches:
a memory; and one or more processing units coupled to the memory (Paragraph 84; “FIG. 5B shows processor core 590 including a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570”).
Claim 11 is rejected for similar reasons as those of claim 1.
Claim 16 recites similar limitations as those of claim 1, additionally reciting a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations. Kakaiya further teaches:
a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (Paragraph 123; “In some embodiments, the operations discussed herein, e.g., with reference to FIG. 1 et seq., may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including one or more tangible (e.g., non-transitory) machine-readable or computer-readable media having stored thereon instructions”).
Claim 16 is rejected for similar reasons as those of claim 1.
Regarding claim 2, Kakaiya in view of Raisch teach the method of claim 1. Kakaiya teaches:
adding a unique identifier to the work descriptor, wherein the hardware device is to provide the unique identifier in association with the performance completion message and the one or more additional completion messages (Paragraphs 68-69; “at an operation 232, a work-descriptor TEE tag is used for tagging upstream DMA requests (e.g., ring-buffer reads, source-buffer reads, destination-buffer reads/writes, completion-record writes, etc.). At an operation 234, it is determined whether the TEE tag of the work-descriptor is asserted (e.g., 1b). If so, at an operation 236, the DMA request(s) are tagged with the same TEE tag (e.g., 1b)” and “at an operation 264, it is determined whether the TEE tag of DMA read completion(s) match the original TEE tag of the request(s). If so, at an operation 266, the read completion is accepted”. The TEE tag acts as the per-descriptor identifier. Further, Paragraph 30 discloses “At operation 4, the accelerator hardware will generate a completion interrupt, a completion record DMA write, or both to notify the software client about the completion of the work.”, where the completion record includes the TEE tag to indicate which indicator completed.).
Claim 12 recites similar limitations as those of claim 2. Claim 12 is rejected for similar reasons as those of claim 2.
Regarding claim 4, Kakaiya in view of Raisch teaches the method of claim 1. Kakaiya teaches:
wherein the hardware device is one of: a network interface controller, a graphics processing unit, a data processing unit, or a central processing unit (Paragraph 31; “During this process, the Central Processing Unit (CPU) or processor core would consult a memory management unit to translate virtual address associated with the WQ to a physical address to perform the MMIO write”, the CPU acts as the processing hardware that performs descriptor handling and ultimately executes the workflow tasks specified in the descriptor, corresponding to the central processing unit element of the “one of” list of elements.).
Claim 17 recites similar limitations as those of claim 4. Claim 17 is rejected for similar reasons as those of claim 4.
Regarding claim 8, Kakaiya in view of Raisch teach the method of claim 1. Kakaiya teaches:
wherein the trigger criterion comprises an event associated with a workflow task of the plurality of workflow tasks (Paragraphs 30 and 69; workflow includes several operations, including: “(i) validate the descriptor, (ii) issue DMA read(s) to read the source buffer(s), (iii) complete the required processing per the operation specified in the descriptor, and (iv) perform DMA write(s)”, corresponding to workflow tasks. Paragraph 69 further discloses “at an operation 264, it is determined whether the TEE tag of DMA read completion(s) match the original TEE tag of the request(s)”. The determination occurs upon DMA read completion, which is an event occurring during execution of a workflow task, thereby serving as a trigger criterion associated with that workflow task.).
Claim 19 recites similar limitations as those of claim 8. Claim 19 is rejected for similar reasons as those of claim 8.
Regarding claim 10, Kakaiya in view of Raisch teaches the method of claim 1. Kakaiya teaches:
wherein causing the work descriptor to be available to the hardware device for execution further comprises:
storing the work descriptor in a work queue of the host system, wherein the work queue is accessible by the hardware device (Paragraphs 24 and 30; “Software client 118 creates a work descriptor and invokes the accelerator to process the descriptor (operation 1), e.g., either by writing the descriptor directly into the address associated with the WQ or by writing the descriptor into a ring-buffer and updating the tail pointer associated with the WQ” discloses storing the work descriptor in the work queue (WQ). Paragraph 24 further discloses “As shown in FIG. 1A, a scalable accelerator 101 may include a Work Acceptance Unit 102 which includes one or more work-queues (WQs) 103a-103m that can be used by clients (such as software (SW) clients 104a-104n) to submit the work to the accelerator 101”, which demonstrates that the work queue is accessible by the hardware device.);
and notifying the hardware device about the work descriptor in the work queue (Paragraph 30; “Accelerator hardware (HW) (at operation 2) will be notified about the new descriptor or update of the tail pointer, and in the event that descriptor is not provided directly it would issue a Direct Memory Access (DMA) read to read the descriptor from the ring-buffer” expressly discloses notification to the hardware regarding the work descriptor in the queue.).
Claim 20 recites similar limitations as those of claim 10. Claim 20 is rejected for similar reasons as those of claim 10.
Claims 3, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kakaiya in view of Raisch, further in view of Presler-Marshall (US 20200042573 A1).
Regarding claim 3, Kakaiya in view of Raisch teaches the method of claim 1. Kakaiya teaches:
receiving, at the host system, a completion message of the one or more additional completion messages (Paragraph 30; “At operation 4, the accelerator hardware will generate a completion interrupt, a completion record DMA write, or both to notify the software client about the completion of the work.” The host system, software client 118, receives the completion record or interrupt corresponding to descriptor execution. Alongside the TEE tag taught in Paragraphs 68-69, the TEE tag allows identification of individual DMA completions, representing additional completion messages during performance of the work descriptor).
Kakaiya in view of Raisch does not teach comprising an operational statistic associated with the hardware device; modifying an operational parameter associated with the operational statistic.
However, Presler-Marshall teaches:
comprising an operational statistic associated with the hardware device; and modifying an operational parameter associated with the operational statistic (Paragraph 61; “top-level and component-level performance data gathered from the computing system and stored with the performance data 145. The performance monitor 110 may adjust or alter the operation of any of the components 211, 212, 213, and 214 automatically in order to mitigate a statistically significant decrease in the top-level performance of the computing system identified by the statistical tester 120”, where performance data reflects operational statistics of hardware components, and the system may modify operational parameters in response to the monitored statistics.).
Kakaiya, Raisch, and Presler-Marshall are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya in view of Raisch to incorporate the teachings of Presler-Marshall and have the message comprise an operational statistic associated with the hardware device; and modify an operational parameter associated with the operational statistic. A person of ordinary skill in the art would have recognized adjusting system components in response to monitored performance to be a known method in the art yielding the predictable result of maintaining or improving system performance.
Claim 13 recites similar limitations as those of claim 3. Claim 13 is rejected for similar reasons as those of claim 3.
Regarding claim 9, Kakaiya in view of Raisch teaches the method of claim 8. Kakaiya in view of Raisch does not teach wherein the trigger criterion further comprises a conditional evaluation of an operational statistic.
However, Presler-Marshall teaches:
wherein the trigger criterion further comprises a conditional evaluation of an operational statistic (Paragraph 61; “performance monitor 110 may implement automated changes to the computing system including the computing device 200 and the application 210 based on the results of the statistical tests applied by the statistical tester 120 to the top-level and component-level performance data gathered from the computing system”, where the statistical tests applied to performance data constitutes a conditional evaluation of operational statistics, and modification occurs when the evaluated statistic satisfies a condition, thereby corresponding to a trigger criterion based on conditional evaluation of an operational statistic.).
Kakaiya, Raisch, and Presler-Marshall are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya in view of Raisch to incorporate the teachings of Presler-Marshall and have the trigger criterion comprise a conditional evaluation of an operational statistic. A person of ordinary skill in the art would have recognized the known method of monitoring performance metrics and applying threshold or statistical tests to determine when corrective or reporting action should occur, and the implementation of this known method would have yielded the predictable result of enabling adaptive control and performance-based event triggering, with the expected benefits of improving system responsiveness and efficiency.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kakaiya in view of Raisch, further in view of Liang et al. (US 20230034779 A1) hereafter Liang.
Regarding claim 5, Kakaiya in view of Raisch teaches the method of claim 1. Kakaiya teaches:
A work descriptor (Paragraph 30; “Software client 118 creates a work descriptor”);
And a completion indicator (Paragraph 30; “the accelerator hardware will generate a completion interrupt, a completion record DMA write, or both to notify the software client about the completion of the work” corresponds to a field in the descriptor used to track completion.).
Kakaiya in view of Raisch does not teach a wrapper work descriptor.
However, Liang teaches:
A wrapper work descriptor (Paragraph 34; “a wrapper is designed to carry meta-data within buffer descriptor”).
Kakaiya, Raisch, and Liang are considered to be analogous to the claimed invention because they are in the same field of task management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya in view of Raisch to incorporate the teachings of Liang and generate a wrapper work descriptor comprising the work descriptor and completion indicator field. A person of ordinary skill in the art would have recognized the encapsulation of metadata with a descriptor and tracking completion of hardware tasks via descriptor fields to be a known method in the art, and the implementation of such methods would yield the predictable result of executing work descriptors while providing completion feedback to the system.
Claim 14 recites similar limitations as those of claim 5. Claim 14 is rejected for similar reasons as those of claim 5.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kakaiya in view of Raisch, further in view of Liang, further in view of Easton et al. (US 20130305247 A1) hereafter Easton.
Regarding claim 6, Kakaiya in view of Raisch, further in view of Liang teaches the method of claim 5. Kakaiya teaches:
A work descriptor (Paragraph 31; “Software client 118 creates a work descriptor and invokes the accelerator to process the descriptor (operation 1)”).
Kakaiya in view of Raisch, further in view of Liang does not teach wherein the completion indicator field comprises a plurality of bits corresponding to a plurality of supported completion indicators, and wherein adding the one or more completion indicators further comprises setting one or more bits of the plurality of bits corresponding to the one or more completion indicators.
However, Easton teaches:
wherein the completion indicator field comprises a plurality of bits (Paragraphs 160-169; “This field is set by the adapter during execution of the Establish QDIO Queues CCW command, and is set to indicate the adapter supported values before the successful completion of the command. The meaning of bits 0-1 are as follows, in one example”, where the AC field explicitly comprises multiple bits which are independently defined) corresponding to a plurality of supported completion indicators (Paragraphs 160-169; “When zero, bit 0 indicates that the adapter does not support the interruption request bit in the SBALF 0 field (described below) of the SBAL for input queues. When one, bit 0 indicates that the adapter supports the interruption request bit”, each bit corresponds to whether a particular interruption request, corresponding to completion notification mechanism, is supported), and wherein adding the one or more completion indicators further comprises setting one or more bits of the plurality of bits corresponding to the one or more completion indicators (Paragraphs 160-169; “When this bit is one at the time the Establish QDIO Queues CCW command is issued, a request to enable the subchannel for QEBSM is indicated”, and “When one, bit 0 indicates that the adapter supports the interruption request bit”, where the system sets specific bits to enable or request interrupt/completion behavior, thereby adding the desired completion indicator by setting the corresponding bit.).
Kakaiya, Raisch, Liang, and Easton are considered to be analogous to the claimed invention because they are in the same field of task management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya in view of Raisch, further in view of Liang to incorporate the teachings of Easton and incorporate the bits completion indicator field into the work descriptor of Kakaiya in view of Raisch further in view of Liang. A person of ordinary skill in the art would have recognized the method of implementing selectable interrupt/completion behavior via bitmask fields to be a known method in the art, yielding the predictable result of enabling the hardware device to selectively generate supported completion notifications based on which bits are set.
Claim 15 recites similar limitations as those of claim 6. Claim 15 is rejected for similar reasons as those of claim 6.
Claims 7 and 18 are re rejected under 35 U.S.C. 103 as being unpatentable over Kakaiya in view of Raisch, further in view of Diment et al. (US 20150220417 A1) hereafter Diment.
Regarding claim 7, Kakaiya in view of Raisch teaches the method of claim 1. Kakaiya in view of Raisch does not teach wherein a completion message of the one or more additional completion messages comprises at least one of: a timestamp, a latency statistic, or a utilization statistic.
However, Diment teaches:
wherein a completion message of the one or more additional completion messages comprises at least one of: a timestamp, a latency statistic, or a utilization statistic (Paragraph 156; “Performance data can include raw information of monitored processes and activities as well as various timestamps measuring latency of activities of interest. Analysis of performance data (block 427) can serve to determine various user computing performance metrics and statistic as well as various computing environment performance metrics and statistics (e.g. interaction response time, user interaction statistics, CPU load, memory consumption, network usage, applications usage, application activity frequencies).”, the performance data including timestamps, corresponding to the applicant’s timestamp, interaction response time, corresponding to latency statistic, and CPU load/memory consumption/network usage/applications usage/application activity frequencies, corresponding to utilization statistics.).
Kakaiya, Raisch, and Diment are considered to be analogous to the claimed invention because they are in the same field of resource management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kakaiya in view of Raisch to incorporate the teachings of Diment and include a timestamp, latency statistic, and utilization statistic in a completion message. A person of ordinary skill in the art would have recognized this as a known method of embedding performance and timing metadata in completion notifications, yielding the predictable result of enabling the host to monitor execution timing, measure performance, and manage resource utilization.
Claim 18 recites similar limitations as those of claim 7. Claim 18 is rejected for similar reasons as those of claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Johnson (US 6591310 B1) discusses a reply descriptor for transmission over an I/O message passing medium in response to a corresponding request message, the descriptor comprises at least one indication field that can function as a `flag` to identify its type, and a content field; whereby a reply message is generated only if at least one predefined condition is not met and the content field will, accordingly, comprise information of that reply message's storage location.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH P TRAN whose telephone number is (571)272-6926. The examiner can normally be reached M-TH 4:30 a.m. - 12:30 p.m. PT, F 4:30 a.m. - 8:30 a.m. PT, or at Kenneth.Tran@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571) 270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH P TRAN/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196