DETAILED ACTION
This action is responsive to the following: the amendments to claims and request for continued examination filed on May 12, 2026.
Claims 1-20 are pending. Claims 1, 7, and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2026 has been entered.
Response to Amendment
The amendments filed on May 12, 2026 are entered. Claims 1-20 remain pending.
Claim Rejections - 35 USC § 112 - lack of written description
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 14 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 7 and 14 contain the limitation of a “buried frontside wordline,” which is not described in the specification. The specification refers to “buried backside wordlines” and “frontside wordlines” separately but does not refer to a frontside wordline which is also buried.
Applicant generally asserts Figures 1-3 as alleged support, however Figures 1-3 represents all of the Figures in the application. Applicant also asserts support the “accompanying description” of Figures 1-3, which is the entire disclosure. In other words, applicant generally asserts their entire disclosure supports the amendments, but applicant has not specifically pointed out where support could be found.
Applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim limitation “buried frontside wordline” in the application as filed. MPEP 2163.04.
The term “buried” as used in the disclosure about the word lines (e.g. para. 20) appears to mean the word lines are “buried” in the substrate. The term “buried wordline” is used and this feature is described as an option (esp. para. 20: “Also, optionally, one or more wordlines (WL0, WL1) may comprise a buried wordline formed within the substrate.”). But, paragraph 20 also indicates these conductive lines are “buried within a substrate, e.g., in a buried backside metal layer.”
Applicant’s originally filed Figures 1A-1C illustrate the word lines and use labeling to indicate “frontside metal FM.”
Applicant’s originally filed Figure 2A and 2B illustrate an example SRAM row where word line 1 is a “buried backside metal BM” and word line 2 is a “frontside metal FM.”
In other words, being “buried” and being “frontside” appear to be disclosed as alternatives. The word line is either buried in the substrate (and it is the backside) or on the frontside.
Claim Rejections - 35 USC § 112 - indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent Claims 7 and 14 recite the term “buried frontside wordline,” which is indefinite for containing contradictory attributes. See written description requirement rejection supra. Based on the originally filed Specification, “buried” means buried within a substrate and “backside” seem to refer to the same trait of a metal line disposed on the backside of the semiconductor substrate. And the term “frontside” is used to describe metal layers disposed above the substrate, not buried within the substrate. All elements described as “buried” within the specification are said to be on the backside of the substrate. Therefore, the descriptor “buried frontside” in the context of the present disclosure contradicts itself. Therefore, the claim is indefinite for describing qualities that are not consistent with the disclosed technology and terminology used to describe it.
MPEP 2173.06(II) instructs examiners as follows:
II. PRIOR ART REJECTION OF CLAIM REJECTED AS INDEFINITE
All words in a claim must be considered in judging the patentability of a claim against the prior art. In re Wilson, 424 F.2d 1382, 165 USPQ 494 (CCPA 1970). The fact that terms may be indefinite does not make the claim obvious over the prior art. When the terms of a claim are considered to be indefinite, at least two approaches to the examination of an indefinite claim relative to the prior art are possible.
First, where the degree of uncertainty is not great, and where the claim is subject to more than one interpretation and at least one interpretation would render the claim unpatentable over the prior art, an appropriate course of action would be for the examiner to enter two rejections: (A) a rejection based on indefiniteness under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph; and (B) a rejection over the prior art based on the interpretation of the claims which renders the prior art applicable. See, e.g., Ex parte Ionescu, 222 USPQ 537 (Bd. App. 1984). When making a rejection over prior art in these circumstances, it is important for the examiner to point out how the claim is being interpreted. Second, where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art. As stated in In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
The first approach is recommended from an examination standpoint because it avoids piecemeal examination in the event that the examiner’s 35 U.S.C. 112, second paragraph rejection is not affirmed, and may give applicant a better appreciation for relevant prior art if the claims are redrafted to avoid the 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph rejection.
As such, these claims will be interpreted in the way that renders the prior art applicable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claims 7-11 13-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (20240251540).
Regarding Independent Claim 7, Lin teaches a device comprising:
an array of bitcells (Fig. 1A: 101) having a first bitcell (Fig. 9D, 910) disposed adjacent to a second bitcell (Fig. 9D: 911) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with multiple different wordlines (Fig 9D: WL[j], BWL[j+1]), including a frontside wordline (Fig 9D: WL[j]) and a buried wordline (Fig 9D: BWL[j]);
the frontside word line (Fig. 1A: WL[0]) coupled to first transistors (Fig. 2: T1, T2) in the first bitcell (Fig. 1A: DMC, C[k]; para 29);
the buried wordline (Fig. 1A: BWL[0]) coupled to second transistors (Fig. 2: T1, T2) in the second bitcell (Fig. 1A: MC, C[k+1];); and
a frontside ground line (Fig. 3A: VSS; para 60) coupled to the first transistors (Fig. 1A: DMC, C[k]; para 29; Fig. 2: N1, N2) and the second transistors (Fig. 1A: MC, C[k+1]; Fig. 2: N1, N2).
Regarding Claim 8, Lin teaches the limitations of claim 7. Lin further teaches the frontside wordline (Fig. 1A: WL[0]) is formed in a frontside metal layer (Fig. 3A: M0-2),
the frontside ground line (Fig. 3A: VSS; para 60) is formed in the frontside metal layer (Fig. 3A: M0-1, M0-6; para 60).
Regarding Claim 9, Lin teaches the limitations of claim 8. Lin further teaches the frontside wordline (Fig. 7: WL) and the frontside ground line (Fig. 7: M0; para 60) are formed in the frontside metal layer (Fig. 7: M0, M1) that is disposed above the buried wordline (Fig. 7: BWL), and
the buried wordline (Fig. 7: BWL) is formed in the buried backside metal layer (Fig. 7: BM1, BM3) that is disposed below the frontside wordline and the frontside ground line.
Regarding Claim 10, Lin teaches the limitations of claim 7. Lin further teaches the first bitcell (Fig. 1A: DMC, C[k]; para 29) comprises a first multi-transistor bitcell with first passgates (Fig. 2: T1, T2) coupled to first complementary bitlines (Fig. 2: BL, BLB), and
the frontside wordline (Fig. 2: WL) is coupled to gates of the first passgates (Fig. 2: T1, T2).
Regarding Claim 11, Lin teaches the limitations of claim 10. Lin further teaches the second bitcell (Fig. 1A: MC, C[k+1];) comprises a second multi-transistor bitcell with second passgates (Fig. 2: T1, T2) coupled to second complementary bitlines (Fig. 2: BL, BLB), and
the buried wordline (Fig. 2: BWL) is coupled to gates of the second passgates (Fig. 2: T1, T2).
Regarding Claim 13, Lin teaches the limitations of claim 7. Lin further teaches the first bitcell and the second bitcell are static random access memory (SRAM) bitcells (para 24) for single-port memory applications.
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Regarding Independent Claim 14, Lin teaches an array of bitcells (Fig. 1A: 101) having first bitcells (Fig. 1C: MC, 101’, 101, WL, WL’) and second bitcells,(Fig. 1C: MC, 101’, 101, BWL, BWL’) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with a plurality of different wordlines (Fig 9D: WL[j], BWL[j+1]), wherein the first bitcells are disposed in a first portion of the array, and wherein the second bitcells are disposed in a second portion of the array that is different than the first portion of the array; and
the plurality of different wordlines (Fig. 1C: BWL, BWL’, WL, WL’) including a frontside wordline (Fig. 1C: WL, WL’) and a buried wordline (Fig. 1C: BWL, BWL’) formed below the frontside wordline (Fig. 7, WL, BWL), wherein the frontside wordline couples a wordline driver (Fig. 1A: WL DRV) to the first bitcells (Fig. 1C: MC, 101’, 101, WL, WL’), and wherein the buried wordline couples the wordline driver (Fig. 1A: WL DRV) to the second bitcells (Fig. 1C: MC, 101’, 101, BWL, BWL’), and
wherein the second bitcells (Fig. 1C: MC, 101’, 101, BWL, BWL’), in the second portion of the array are closer to the wordline driver than the first bitcells in the first portion of the bitcell array (para 38).
Regarding Claim 15, Lin teaches the limitations of claim 14. Lin further teaches the buried wordline is shorter in length than the frontside wordline (Fig. 1C: WL, BWL, WL’, BWL’; para 21).
Regarding Claim 16, Lin teaches the limitations of claim 14. Lin further teaches the first bitcells (Fig. 1C: MC, WL, WL’) have first transistors (Fig. 2: T1, T2),
the frontside wordline (Fig. 1C: WL, WL’) couples the wordline driver (Fig. 1C: WL DRV) to the first transistors (Fig. 2: T1, T2) in the first bitcells (Fig. 1C: MC, WL, WL’),
the second bitcells (Fig. 1C: MC, BWL, BWL’) have second transistors (Fig. 2: T1, T2), and
the buried wordline (Fig. 1C: BWL, BWL’) couples the wordline driver (Fig. 1C: WL DRV) to the second transistors (Fig. 2: T1, T2) in the second bitcells (Fig. 1C: MC, BWL, BWL’).
Regarding Claim 17, Lin teaches the limitations of claim 16. Lin further teaches a frontside ground line (Fig. 3A: VSS; para 60) coupled to the first transistors (Fig.2: N1, N2) and the second transistors (Fig. 2: N1, N2),
wherein the frontside ground line (Fig. 3A: VSS; para 60) is formed in a frontside metal layer (Fig. 3A: M0-1, M0-6; para 60).
Regarding Claim 18, Lin teaches the limitations of claim 14. Lin further teaches the frontside wordline (Fig. 1C: WL, WL’) is formed in a frontside metal layer (Fig. 7: M1)
Regarding Claim 20, Lin teaches the limitations of claim 14. Lin further teaches the first bitcell and the second bitcell are static random access memory (SRAM) bitcells (para 24) for single-port memory applications.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (20240147684) in view of Lin et al (20240251540).
Regarding Independent Claim 1, Liaw teaches a device comprising:
an array of bitcells having a first bitcell (Fig. 6A: 10) disposed adjacent to a second bitcell (Fig. 6A: 10);
a first wordline (Fig. 2A: F-M2-WL) coupled to first transistors (Fig. 2A: PG-1, PG-2) in the first bitcell (Fig. 6A: 10);
a second wordline (Fig. 2A: F-M2-WL) coupled to second transistors (Fig. 2A: PG-1, PG-2) in the second bitcell (Fig. 6A: 10); and
a buried ground line (Fig. 2B: B-M2-CVss) coupled to the first transistors (Fig. 2B: PD-1, PD-2) and the second transistors (Fig. 2B: PD-1, PD-2).
Wherein the first wordline and the second wordline are formed in a frontside metal layer (Fig. 3B: F-M2-WL)
However, Liaw fails to teach that a first bitcell disposed adjacent to a second bitcell in a multiple wordline row of bitcells with multiple different wordlines, including a first wordline and a second wordline.
Lin teaches a first bitcell (Fig. 9D, 910) disposed adjacent to a second bitcell (Fig. 9D: 911) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with multiple different wordlines (Fig 9D: WL[j], BWL[j+1]), including a first wordline (Fig 9D: WL[j]) and a second wordline (Fig 9D: BWL[j+1]).
Having multiple word lines with separate drivers control a single row of cells reduces the load on the word line when the row is selected. This would allow for faster reading and writing of cells in a row. As there are half as many cells on the word line where there are cells having an operation performed on them.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lin to the teachings of Liaw to produce a memory cell with word lines disposed on front side metal layers and word lines disposed on a backside metal layer where multiple the row of memory cells includes multiple word lines that control bit cells disposed adjacent to one another in the row.
Regarding Claim 2, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the buried ground line is formed in a buried backside metal layer (Fig. 3B: B-M2-CVss) that is disposed below the first wordline and the second wordline (Fig. 3B: F-M2-WL).
Regarding Claim 3, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the first bitcell comprises a first multi-transistor bitcell (Fig. 2A: 10, PG-1, PG-2, PD-1, PD-2, PU-1, PU-2) with first passgates (Fig. 2A: PG-1, PG-2) coupled to first complementary bitlines (Fig. 2A: F-M1-BL, F-M1-BLB), and the first word line (Fig. 2A: F-M1-WL) is coupled to gates of the first passgates (Fig. 2A: PG-1, PG-2).
Regarding Claim 4, Liaw and Lin teach the limitations of claim 1. Liaw further teaches the second bitcell comprises a second multi-transistor bitcell (Fig. 2A: 10, PG-1, PG-2, PD-1, PD-2, PU-1, PU-2) with second passgates (Fig. 2A: PG-1, PG-2).
However, Liaw fails to teach that an adjacent bitcell coupled to a second word line also has second complimentary bit lines. Adjacent cells either share complimentary bit lines or share a common word line.
Lin however teaches a second adjacent bit cell (Fig. 1A: MC, C[k+1]) with a second word line (Fig. 1A: BWL) and second set of complimentary bit lines (Fig. 1A: BL[k+1]).
Lin at 34 states in part “Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.” Thus, combining Liaw with Lin leads to improved loading by reducing the number of cells and therefore passgates on an individual word line and would improve performance and power to distribute the adjacent bitcells across multiple word lines in a single row of cells. Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lin to the teachings of Liaw to produce a SRAM memory array with adjacent bitcells, where the word lines are disposed on front side metal lines and the ground is disposed on a buried backside metal line and each cell is controlled by different word lines and different sets of complimentary bit lines.
Regarding Claim 5, Liaw and Lin teach the limitations of claim 4.
Lin further teaches one or more precharge lines (Fig. 1a: 102) are used to precharge (para 26) at least one of the first complementary bitlines (Fig. 2: BL, BLB) and the second complementary bitlines (Fig. 2: BL, BLB).
Regarding Claim 6, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the first bitcell (Fig. 6A: 10) and the second bitcell (Fig. 6A: 10) are static random access memory (SRAM) bitcells (Fig. 2A-2B: 10; para 25) for single-port memory applications.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (20240251540) in view of Liaw (20240147684).
Regarding Claim 12, Lin teaches the limitations of claim 11. Lin further teaches a frontside precharge line (Fig. 1a: 102) formed in the frontside metal layer is used to precharge at least one of the first complementary bitlines (Fig. 2: BL, BLB).
Lin however does not teach that the bit lines are buried on a backside metal layer.
Liaw however teaches a bit line that is buried on a backside metal layer (Fig. 7D: B-M1-BL).
Lin states in paragraph 34 “in at least one embodiment, word line loading associated with the back side word line BWL[0] and the timing delay RC for accessing the memory cells MC in the second segment are reduced, and the access speed for the memory cells MC in the second segment is improved. Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.”
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Liaw to the teachings of Lin in order to produce a memory with one front side bit line and one backside bit line. Wherein the bit lines precharging is controlled by precharge lines extending from the control circuit to the bit lines as standard practice in the art. It would further be obvious to one of ordinary skill in the art to route precharge lines used to control the precharging of bit lines of backside metal using precharge lines that are also buried using backside metal.
Regarding Claim 19, Lin teaches the limitations of claim 14. Lin further teaches a frontside precharge line (Fig. 1a: 102) that precharges first complementary bitlines (Fig. 2: BL, BLB) coupled to the first bitcells (Fig. 1C: MC, WL, WL’) in the first portion of the array. Lin also teaches buried signal lines (Fig. 1C: BWL, BWL’) that are shorter than front side signal lines (para 21).
Lin however fails to teach buried precharge line that precharges second complementary bitlines coupled to the second bitcells in the second portion of the array.
Liaw however teaches a bit line that is buried on a backside metal layer (Fig. 7D: B-M1-BL).
Lin states in paragraph 34 “in at least one embodiment, word line loading associated with the back side word line BWL[0] and the timing delay RC for accessing the memory cells MC in the second segment are reduced, and the access speed for the memory cells MC in the second segment is improved. Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.” Thus, as similar benefit could be gained using the same principal for the precharge lines to drive the bit lines to a specific voltage during a read or write operation. Reducing the length of precharge line, such as through a back side precharge line distributed to only the nearest portion of an array to reducing loading. And reducing the number of bit lines on a pre charge line would similarly reduce loading by splitting the bit lines attached to a precharge line in a row to one of either a precharge line on either the front or back side.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Liaw to the teachings of Lin in order to produce a memory with one front side bit line and one backside bit line. Wherein the bit lines precharging is controlled by precharge lines extending from the control circuit to the bit lines as standard practice in the art. It would further be obvious to one of ordinary skill in the art to route precharge lines used to control the precharging of bit lines of backside metal using precharge lines that are also buried using backside metal. And applying the teachings of line with regards to other signal lines, such as word lines that the buried precharge lines would be shorter than the front side precharge lines.
Response to Arguments
Applicant's arguments filed May 12, 2026 have been fully considered but they are not persuasive.
Applicants arguments with respect to the anticipation rejection under 35 U.S.C. 102 of claims 7 and 14 rely solely on the amendment describing frontside word lines. Since this term is indefinite describing contradictory qualities of a metal layer and because applicant does not appear to be in possession of this limitation, this limitation will be ignored and thus the previous rejection will be maintained.
Applicant arguments with respect to the obviousness rejection under 35 U.S.C. 103 of claim 1, applicant argues against the references Liaw and Lin individually in order to show nonobviousness. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Therefore, the rejection is maintained.
Furthermore, the recent amendments raise issues of indefiniteness and new subject matter. Claims 7 and 14, for example, recite “buried frontside wordlines”; however the term does not appear to be expressly used in the written description or in the drawings and the applicant has not pointed to specific elements in the drawings or paragraphs in the specification where the description of “buried frontside wordlines” can be found.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sheppard (US 7092279 B1) shows an SRAM array where the rows of bit cells utilize multiple word lines, where even cells receive an even word line in the row and odd cells receive an odd word line.
Wendell at all (US 5883826 A) shows multiple wordline rows, where bit cells alternate through the row receive either the truth or compliment of the address signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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