DETAILED ACTION
This action is responsive to the Amendments to Claims and arguments made in amendment filed on October 16, 2025.
Claims 1-20 are pending. Claims 1, 7, and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed October 16, 2025 have been entered. Claims 1-20 remain pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claims 7-11 13-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (20240251540).
Regarding Independent Claim 7, Lin teaches a device comprising:
an array of bitcells (Fig. 1A: 101) having a first bitcell (Fig. 9D, 910) disposed adjacent to a second bitcell (Fig. 9D: 911) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with multiple different wordlines (Fig 9D: WL[j], BWL[j+1]), includinq a frontside wordline (Fig 9D: WL[j]) and a buried wordline (Fig 9D: BWL[j]);
the frontside word line (Fig. 1A: WL[0]) coupled to first transistors (Fig. 2: T1, T2) in the first bitcell (Fig. 1A: DMC, C[k]; para 29);
the buried wordline (Fig. 1A: BWL[0]) coupled to second transistors (Fig. 2: T1, T2) in the second bitcell (Fig. 1A: MC, C[k+1];); and
a frontside ground line (Fig. 3A: VSS; para 60) coupled to the first transistors (Fig. 1A: DMC, C[k]; para 29; Fig. 2: N1, N2) and the second transistors (Fig. 1A: MC, C[k+1]; Fig. 2: N1, N2).
Regarding Claim 8, Lin teaches the limitations of claim 7. Lin further teaches the frontside wordline (Fig. 1A: WL[0]) is formed in a frontside metal layer (Fig. 3A: M0-2),
the buried wordline (Fig. 1A: BWL[0]) is formed in a buried backside metal layer (Fig. 5: BM0-2), and
the frontside ground line (Fig. 3A: VSS; para 60) is formed in the frontside metal layer (Fig. 3A: M0-1, M0-6; para 60).
Regarding Claim 9, Lin teaches the limitations of claim 8. Lin further teaches the frontside wordline (Fig. 7: WL) and the frontside ground line (Fig. 7: M0; para 60) are formed in the frontside metal layer (Fig. 7: M0, M1) that is disposed above the buried wordline (Fig. 7: BWL), and
the buried wordline (Fig. 7: BWL) is formed in the buried backside metal layer (Fig. 7: BM1, BM3) that is disposed below the frontside wordline and the frontside ground line.
Regarding Claim 10, Lin teaches the limitations of claim 7. Lin further teaches the first bitcell (Fig. 1A: DMC, C[k]; para 29) comprises a first multi-transistor bitcell with first passgates (Fig. 2: T1, T2) coupled to first complementary bitlines (Fig. 2: BL, BLB), and
the frontside wordline (Fig. 2: WL) is coupled to gates of the first passgates (Fig. 2: T1, T2).
Regarding Claim 11, Lin teaches the limitations of claim 10. Lin further teaches the second bitcell (Fig. 1A: MC, C[k+1];) comprises a second multi-transistor bitcell with second passgates (Fig. 2: T1, T2) coupled to second complementary bitlines (Fig. 2: BL, BLB), and
the buried wordline (Fig. 2: BWL) is coupled to gates of the second passgates (Fig. 2: T1, T2).
Regarding Claim 13, Lin teaches the limitations of claim 7. Lin further teaches the first bitcell and the second bitcell are static random access memory (SRAM) bitcells (para 24) for single-port memory applications.
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Regarding Independent Claim 14, Lin teaches an array of bitcells (Fig. 1A: 101) having first bitcells (Fig. 1C: MC, 101’, 101, WL, WL’) and second bitcells,(Fig. 1C: MC, 101’, 101, BWL, BWL’) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with a plurality of different wordlines (Fig 9D: WL[j], BWL[j+1]), wherein the first bitcells are disposed in a first portion of the array, and wherein the second bitcells are disposed in a second portion of the array that is different than the first portion of the array; and
the plurality of different wordlines (Fig. 1C: BWL, BWL’, WL, WL’) including a frontside wordline (Fig. 1C: WL, WL’) and a buried wordline (Fig. 1C: BWL, BWL’) formed below the frontside wordline (Fig. 7, WL, BWL), wherein the frontside wordline couples a wordline driver (Fig. 1A: WL DRV) to the first bitcells (Fig. 1C: MC, 101’, 101, WL, WL’), and wherein the buried wordline couples the wordline driver (Fig. 1A: WL DRV) to the second bitcells (Fig. 1C: MC, 101’, 101, BWL, BWL’), and
wherein the second bitcells (Fig. 1C: MC, 101’, 101, BWL, BWL’), in the second portion of the array are closer to the wordline driver than the first bitcells in the first portion of the bitcell array (para 38).
Regarding Claim 15, Lin teaches the limitations of claim 14. Lin further teaches the buried wordline is shorter in length than the frontside wordline (Fig. 1C: WL, BWL, WL’, BWL’; para 21).
Regarding Claim 16, Lin teaches the limitations of claim 14. Lin further teaches the first bitcells (Fig. 1C: MC, WL, WL’) have first transistors (Fig. 2: T1, T2),
the frontside wordline (Fig. 1C: WL, WL’) couples the wordline driver (Fig. 1C: WL DRV) to the first transistors (Fig. 2: T1, T2) in the first bitcells (Fig. 1C: MC, WL, WL’),
the second bitcells (Fig. 1C: MC, BWL, BWL’) have second transistors (Fig. 2: T1, T2), and
the buried wordline (Fig. 1C: BWL, BWL’) couples the wordline driver (Fig. 1C: WL DRV) to the second transistors (Fig. 2: T1, T2) in the second bitcells (Fig. 1C: MC, BWL, BWL’).
Regarding Claim 17, Lin teaches the limitations of claim 16. Lin further teaches a frontside ground line (Fig. 3A: VSS; para 60) coupled to the first transistors (Fig.2: N1, N2) and the second transistors (Fig. 2: N1, N2),
wherein the frontside ground line (Fig. 3A: VSS; para 60) is formed in a frontside metal layer (Fig. 3A: M0-1, M0-6; para 60).
Regarding Claim 18, Lin teaches the limitations of claim 14. Lin further teaches the frontside wordline (Fig. 1C: WL, WL’) is formed in a frontside metal layer (Fig. 7: M1), and
the buried wordline (Fig. 1C: BWL, BWL’) is formed beneath the frontside wordline (Fig. 1C: WL, WL’) in a buried backside metal layer (Fig. 7: BM1, BM3) that is disposed below the frontside metal layer (Fig. 7: M1).
Regarding Claim 20, Lin teaches the limitations of claim 14. Lin further teaches the first bitcell and the second bitcell are static random access memory (SRAM) bitcells (para 24) for single-port memory applications.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (20240147684) in view of Lin et al (20240251540).
Regarding Independent Claim 1, Liaw teaches a device comprising:
an array of bitcells having a first bitcell (Fig. 6A: 10) disposed adjacent to a second bitcell (Fig. 6A: 10);
a first wordline (Fig. 2A: F-M2-WL) coupled to first transistors (Fig. 2A: PG-1, PG-2) in the first bitcell (Fig. 6A: 10);
a second wordline (Fig. 2A: F-M2-WL) coupled to second transistors (Fig. 2A: PG-1, PG-2) in the second bitcell (Fig. 6A: 10); and
a buried ground line (Fig. 2B: B-M2-CVss) coupled to the first transistors (Fig. 2B: PD-1, PD-2) and the second transistors (Fig. 2B: PD-1, PD-2).
However, Liaw fails to teach that a first bitcell disposed adjacent to a second bitcell in a multiple wordline row of bitcells with multiple different wordlines, includinq a first wordline and a second wordline.
Lin teaches a first bitcell (Fig. 9D, 910) disposed adjacent to a second bitcell (Fig. 9D: 911) in a multiple wordline row (Fig. 9D: R[j]) of bitcells with multiple different wordlines (Fig 9D: WL[j], BWL[j+1]), includinq a first wordline (Fig 9D: WL[j]) and a second wordline (Fig 9D: BWL[j+1]).
Having multiple word lines with separate drivers control a single row of cells reduces the load on the word line when the row is selected. This would allow for faster reading and writing of cells in a row. As there are half as many cells on the word line where there are cells having an operation performed on them.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lin to the teachings of Liaw to produce a memory cell with word lines disposed on front side metal layers and word lines disposed on a backside metal layer where multiple the row of memory cells includes multiple word lines that control bit cells disposed adjacent to one another in the row.
Regarding Claim 2, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the first wordline and the second wordline are formed in a frontside metal layer (Fig. 3B: F-M2-WL) that is disposed above the buried ground line (Fig. 3B: B-M2-CVss), and
the buried ground line is formed in a buried backside metal layer (Fig. 3B: B-M2-CVss) that is disposed below the first wordline and the second wordline (Fig. 3B: F-M2-WL).
Regarding Claim 3, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the first bitcell comprises a first multi-transistor bitcell (Fig. 2A: 10, PG-1, PG-2, PD-1, PD-2, PU-1, PU-2) with first passgates (Fig. 2A: PG-1, PG-2) coupled to first complementary bitlines (Fig. 2A: F-M1-BL, F-M1-BLB), and the first word line (Fig. 2A: F-M1-WL) is coupled to gates of the first passgates (Fig. 2A: PG-1, PG-2).
Regarding Claim 4, Liaw and Lin teach the limitations of claim 1. Liaw further teaches the second bitcell comprises a second multi-transistor bitcell (Fig. 2A: 10, PG-1, PG-2, PD-1, PD-2, PU-1, PU-2) with second passgates (Fig. 2A: PG-1, PG-2).
However, Liaw fails to teach that an adjacent bitcell coupled to a second word line also has second complimentary bit lines. Adjacent cells either share complimentary bit lines or share a common word line.
Lin however teaches a second adjacent bit cell (Fig. 1A: MC, C[k+1]) with a second word line (Fig. 1A: BWL) and second set of complimentary bit lines (Fig. 1A: BL[k+1]).
Lin at 34 states in part “Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.” Thus, combining Liaw with Lin leads to improved loading by reducing the number of cells and therefore passgates on an individual word line and would improve performance and power to distribute the adjacent bitcells across multiple word lines in a single row of cells. Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lin to the teachings of Liaw to produce a SRAM memory array with adjacent bitcells, where the word lines are disposed on front side metal lines and the ground is disposed on a buried backside metal line and each cell is controlled by different word lines and different sets of complimentary bit lines.
Regarding Claim 5, Liaw and Lin teach the limitations of claim 4.
Lin further teaches one or more precharge lines (Fig. 1a: 102) are used to precharge (para 26) at least one of the first complementary bitlines (Fig. 2: BL, BLB) and the second complementary bitlines (Fig. 2: BL, BLB).
Regarding Claim 6, Liaw and Lin teach the limitations of Claim 1. Liaw further teaches the first bitcell (Fig. 6A: 10) and the second bitcell (Fig. 6A: 10) are static random access memory (SRAM) bitcells (Fig. 2A-2B: 10; para 25) for single-port memory applications.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (20240251540) in view of Liaw (20240147684).
Regarding Claim 12, Lin teaches the limitations of claim 11. Lin further teaches a frontside precharge line (Fig. 1a: 102) formed in the frontside metal layer is used to precharge at least one of the first complementary bitlines (Fig. 2: BL, BLB).
Lin however does not teach that the bit lines are buried on a backside metal layer.
Liaw however teaches a bit line that is buried on a backside metal layer (Fig. 7D: B-M1-BL).
Lin states in paragraph 34 “in at least one embodiment, word line loading associated with the back side word line BWL[0] and the timing delay RC for accessing the memory cells MC in the second segment are reduced, and the access speed for the memory cells MC in the second segment is improved. Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.”
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Liaw to the teachings of Lin in order to produce a memory with one front side bit line and one backside bit line. Wherein the bit lines precharging is controlled by precharge lines extending from the control circuit to the bit lines as standard practice in the art. It would further be obvious to one of ordinary skill in the art to route precharge lines used to control the precharging of bit lines of backside metal using precharge lines that are also buried using backside metal.
Regarding Claim 19, Lin teaches the limitations of claim 14. Lin further teaches a frontside precharge line (Fig. 1a: 102) that precharges first complementary bitlines (Fig. 2: BL, BLB) coupled to the first bitcells (Fig. 1C: MC, WL, WL’) in the first portion of the array. Lin also teaches buried signal lines (Fig. 1C: BWL, BWL’) that are shorter than front side signal lines (para 21).
Lin however fails to teach buried precharge line that precharges second complementary bitlines coupled to the second bitcells in the second portion of the array.
Liaw however teaches a bit line that is buried on a backside metal layer (Fig. 7D: B-M1-BL).
Lin states in paragraph 34 “in at least one embodiment, word line loading associated with the back side word line BWL[0] and the timing delay RC for accessing the memory cells MC in the second segment are reduced, and the access speed for the memory cells MC in the second segment is improved. Further, because the front side word line WL[0] is physically shorter and does not extend into the second bank 112, resistance and capacitance associated with the front side word line WL[0] are reduced. As a result, in at least one embodiment, word line loading associated with the front side word line WL[0] is reduced which, together with the reduced word line loading associated with the back side word line BWL[0], reduces loading on the word line driver 130 and improves performance and/or power consumption of the memory device 100A.” Thus, as similar benefit could be gained using the same principal for the precharge lines to drive the bit lines to a specific voltage during a read or write operation. Reducing the length of precharge line, such as through a back side precharge line distributed to only the nearest portion of an array to reducing loading. And reducing the number of bit lines on a pre charge line would similarly reduce loading by splitting the bit lines attached to a precharge line in a row to one of either a precharge line on either the front or back side.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Liaw to the teachings of Lin in order to produce a memory with one front side bit line and one backside bit line. Wherein the bit lines precharging is controlled by precharge lines extending from the control circuit to the bit lines as standard practice in the art. It would further be obvious to one of ordinary skill in the art to route precharge lines used to control the precharging of bit lines of backside metal using precharge lines that are also buried using backside metal. And applying the teachings of line with regards to other signal lines, such as word lines that the buried precharge lines would be shorter than the front side precharge lines.
Response to Arguments
Applicant's arguments filed October 16, 2025 have been fully considered but they are not persuasive.
Applicant’s arguments relied solely on the amendment to Independent Claims 1, 7, and 14 that specifies that the first and second bitcells are adjacent to each other in multiple wordline rows. Lin teaches multiple word line rows as shown in Fig. 9D where a separate front side word line (Fig. 9D: WL[j]) and backside word line (Fig. 9D: BWL[j+1]) are shown to have separate drivers (Fig. 9D: DRV[j], DRV[j+1]) and are indexed separately.
Thus the original basis for rejection of Independent claims 7 and 14 is proper and maintained. And Claim 1 is now rejected under the combination of Liaw and Lin under 35 U.S.C. 103, since using multiple wordline rows represents an obvious change to the metal layer layout for SRAM cells proposed by Liaw.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sheppard (US 7092279 B1) shows an SRAM array where the rows of bit cells utilize multiple word lines, where even cells receive an even word line in the row and odd cells receive an odd word line.
Wendell at all (US 5883826 A) shows multiple wordline rows, where bit cells alternate through the row receive either the truth or compliment of the address signal.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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