DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Request for Continued Examination (RCE) on 12/01/2025.
Specification
The disclosure is objected to because of the following informalities: the Specification should be revised carefully because it contains some typographical errors (Example: page 8; paragraph [0032]; recites “the system may alternatively be configured as a buck converter (e.g., as illustrated in FIG. 14A and FIG. 14B)”, which should be “the system may alternatively be configured as a buck converter (e.g., as illustrated in FIG. 12A and FIG. 12B”).
Appropriate correction is required.
Claim Objections
Claim 10 is objected to because of the following informalities: Claim 10, lines 26-27 recites “the first input of the second modulator coupled to the first current feedback terminal”, which should be -- the first input of the second modulator coupled to the second current feedback terminal -- because in this way is supported in Figure 2, parts 104-114; Claim 10, lines 35 recites “the first current feedback terminal”, which should be -- the second current feedback terminal -- because in this way is supported in Figure 2, parts 104-114.
Appropriate correction is required.
Claim 13 is objected to because of the following informalities: Claim 13, lines 1-2 recites “the first and second processing circuitries”, which should be -- a first and second processing circuitries -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7-13, 15-17, 19, 21 and 22 rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Takenaka (US 2017/0214318).
Regarding claim 1, Takenaka discloses (see figures 1-16) a circuit (figures 7 and 15) comprising: a modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) having a first input (figure 7, part first input at lower terminal of 206), a second input (figure 7, part second input at upper terminal of 206), a first output (figure 15, part first output of 200a connected to M4), and a second output (figure 15, part second output of 200a connected to M3) (paragraph [0118]; The step-down converter 410 or otherwise the step-up converter 420 corresponds to the DC/DC converter 100 described above in the embodiment. FIG. 15 shows the DC/DC converter having a single-channel configuration. Also, such a DC/DC converter may have a multi-channel/multi-phase configuration), the first input of the modulator (figure 7, part first input at lower terminal of 206) coupled to a current feedback terminal (figure 7, part current feedback terminal at CS1-CSM); an error amplifier (figure 7, part 202) having a first input (figure 7, part lower input of 202), a second input (figure 7, part upper input of 202), and an output (figure 7, part output of 202), the first input of the error amplifier (figure 7, part lower input of 202) coupled to a voltage feedback terminal (figure 7, part voltage feedback terminal at VS), the second input of the error amplifier (figure 7, part upper input of 202) coupled to a reference voltage terminal (figure 7, part Vref terminal); processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) (paragraphs [0076]-[0082]) having a first input (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), a second input (figures 7 and 10, part second input at 220 from VIS1-VSM), a third input (figures 7 and 10, part third input at Iave), and an output (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input of the processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr) coupled to the output of the error amplifier (figure 7, part Verr of 202), the second input of the processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) coupled to the current feedback terminal (figure 7, part current feedback terminal at CS1-CSM), the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the second input of the modulator (figure 7, part second input at upper terminal of 206); and averaging circuitry (figure 10, part 226) coupled between the third input of the processing circuitry (figures 7 and 10, part third input at Iave) and the current feedback terminal (figures 7 and 10, part current feedback terminal at CS1-CSM; through VIS1-VSM) (paragraph [0122]; The current balance circuit 220a shown in FIG. 10 may include an averaging circuit that generates an average value of the current detection signals VIS instead of the sample-and-hold circuits 222. Such an averaging circuit may be configured as a low-pass filter).
Regarding claim 2, Takenaka discloses everything claimed as applied above (see claim 1). Further, Takenaka discloses (see figures 1-16) the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) includes: summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) having a first input (figure 11, part first input of 230_1-230_M from Verr), a second input (figure 10, part second input of 228_1-228_M from 224_1-224_M), a third input (figure 10, part third input of 228_1-228_M from 226), and an output (figures 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input of the summing circuitry (figure 12, part first input of 230_1-230_M from Verr) coupled to the first input of the processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), and the output of the summing circuitry (figures 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M); and peak tracking circuitry (figure 10, part peak tracking circuitry generated by 222_1-222_M and 224_1-224_M) coupled between the second input of the processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) and the second input of the summing circuitry (figure 10, part second input of 228_1-228_M from 224_1-224_M) (paragraph [0096]; the current balance control operation is performed such that the peaks of the coil currents IL matches each other as described above, the sample-and-hold circuit 222_i may preferably perform the sampling operation at a timing of the peak of the current detection signal VISi).
Regarding claim 7, Takenaka discloses everything claimed as applied above (see claim 1). Further, Takenaka discloses (see figures 1-16) the modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) is coupled in a first feedback path (figure 7, part first feedback path from CS1-CSM to modulator 204_1-204_M) including the current feedback terminal (figure 7, part current feedback terminal at CS1-CSM) and the first input of the modulator (figure 7, part first input at lower terminal of 206), wherein the error amplifier (figure 7, part 202) and the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) are coupled in a second feedback path (figure 7, part second feedback path from VS to processing circuitry generated by 220 and 250) including the voltage feedback terminal (figure 7, part voltage feedback terminal at VS), the first input of the error amplifier (figure 7, part lower input of 202), the output of the error amplifier (figure 7, part output of 202), the first input of the processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), and the second input of the modulator (figure 7, part second input at upper terminal of 206), and wherein the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) is coupled in a third feedback path (figure 7, part third feedback path from CS1-CSM to 220) including the current feedback terminal (figure 7, part current feedback terminal at CS1-CSM), the second input of the processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM), the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), and the second input of the modulator (figure 7, part second input at upper terminal of 206).
Regarding claim 8, Takenaka discloses everything claimed as applied above (see claim 1). Further, Takenaka discloses (see figures 1-16) a first transistor (figure 15, part M4) having a first terminal, a second terminal, and a control terminal (figure 15, part M4; a first terminal, a second terminal, and a control terminal), the control terminal of the first transistor (figure 15, part M4; control terminal) coupled to the first output of the modulator (figure 15, part first output of 200a connected to M4); and a second transistor (figure 15, part M3) having a first terminal, a second terminal, and a control terminal (figure 15, part M3; a first terminal, a second terminal, and a control terminal), the first terminal of the second transistor (figure 15, part M3; upper first terminal) coupled to the second terminal of the first transistor (figure 15, part M4; lower second terminal), the control terminal of the second transistor (figure 15, part M3; control terminal) coupled to the second output of the modulator (figure 15, part second output of 200a connected to M3).
Regarding claim 9, Takenaka discloses (see figures 1-16) a system (figures 7 and 10) comprising: a first switching circuit (figure 7, part first switching circuit generated by M11[figure 15, part as M3]/D11[figure 15, part as M4]) coupled to a power input (figure 7, part power input at Vin) and a power output (figure 7, part power output at Vout); a second switch circuit (figure 7, part second switching circuit generated by M12[figure 15, part as M3]/D12[figure 15, part as M4]) coupled to the power input (figure 7, part power input at Vin) and the power output (figure 7, part power output at Vout) (paragraph [0118]; The step-down converter 410 or otherwise the step-up converter 420 corresponds to the DC/DC converter 100 described above in the embodiment. FIG. 15 shows the DC/DC converter having a single-channel configuration. Also, such a DC/DC converter may have a multi-channel/multi-phase configuration); a first inductor (figure 7, part L11) coupled to the first switching circuit (figure 7, part first switching circuit generated by M11[figure 15, part as M3]/D11[figure 15, part as M4]); a second inductor (figure 7, part L12) coupled to the second switching circuit (figure 7, part second switching circuit generated by M12[figure 15, part as M3]/D12[figure 15, part as M4]); a first control circuit (figure 7, part first control circuit generated by 202, 220, 250, 204_1 and 212_1) having inputs coupled to the power output (figure 7, part input at VS from Vout) and the first inductor (figure 7, part input at CS1 from VIS1) and outputs (figure 15, part outputs from 200a to M3/M4) coupled to the first switching circuit (figure 7, part first switching circuit generated by M11[figure 15, part as M3]/D11[figure 15, part as M4]), the first control circuit (figure 7, part first control circuit generated by 202, 220, 250, 204_1 and 212_1) configurable to, responsive to states of its inputs (figure 7, parts input at VS from Vout and input at CS1 from VIS1), provide first switching signals to the first switching circuit (figure 7, part first switching circuit generated by M11[figure 15, part as M3]/D11[figure 15, part as M4]) to cause a first current to flow through the first inductor (figure 7, part current flow through L11) (paragraph [0056]; A voltage drop occurs across both ends of the current sensing resistor R1 in proportion to the current (i.e., coil current) that flows through the switching transistor M1 in the on period of the switching transistor M1); and a second control circuit (figure 7, part second control circuit generated by 202, 220, 250, 204_2 and 212_2) having inputs coupled to the power output (figure 7, part input at VS from Vout) and the second inductor (figure 7, part input at CS2 from VIS2) and outputs (figure 15, part outputs from 200a to M3/M4) coupled to the second switching circuit (figure 7, part second switching circuit generated by M12[figure 15, part as M3]/D12[figure 15, part as M4]), the second control circuit (figure 7, part second control circuit generated by 202, 220, 250, 204_2 and 212_2) configurable to, responsive to states of its inputs (figure 7, part input at VS from Vout and input at CS2 from VIS2), provide second switching signals to the second switching circuit (figure 7, part second switching circuit generated by M12[figure 15, part as M3]/D12[figure 15, part as M4]) to cause a second current to flow through the second inductor (figure 7, part current flow through L12) (paragraph [0056]; A voltage drop occurs across both ends of the current sensing resistor R1 in proportion to the current (i.e., coil current) that flows through the switching transistor M1 in the on period of the switching transistor M1), the first (figure 7, part current flow through L11) and second current (figure 7, part current flow through L12) having a same average in a switching cycle (figure 7, part through current balance circuit 220) (paragraphs [0076]-[0082]; With such a control circuit 200a, the current balance circuit 220 performs the correction operation such that the peak value of the coil current ILi of each channel CHi approaches the peak average IPEAKAVE of the coil currents IL1 through ILM of all the channels CH1 through CHM. Thus, such an operation corrects the coil currents of all the channels such that their peaks match each other. This provides improved current balance among all the channels).
Regarding claim 10, Takenaka discloses everything claimed as applied above (see claim 11). Further, Takenaka discloses (see figures 1-16) the inputs of the first control circuit (figure 7, parts input at VS from Vout and input at CS1 from VIS1) include a first current feedback terminal (figure 7, part CS1) coupled to the first inductor (figure 7, part L11; through M11), a first voltage feedback terminal (figure 7, part first voltage feedback terminal at VS) coupled to the power output (figure 7, part power output at Vout), and a first reference voltage terminal (figure 7, part first reference voltage terminal at Vref), and the first control circuit (figure 7, part first control circuit generated by 202, 220, 250, 204_1 and 212_1) has first outputs (figure 15, part outputs from 200a to M3/M4) coupled to the first switching circuit (figure 7, part first switching circuit generated by M11[figure 15, part as M3]/D11[figure 15, part as M4]); wherein the first control circuit (figure 7, part first control circuit generated by 202, 220, 250, 204_1 and 212_1) includes: a first modulator (figure 7, part 204_1) having a first input (figure 7, part first input at lower terminal of 206), a second input (figure 7, part second input at upper terminal of 206), a first output (figure 15, part first output of 200a connected to M4 [D11]), and a second output (figure 15, part second output of 200a connected to M3 [M11]), the first input of the first modulator (figure 7, part first input at lower terminal of 206) coupled to the first current feedback terminal (figure 7, part CS1); a first error amplifier (figure 7, part first error amplifier generated by 202) having a first input (figure 7, part lower input of the first error amplifier generated by 202), a second input (figure 7, part upper input of the first error amplifier generated by 202), and an output (figure 7, part output of the first error amplifier generated by 202), the first input of the first error amplifier (figure 7, part lower input of the first error amplifier generated by 202) coupled to the first voltage feedback terminal (figure 7, part first voltage feedback terminal at VS), the second input of the first error amplifier (figure 7, part upper input of the first error amplifier generated by 202) coupled to the first reference voltage terminal (figure 7, part first reference voltage terminal at Vref); first processing circuitry (figure 7, part first processing circuitry generated by 220 and 250; between 202 and 204) having a first input (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), a second input (figures 7 and 10, part second input at 220 from VIS1-VSM), a third input (figures 7 and 10, part third input at Iave), and an output (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input of the first processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr) coupled to the output of the first error amplifier (figure 7, part output of the first error amplifier generated by 202), the second input of the processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) coupled to the first current feedback terminal (figure 7, part CS1), the output of the first processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the second input of the first modulator (figure 7, part second input at upper terminal of 206 at 204_1); and first averaging circuitry (figure 10, part 226) coupled between the third input of the first processing circuitry (figures 7 and 10, part third input at Iave) and the first current feedback terminal (figure 7, part CS1); wherein the inputs of the second control circuit (figure 7, part input at VS from Vout and input at CS2 from VIS2) include a second current feedback terminal (figure 7, part CS2) coupled to the second inductor (figure 7, part L12), a second voltage feedback terminal (figure 7, part second voltage feedback terminal at VS) coupled to the power output (figure 7, part power output at Vout), and a second reference voltage terminal (figure 7, part second reference voltage terminal at Vref) coupled to the first reference voltage terminal (figure 7, part first reference voltage terminal at Vref), and the second control circuit (figure 7, part second control circuit generated by 202, 220, 250, 204_2 and 212_2) has second outputs (figure 15, part outputs from 200a to M3/M4) coupled to the second switching circuit (figure 7, part second switching circuit generated by M12[figure 15, part as M3]/D12[figure 15, part as M4]); and wherein the second control circuit (figure 7, part second control circuit generated by 202, 220, 250, 204_2 and 212_2) includes: a second modulator (figure 7, part 204_2) having a first input (figure 7, part first input at lower terminal of 206), a second input (figure 7, part second input at upper terminal of 206), a first output (figure 15, part first output of 200a connected to M4 [D12]), and a second output (figure 15, part second output of 200a connected to M3 [M12]), the first input of the second modulator (figure 7, part first input at lower terminal of 206) coupled to the second current feedback terminal [based on objection presented above] (figure 7, part CS2); a second error amplifier (figure 7, part second error amplifier generated by 202) having a first input (figure 7, part lower input of the second error amplifier generated by 202), a second input (figure 7, part upper input of the second error amplifier generated by 202), and an output (figure 7, part output of the second error amplifier generated by 202), the first input of the second error amplifier (figure 7, part lower input of the second error amplifier generated by 202) coupled to the second voltage feedback terminal (figure 7, part second voltage feedback terminal at VS), the second input of the second error amplifier (figure 7, part upper input of the second error amplifier generated by 202) coupled to the second reference voltage terminal (figure 7, part second reference voltage terminal at Vref); second processing circuitry (figure 7, part second processing circuitry generated by 220 and 250; between 202 and 204) having a first input (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), a second input (figures 7 and 10, part second input at 220 from VIS1-VSM), a third input (figures 7 and 10, part third input at Iave), and an output (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input of the second processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr) coupled to the output of the second error amplifier (figure 7, part output of the second error amplifier generated by 202), the second input of the processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) coupled to the second current feedback terminal [based on objection presented above] (figure 7, part CS2), the output of the second processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the second input of the second modulator (figure 7, part second input at upper terminal of 206 at 204_2); and second averaging circuitry (figure 10, part 226) coupled between the third input of the (figures 7 and 10, part third input at Iave) of the second processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M) and the second current feedback terminal (figure 7, part CS2).
Regarding claim 11, Takenaka discloses everything claimed as applied above (see claim 10). Further, Takenaka discloses (see figures 1-16) first inductor has first inductance (figure 7, part L11), and wherein the second inductor has second inductance (figure 7, part L12) different than first inductance (figure 7, part L11).
Regarding claim 12, Takenaka discloses everything claimed as applied above (see claim 10). Further, Takenaka discloses (see figures 1-16) a first current sensor (figure 7, part first current sensor generated by R11) and a second current sensor (figure 7, part second current sensor generated by R12), the first current sensor (figure 7, part first current sensor generated by R11) coupled between the first inductor (figure 7, part L11; through M11) and each of the second input of the first processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) and an input of the first averaging circuitry (figure 10, part 226) (paragraph [0122]; The current balance circuit 220a shown in FIG. 10 may include an averaging circuit that generates an average value of the current detection signals VIS instead of the sample-and-hold circuits 222. Such an averaging circuit may be configured as a low-pass filter), and the second current sensor (figure 7, part second current sensor generated by R12) coupled between the second inductor (figure 7, part L12; through M12) and each of the second input of the second processing circuitry (figures 7 and 10, part second input at 220 from VIS1-VSM) and an input of the second averaging circuitry (figure 10, part input of 226) (paragraph [0122]; The current balance circuit 220a shown in FIG. 10 may include an averaging circuit that generates an average value of the current detection signals VIS instead of the sample-and-hold circuits 222. Such an averaging circuit may be configured as a low-pass filter), wherein the first current sensor (figure 7, part first current sensor generated by R11) includes a first current sense resistor having a first resistance (figure 7, part R11), and wherein the second current sensor (figure 7, part second current sensor generated by R12) includes a second current sense resistor having a second resistance (figure 7, part R12) different than the first resistance (figure 7, part R11) (paragraph [0056]; The current sensing resistor R1 provided for each channel is arranged between the corresponding switching transistor M1 and the ground. A voltage drop occurs across both ends of the current sensing resistor R1 in proportion to the current (i.e., coil current) that flows through the switching transistor M1 in the on period of the switching transistor M1. The voltage drop that occurs across the current sensing resistor R1 is input as the current detection signal VIS to the corresponding CS terminal).
Regarding claim 13, Takenaka discloses everything claimed as applied above (see claim 9). Further, Takenaka discloses (see figures 1-16) each of the first (figure 7, part first processing circuitry generated by 220 and 250; between 202 and 204) and second processing circuitries (figure 7, part second processing circuitry generated by 220 and 250; between 202 and 204) includes respective summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) and respective peak tracking circuitry (figure 10, part peak tracking circuitry generated by 222_1-222_M and 224_1-224_M).
Regarding claim 15, Takenaka discloses (see figures 1-16) a circuit (figures 7 and 15) comprising: a modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) having a first input (figure 7, part first input at lower terminal of 206), a second input (figure 7, part second input at upper terminal of 206), a first output (figure 15, part first output of 200a connected to M4), and a second output (figure 15, part second output of 200a connected to M3) (paragraph [0118]; The step-down converter 410 or otherwise the step-up converter 420 corresponds to the DC/DC converter 100 described above in the embodiment. FIG. 15 shows the DC/DC converter having a single-channel configuration. Also, such a DC/DC converter may have a multi-channel/multi-phase configuration), the first input of the modulator (figure 7, part first input at lower terminal of 206) coupled to a current feedback terminal (figure 7, part current feedback terminal at CS1-CSM); an error amplifier (figure 7, part 202) having a first input (figure 7, part lower input of 202), a second input (figure 7, part upper input of 202), and an output (figure 7, part output of 202), the first input of the error amplifier (figure 7, part lower input of 202) coupled to a voltage feedback terminal (figure 7, part voltage feedback terminal at VS), the second input of the error amplifier (figure 7, part upper input of 202) coupled to a reference voltage terminal (figure 7, part Vref terminal); processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) (paragraphs [0076]-[0082]) having a first input (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), a second input (figures 7 and 10, part second input at Iave), and an output (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input of the processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr) coupled to the output of the error amplifier (figure 7, part Verr of 202), and the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the second input of the modulator (figure 7, part second input at upper terminal of 206); and averaging circuitry (figure 10, part 226) coupled between the second input of the processing circuitry (figures 7 and 10, part second input at Iave) and the current feedback terminal (figures 7 and 10, part current feedback terminal at CS1-CSM; through VIS1-VSM) (paragraph [0122]; The current balance circuit 220a shown in FIG. 10 may include an averaging circuit that generates an average value of the current detection signals VIS instead of the sample-and-hold circuits 222. Such an averaging circuit may be configured as a low-pass filter).
Regarding claim 16, Takenaka discloses everything claimed as applied above (see claim 15). Further, Takenaka discloses (see figures 1-16) the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) has a third input (figures 7 and 10, part third input at 220 from VIS1-VSM) coupled to the current feedback terminal (figure 7, part current feedback terminal at CS1-CSM) and includes summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) having first (figure 11, part first input of 230_1-230_M from Verr), second (figure 10, part second input of 228_1-228_M from 226), and third inputs (figure 10, part third input of 228_1-228_M from 224_1-224_M) and an output (figures 10 and 11, part output of 230_1-230_M to 206_1-206_M), the first input (figure 11, part first input of 230_1-230_M from Verr) coupled to the first input of the processing circuitry (figures 7, 10 and 11, part first input at 230_1-230_M from Verr), the second input (figure 10, part second input of 228_1-228_M from 226) coupled to an output of the averaging circuitry (figure 10, part output of 226), and the output (figures 10 and 11, part output of 230_1-230_M to 206_1-206_M) coupled to the output of the processing circuitry (figures 7, 10 and 11, part output of 230_1-230_M to 206_1-206_M); and ripple tracking circuitry (figure 10, part ripple tracking circuitry generated by 222_1-222_M and 224_1-224_M) coupled between the third input of the summing circuitry (figure 10, part third input of 228_1-228_M from 224_1-224_M) and the third input of the processing circuitry (figures 7 and 10, part third input at 220 from VIS1-VSM) (paragraph [0096]; the current balance control operation is performed such that the peaks of the coil currents IL matches each other as described above, the sample-and-hold circuit 222_i may preferably perform the sampling operation at a timing of the peak of the current detection signal VISi).
Regarding claim 17, Takenaka discloses everything claimed as applied above (see claim 16). Further, Takenaka discloses (see figures 1-16) the ripple tracking circuitry (figure 10, part ripple tracking circuitry generated by 222_1-222_M and 224_1-224_M) is configurable to determine a ripple of a first signal at the current feedback terminal (figure 7, part VIS1-VISM at current feedback terminal at CS1-CSM) and output a second signal responsive to determining the ripple (figure 10, part I1B-IMB from ripple tracking circuitry generated by 222_1-222_M and 224_1-224_M) (paragraph [0096]; the current balance control operation is performed such that the peaks of the coil currents IL matches each other as described above, the sample-and-hold circuit 222_i may preferably perform the sampling operation at a timing of the peak of the current detection signal VISi).
Regarding claim 19, Takenaka discloses everything claimed as applied above (see claim 16). Further, Takenaka discloses (see figures 1-16) the summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) is configurable to receive a first signal (figure 11, part Verr) at the first input (figure 11, part first input of 230_1-230_M from Verr), a second signal (figure 10, part second signal at Iave) at the second input (figure 10, part second input of 228_1-228_M from 226), a third signal (figure 10, part third signal at I1B-IMB) at the third input (figure 10, part third input of 228_1-228_M from 224_1-224_M), and provide a fourth signal (figure 11, part fourth signal at Verr1-Verrm) responsive to subtracting the second signal (figure 10, part second signal at Iave) from the first signal (figure 11, part Verr) to generate a difference signal (figure 10, part difference of second signal at Iave and Verr), and subtracting the third signal (figure 10, part third signal at I1B-IMB) from the difference signal (figure 10, part difference of second signal at Iave and Verr) (paragraphs [0104-0106]; VERRi=VERR+ ΔVOFSi = VERR + R21×ΔIi; wherein ΔIi = Iave – IMA).
Regarding claim 21, Takenaka discloses everything claimed as applied above (see claim 1). Further, Takenaka discloses (see figures 1-16) the modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) is configurable to switch states of the first (figure 15, part first output of 200a connected to M4) and second outputs (figure 15, part second output of 200a connected to M3) responsive (figure 7, part 206) to a first signal at the first input (figure 7, part first signal at first input at lower terminal of 206) rising above (figure 7, part 206) a second signal at the second input (figure 7, part second signal at second input at upper terminal of 206).
Regarding claim 22, Takenaka discloses everything claimed as applied above (see claim 1). Further, Takenaka discloses (see figures 1-16) the modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) is configurable to switch states of the first (figure 15, part first output of 200a connected to M4) and second outputs (figure 15, part second output of 200a connected to M3) responsive to a first signal at the first input (figure 7, part first signal at first input at lower terminal of 206) falling below (figure 7, part 206) a second signal at the second input (figure 7, part second signal at second input at upper terminal of 206).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 14, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka (US 2017/0214318), in view of Rajagopalan (US 6,137,274).
Regarding claim 3, Takenaka discloses everything claimed as applied above (see claim 2). Further, Takenaka discloses (see figures 1-16) the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) includes the third input of the summing circuitry (figure 10, part third input of 228_1-228_M from 226) and the third input of the processing circuitry (figures 7 and 10, part third input at Iave). However, Takenaka does not expressly disclose a respective amplification circuitry.
Rajagopalan teaches (see figure 1) processing circuitry (figure 1, part processing circuitry generated by 11, 20, 21 and 31) includes an amplification circuitry (figure 1, part amplification circuitry generated by 21) coupled between the third input of the summing circuitry (figure 1, part input of 31) and the third input of the processing circuitry (figure 1, part third input at output of averaging circuitry generated by 20) (column 5; lines 36-62; current mirror circuitry 21 is configured so that the parameter k is variable in response to an external control signal (e.g., a signal applied to a pin labeled "Gain", indicated in phantom view, and supplied from the pin labeled "Gain" to circuitry 21). Thus, a desired value of parameter k is determined by an external control signal applied (from external circuitry) to a pin of controller chip 1, and from such pin to circuitry 21, and each current signal k(Iavg) is effectively amplified with a gain that is controlled by the external gain control signal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the amplification circuitry features as taught by Rajagopalan to the processing circuitry of Takenaka and obtain processing circuitry includes an amplification circuitry coupled between the third input of the summing circuitry and the third input of the processing circuitry, because it provides more efficient and accurate control in order to obtain more stable output (column 3; lines 1-4).
Regarding claim 4, Takenaka and Rajagopalan teach everything claimed as applied above (see claim 3). Further, Takenaka discloses (see figures 1-16) a current sense amplifier (figure 14, part current sense amplifier at 234) having an input and an output (figure 14, part current sense amplifier at 234; input and output), the input of the current sense amplifier (figure 14, part input of current sense amplifier at 234) coupled to the current feedback terminal (figures 7 and 14, part current feedback terminal at CS1-CSM; through VIS1-VISM), the output of the current sense amplifier (figure 14, part output of current sense amplifier at 234) coupled to the first input of the modulator (figure 7, part first input at lower terminal of 206), an input of the averaging circuitry (figure 10, part input of 226), and an input of the peak tracking circuitry (figure 10, part input of peak tracking circuitry generated by 222_1-222_M and 224_1-224_M).
Regarding claim 5, Takenaka and Rajagopalan teach everything claimed as applied above (see claim 4). Further, Takenaka discloses (see figures 1-16) the summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) is first summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M), the circuit further comprising: slope compensation circuitry having an output (figure 7, part slope compensation circuitry that generates Vslope); and second summing circuitry (figure 7, part 210) having a first input (figure 7, part 210; input from VIS1), a second input (figure 7, part 210; input at Vslope), and an output (figure 7, part 210; output), the first input of the second summing circuitry (figure 7, part 210; input from VIS1) coupled to the output of the current sense amplifier (figure 7, part at VIS1), the second input of the second summing circuitry (figure 7, part 210; input at Vslope) coupled to the output of the slope compensation circuitry (figure 7, part slope compensation circuitry that generates Vslope), and the output of the second summing circuitry (figure 7, part 210; output) coupled to the first input of the modulator (figure 7, part first input at lower terminal of 206).
Regarding claim 6, Takenaka and Rajagopalan teach everything claimed as applied above (see claim 5). Further, Takenaka discloses (see figures 1-16) the modulator (figures 7 and 15, part modulator 204_1-204_M inside of 200a) includes: a comparator (figure 7, part 206) having a first input (figure 7, part 206; lower input), a second input (figure 7, part 206; upper input), and an output (figure 7, part 206; output), the first input of the comparator (figure 7, part 206; lower input) forming the first input of the modulator (figure 7, part first input at lower terminal of 206), the second input of the comparator (figure 7, part 206; upper input) forming the second input of the modulator (figure 7, part second input at upper terminal of 206); and driver logic circuitry (figure 7, part driver logic circuitry generated by 208 and 212) having an input (figure 7, part driver logic circuitry generated by 208 and 212; input at 208), a first output (figure 15, part first output from 200a to M4), and a second output (figure 15, part second output from 200a to M3), the input of the driver logic circuitry (figure 7, part driver logic circuitry generated by 208 and 212; input at 208) coupled to the output of the comparator (figure 7, part 206; output), the first output of the driver logic circuitry (figure 15, part first output from 200a to M4) forming the first output of the modulator (figure 15, part first output of 200a connected to M4), the second output of the driver logic circuitry (figure 15, part second output from 200a to M3) forming the second output of the modulator (figure 15, part second output of 200a connected to M3) (paragraph [0118]; The step-down converter 410 or otherwise the step-up converter 420 corresponds to the DC/DC converter 100 described above in the embodiment. FIG. 15 shows the DC/DC converter having a single-channel configuration. Also, such a DC/DC converter may have a multi-channel/multi-phase configuration).
Regarding claim 14, Takenaka discloses everything claimed as applied above (see claim 13). Further, Takenaka discloses (see figures 1-16) each of the first (figure 7, part first processing circuitry generated by 220 and 250; between 202 and 204) and second processing circuitry (figure 7, part second processing circuitry generated by 220 and 250; between 202 and 204) includes an input of the respective summing circuitry (figure 10, part input at 228_1-228_M in the summing circuitry generated by 228_1-228_M and 230_1-230_M) and an output of the respective averaging circuitry (figures 7 and 10, part output of 226). However, Takenaka does not expressly disclose a respective amplification circuitry.
Rajagopalan teaches (see figure 1) each of the first (figure 1, part first processing circuitry generated by 11, 20, 21 and 31) and second processing circuitry (figure 1, part second processing circuitry generated by 12, 20, 21 and 32) includes a respective amplification circuitry (figure 1, part amplification circuitry generated by 21) coupled between an input of the respective summing circuitry (figure 1, part input of 31/32) and an output of the respective averaging circuitry (figure 1, part output of averaging circuitry generated by 20) (column 5; lines 36-62; current mirror circuitry 21 is configured so that the parameter k is variable in response to an external control signal (e.g., a signal applied to a pin labeled "Gain", indicated in phantom view, and supplied from the pin labeled "Gain" to circuitry 21). Thus, a desired value of parameter k is determined by an external control signal applied (from external circuitry) to a pin of controller chip 1, and from such pin to circuitry 21, and each current signal k(Iavg) is effectively amplified with a gain that is controlled by the external gain control signal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the amplification circuitry features as taught by Rajagopalan to the first and second processing circuitry of Takenaka and obtain each of the first and second processing circuitry includes a respective amplification circuitry coupled between an input of the respective summing circuitry and an output of the respective averaging circuitry, because it provides more efficient and accurate control in order to obtain more stable output (column 3; lines 1-4).
Regarding claim 18, Takenaka discloses everything claimed as applied above (see claim 16). Further, Takenaka discloses (see figures 1-16) the processing circuitry (figure 7, part processing circuitry generated by 220 and 250; between 202 and 204) includes its second input (figure 10, part second input of 228_1-228_M from 226) and the output of the averaging circuitry (figures 7 and 10, part output of 226). However, Takenaka does not expressly disclose a respective amplification circuitry.
Rajagopalan teaches (see figure 1) processing circuitry (figure 1, part processing circuitry generated by 11, 20, 21 and 31) includes an amplification circuitry (figure 1, part amplification circuitry generated by 21) coupled between its second input (figure 1, part input of 31) and the output of the averaging circuitry (figure 1, part output of averaging circuitry generated by 20) (column 5; lines 36-62; current mirror circuitry 21 is configured so that the parameter k is variable in response to an external control signal (e.g., a signal applied to a pin labeled "Gain", indicated in phantom view, and supplied from the pin labeled "Gain" to circuitry 21). Thus, a desired value of parameter k is determined by an external control signal applied (from external circuitry) to a pin of controller chip 1, and from such pin to circuitry 21, and each current signal k(Iavg) is effectively amplified with a gain that is controlled by the external gain control signal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the amplification circuitry features as taught by Rajagopalan to the processing circuitry of Takenaka and obtain processing circuitry includes an amplification circuitry coupled between its second input and the output of the averaging circuitry, because it provides more efficient and accurate control in order to obtain more stable output (column 3; lines 1-4).
Regarding claim 20, Takenaka and Rajagopalan teach everything claimed as applied above (see claim 18). Further, Takenaka discloses (see figures 1-16) summing circuitry (figure 10, part summing circuitry generated by 228_1-228_M and 230_1-230_M) includes current summing circuitry (figure 10, part current summing circuitry at 230_1-230_M; input ∆I1-IM from 228_1-228_M) and a current-to-voltage converter circuitry (figure 10, part current-to-voltage converter circuitry generated by R21-1 and C21/1; to output Verr1) (paragraphs [0104]-[0106]).
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838