DETAILED ACTION
This office action is in response to claims filed 27 October 2023.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-2, 10-11, and 19-20 are objected to because of the following informalities: “the first CPU” should read “the first CPU core” Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Regarding claim 1, in step 1 of the 101 analysis set forth in MPEP 2106, the claim recites an apparatus that determines scheduling slots to assign tasks based on task type. An apparatus is one of the four statutory categories of invention.
In step 2A, prong 1 of the 101 analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
i. “determine a first slot of a slot pattern in which a task of a first type is scheduled to be performed” (a person can mentally determine a slot by simply evaluating slot patterns and tasks, and making a judgement of a particular slot (MPEP 2106.04(a)))
ii. “assign at least one task of the first type to be performed by at least one first CPU core allocated to perform tasks of the first type” (a person can mentally assign tasks to be performed by CPUs by simply evaluating CPUs and making a judgment of a particular one to assign a task to (MPEP 2106.04(a))).
iii. “determine a second slot of the slot pattern in which a task of the first type is not scheduled to be performed” (a person can mentally determine a second slot by simply evaluating slot patterns and making a judgment of a second slot (MPEP 2106.04(a)))
iv. “transition the at least one first CPU from an active state to an idle state after at least the second slot of the slot pattern” (a person can mentally transition CPU states by simply evaluating conditions and making a determination that a state of the CPU should change to an idle state (MPEP 2106.04(a)))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
In step 2A, prong 2 of the 101 analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
v. “An apparatus for idle state central processing unit (CPU) core transitioning, the apparatus comprising: at least one memory storing instructions; and at least one processor configured to execute the instructions” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In step 2B of the 101 analysis set forth in the 2019 PEG, the examiner has determined through reanalysis of the following limitations considered in step 2A prong 2, that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
v. “An apparatus for idle state central processing unit (CPU) core transitioning, the apparatus comprising: at least one memory storing instructions; and at least one processor configured to execute the instructions” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
Regarding claim 2, the additional element “the second slot of the slot pattern occurs after the assigned at least one task of the first type is scheduled to be completed by the at least one first CPU” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 3, the additional element “the slot pattern is a time-division duplex (TDD) pattern” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 4, the additional element “determine a third slot of the slot pattern in which a task of a second type is scheduled to be performed” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally determine a third slot by simply evaluating slot patterns and making a judgment of a third slot (MPEP 2106.04(a))). Further, the additional element “assign at least one task of the second type to be performed by at least one second CPU core during the third slot of the slot pattern” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally assign tasks to be performed by CPUs by simply evaluating CPUs and making a judgment of a particular one to assign a task to (MPEP 2106.04(a))).
Regarding claim 5, the additional element “transition the at least one first CPU from the active state to the idle state while the at least one task of the second type is being performed by the at least one second CPU core” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally transition CPU states by simply evaluating conditions and making a determination that a state of the CPU should change to an idle state (MPEP 2106.04(a))).
Regarding claim 6, the additional element “the task of the first type comprises an uplink task, and wherein the task of the second type comprises either a downlink task or a sounding reference signal (SRS) task” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 7, the additional element “the task of the first type comprises a downlink task, and wherein the task of the second type comprises either an uplink task or a sounding reference signal (SRS) task” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 8, the additional element “the task of the first type comprises a sounding reference signal (SRS) task, and wherein the task of the second type comprises either an uplink task or a downlink task” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 9, the additional element “the idle state corresponds to a C-6 long sleep idle state of the at least one first CPU core” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claims 10-18, and 19-20, they comprise limitations similar to claims 1-9, and are therefore rejected for similar rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 2 4 5 10 11 13 14 19 20 are rejected under 35 U.S.C. 103 as being unpatentable over SCHWERK Pub. No.: US 2006/0184944 A1 (hereafter SCHWERK), in view of VANKA et al. Pub. No.: US 2017/0038813 A1 (hereafter VANKA).
Regarding claim 1, SCHWERK teaches the invention substantially as claimed, including:
An apparatus for idle state central processing unit (CPU) core transitioning, the apparatus comprising:
at least one memory storing instructions; and at least one processor configured to execute the instructions ([0014] Computer systems are also described that may include a processor and a memory coupled to the processor. The memory may encode one or more programs that cause the processor to perform one or more of the method acts described herein) to:
determine a first slot of a slot pattern in which a task of a first type is scheduled to be performed ([0024] FIG. 1 illustrates a method 100 that may include, at step 110, receiving a plurality of requests for batch jobs. Each such batch job may correspond to one of a plurality of batch job categories (i.e., “types”). The batch job categories in turn may each have one or more associated time slots. The request may indicate in which of one or more of the associated time slots processing is desired. [0026] The time slots may be recurring or they may be triggered based on processing consumption. For example, a time slot may be 1:15 am to 1:23 am every day (i.e., recurring time slots represent a “pattern” of slots));
assign at least one task of the first type to be performed by at least one first CPU core allocated to perform tasks of the first type ([0031] A processor 320 may process each batch job during the one or more of the selected time slots. Optionally, a scheduler (not shown) may be interposed between the receiver 310 and the processor 320 which schedules the processing to be conducted by the processor 320 (i.e., scheduler schedules, or “assigns” each batch job to conducted by an allocated processor));
determine a second slot of the slot pattern in which a task of the first type is not scheduled to be performed ([0025] The administrator may schedule these special batch jobs at different times (e.g., time slots associated with the batch job category). For example, batch jobs that require lengthy processing might be associated with one batch job category so that they may be processed during off-hours. Batch jobs that require short processing might be placed into another batch job category so that they may be processed during short intervals during peak usage hours (i.e., first type jobs having longer processing times are scheduled to be performed in a first slot during off hours and second type jobs having shorter processing times are scheduled in a second slot during peak hours)); and
While SCHWERK discusses scheduling of tasks into time slots based on task type, SCHWERK does not explicitly teach:
transition the at least one first CPU from an active state to an idle state after at least the second slot of the slot pattern
However, in analogous art that similarly teaches scheduling of tasks, VANKA teaches:
transition the at least one first CPU from an active state to an idle state after at least the second slot of the slot pattern ([0046] As would also be understood by one of skill in the art, the different tasks executed by each thread may require different activity levels for one or more cache associated with the cores 120, 122, 124, 126 executing the threads. Using the 0th Core as an example again, as illustrated in FIG. 2, the two tasks executed during Frame 1 require little activity by the cache associated with the 0th Core. [0048] As also illustrated in FIG. 2, after the completion of Frame 1/Period 1, none of cores 120, 122, 124, 126 have any threads or tasks to execute in Frame 2/Period 2. As a result cores 120, 122, 124, 126 will enter an idle state for at least Frame 2/Period 2. In other examples, one or more of cores 120, 122, 124, 126 may remain active during Frame 2/Period 2 while the remaining cores 120, 122, 124, 126 enter the idle state (i.e., 0th core, representing a “first CPU” is transitioned from active to inactive state after a first slot in frame 1 executes an ipEvent task, and a second slot in frame 1 executes a task (xTh2) that is a different type from the ipEvent task))
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined VANKA’s teaching of transitioning a CPU to idle after first and second time slots, with SCHWERK’s teaching of executing tasks of different types in different time slots, to realize, with a reasonable expectation of success, a system that executes tasks in different timeslots, as in SCHWERK, which then places the processors in idle state following completion of the time slots, as in VANKA. A person having ordinary skill would have been motivated to make this combination to conserve power (VANKA [0002]-[0004]).
Regarding claim 2, SCHWERK further teaches:
the second slot of the slot pattern occurs after the assigned at least one task of the first type is scheduled to be completed by the at least one first CPU (0025] The administrator may schedule these special batch jobs at different times (e.g., time slots associated with the batch job category). For example, batch jobs that require lengthy processing might be associated with one batch job category so that they may be processed during off-hours. Batch jobs that require short processing might be placed into another batch job category so that they may be processed during short intervals during peak usage hours (i.e., one time slot completes before a second time slot occurs, depending on when the peak usage hours and the off hours occur)).
Regarding claim 4, SCHWERK further teaches:
determine a third slot of the slot pattern in which a task of a second type is scheduled to be performed; and assign at least one task of the second type to be performed by at least one second CPU core during the third slot of the slot pattern ([0025] The batch job categories define certain types of batch jobs. The categories may be defined by a system administrator based on any criteria that may be used to differentiate batch job types. In some variations of the subject, the administrator may define special batch jobs that represent the batch job categories (e.g., one batch job per category). In addition, the administrator may schedule these special batch jobs at different times (e.g., time slots associated with the batch job category) (i.e., each of any number of time slots including a first, second, or third time slot is configured for a given category of task respectively)).
Regarding claim 5, VANKA further teaches:
transition the at least one first CPU from the active state to the idle state while the at least one task of the second type is being performed by the at least one second CPU core (([0046] As would also be understood by one of skill in the art, the different tasks executed by each thread may require different activity levels for one or more cache associated with the cores 120, 122, 124, 126 executing the threads. Using the 0th Core as an example again, as illustrated in FIG. 2, the two tasks executed during Frame 1 require little activity by the cache associated with the 0th Core. [0048] As also illustrated in FIG. 2, after the completion of Frame 1/Period 1, none of cores 120, 122, 124, 126 have any threads or tasks to execute in Frame 2/Period 2. As a result cores 120, 122, 124, 126 will enter an idle state for at least Frame 2/Period 2. In other examples, one or more of cores 120, 122, 124, 126 may remain active during Frame 2/Period 2 while the remaining cores 120, 122, 124, 126 enter the idle state (i.e., a first core enters an idle state while a second core performs a task)).
Regarding claims 10-11, 13-14, and 19-20, they comprise limitations similar to claims 1-2, and 4-5, and are therefore rejected for similar rationale.
Claims 3, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over SCHWERK, in view of VANKA, as applied to claims 1, and 10, and in further view of PRATNER et al. Pub. No.: US 2020/0326980 A1 (hereafter PRATNER).
Regarding claim 3, while SCHWERK and VANKA discuss scheduling of tasks, they do not explicitly teach:
the slot pattern is a time-division duplex (TDD) pattern.
However, in analogous art that similarly teaches scheduling of tasks, PRANTNER teaches:
the slot pattern is a time-division duplex (TDD) pattern ([0139] For example FIG. 4 shows an exemplary embodiment of such a given instance of a system configuration with the produced scheduling algorithm…The given system includes five virtual machines, namely VM A, VM B, VMC, VM D and VM E. In other embodiments, the system may also include less or more virtual machines. In the given embodiment each virtual machine has the same processor share or time slice, here for example 20%. All virtual machines include periodic tasks having 2 ms and 5 ms task periods. In other words, each virtual machine must be scheduled every 2 ms and additionally at multiples of 5 ms. The first 4 ms of the cycle period in FIG. 4 shows a standard uniform round robin time division multiplexing scheduling as each virtual machine must be scheduled two times within that period, one after the other in a fixed sequence. After the 4 ms, the virtual machines VM A, VM B, VMC, VM D and VM E are scheduled, such that the 2 ms and 5 ms task periods are met by each virtual machine (i.e., periodic virtual machine tasks are scheduled to time slits based on a time division multiplexing scheduling algorithm)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined PRANTER’s teaching of scheduling tasks based on a time division multiplexing algorithm, with SCHWERK and VANKA’s teaching of scheduling tasks to time slots, to realize, with a reasonable expectation of success, a system that schedules tasks to time slots, as in SCHWERK and VANKA, based on time division multiplexing scheduling algorithms, as in PRANTER. A person of ordinary skill would have been motivated to make this combination to optimize scheduling to reduce jitter which ensuring that the system still meets real time requirements (PRANTER [0139]).
Regarding claim 12, it comprises limitations similar to claim 3, and is therefore rejected for similar rationale.
Claims 6-7, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over SCHWERK, in view of VANKA, as applied to claims 4, and 13, and in further view of BHATT et al. Pub. No.: US 2018/0352557 A1 (hereafter BHATT).
Regarding claim 6, while SCHWERK and VANKA discuss scheduling of tasks, they do not explicitly teach:
the task of the first type comprises an uplink task, and wherein the task of the second type comprises either a downlink task or a sounding reference signal (SRS) task.
However, in analogous art that similarly discusses scheduling of tasks, BHATT teaches:
the task of the first type comprises an uplink task, and wherein the task of the second type comprises either a downlink task or a sounding reference signal (SRS) task ([0057] FIG. 5D shows an exemplary embodiment of the baseband processing subsystem 130 that illustrates how two simultaneous processing pipelines are implemented. For example, in a first processing pipeline 536, which in an exemplary embodiment can be an uplink process, the PSM 210 schedules jobs for the FFE1, FFE2, PFE3, and FFE4 resources. In a second processing pipeline 552, which in an exemplary embodiment can be a downlink process, the PSM 210 schedules jobs for the PFE4, FFE3, PFE2, and PFE1 resources. For example, the PSM 210 outputs scheduled jobs to the resources through the bus 314 to perform the two processing pipelines 550 and 552 (i.e., tasks to be scheduled on functional element resources include uplink and downlink tasks)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined BHATT’s teaching of scheduling tasks in pipelines including uplink and downlink tasks on resources, with the combination of SCHWERK and VANKA’s teaching of scheduling tasks in time slots on resources, to realize, with a reasonable expectation of success, a system that schedules execution of tasks in time slots of resources, as in SCHWERK and VANKA, which includes uplink and downlink tasks, as in BHATT. A person having ordinary skill would have been motivated to make this combination to provide a unified baseband architecture that allows for a wider range of baseband functions to be performed (BHATT [0005]).
Regarding claim 7, while SCHWERK and VANKA discuss scheduling of tasks, they do not explicitly teach:
the task of the first type comprises a downlink task, and wherein the task of the second type comprises either an uplink task or a sounding reference signal (SRS) task.
However, in analogous art that similarly discusses scheduling of tasks, BHATT teaches:
the task of the first type comprises a downlink task, and wherein the task of the second type comprises either an uplink task or a sounding reference signal (SRS) task ([0057] FIG. 5D shows an exemplary embodiment of the baseband processing subsystem 130 that illustrates how two simultaneous processing pipelines are implemented. For example, in a first processing pipeline 536, which in an exemplary embodiment can be an uplink process, the PSM 210 schedules jobs for the FFE1, FFE2, PFE3, and FFE4 resources. In a second processing pipeline 552, which in an exemplary embodiment can be a downlink process, the PSM 210 schedules jobs for the PFE4, FFE3, PFE2, and PFE1 resources. For example, the PSM 210 outputs scheduled jobs to the resources through the bus 314 to perform the two processing pipelines 550 and 552 (i.e., tasks to be scheduled on functional element resources include uplink and downlink tasks)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined BHATT’s teaching of scheduling tasks in pipelines including uplink and downlink tasks on resources, with the combination of SCHWERK and VANKA’s teaching of scheduling tasks in time slots on resources, to realize, with a reasonable expectation of success, a system that schedules execution of tasks in time slots of resources, as in SCHWERK and VANKA, which includes uplink and downlink tasks, as in BHATT. A person having ordinary skill would have been motivated to make this combination to provide a unified baseband architecture that allows for a wider range of baseband functions to be performed (BHATT [0005]).
Regarding claims 15-16, they comprise limitations similar to claims 6-7, and are therefore rejected for similar rationale.
Claims 8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over SCHWERK, in view of VANKA, as applied to claims 4, and 13, and in further view of GHANBARINEJAD et al. Pub. No.: US 2023/0155800 A1 (hereafter GHANBARINEJAD).
Regarding claim 8, while SCHWERK and VANKA discuss execution of scheduled tasks, they do not explicitly teach:
the task of the first type comprises a sounding reference signal (SRS) task, and wherein the task of the second type comprises either an uplink task or a downlink task.
However, in analogous art that similarly discusses execution of scheduled tasks, GHANBARINEJAD discloses
the task of the first type comprises a sounding reference signal (SRS) task, and wherein the task of the second type comprises either an uplink task or a downlink task (downlink communications from N to CN and/or UE may follow a beam acquisition process including CSI-RS transmissions by N and {CRI, RSRP} reporting by CN and/or UE. Furthermore, uplink communications transmitted from CN and/or UE to N may follow a separate beam acquisition process including SRS transmissions by CN and/or UE and measurements by N (i.e., at least uplink communication tasks follow beam acquisition processes that include sounding reference signal transmission tasks)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined GHANBARINEJAD’s teaching of scheduling an uplink tasks to be performed following a sounding reference signal task, with SCHWERK and VANKA’s teaching of scheduling tasks in slots for execution, to realize, with a reasonable expectation of success, a system that schedules tasks in slots for execution, as in SCHWERK and VANKA, including first a sounding reference signal task before an uplink task, as in GHANBARINEJAD. A person having ordinary skill would have been motivated to make this combination to facilitate beam acquisition in simultaneous communication (GHANBARINEJAD [0098]).
Regarding claim 17, it comprises limitation similar to claim 8, and is therefore rejected for similar rationale.
Claims 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over SCHWERK, in view of VANKA, as applied to claims 1, and 10, and in further view of ROTEM et al. Pub. No.: US 2021/0064804 A1 (hereafter ROTEM).
Regarding claim 9, while SCHWERK and VANKA discuss placing CPU cores in idle states, they do not explicitly teach:
the idle state corresponds to a C-6 long sleep idle state of the at least one first CPU core.
However, in analogous art that similarly discusses placing CPU cores in idle states, ROTEM teaches:
the idle state corresponds to a C-6 long sleep idle state of the at least one first CPU core ([0036] With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined ROTEM’s teaching of placing a CPU to be idled in a C6 state, with the combination of SCHWERK and VANKA’s teaching of placing CPUs in idle modes, to realize, with a reasonable expectation of success, a system that places a CPU in an idle state, as in SCHWERK and VANKA, which is a low power C6 state, as in ROTEM. A person having ordinary skill would have been motivated to make this combination to conserve power and optimize power consumption.
Regarding claim 18, it comprises limitations similar to claim 9, and are therefore rejected for similar rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LUCH et al. Pub. No.: US 2023/0004923 A1 discusses scheduling workers of different worker types to time-slots, followed by assigning scheduled workers to workstations or work tasks associated with the assigned time-slots.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL W AYERS whose telephone number is (571)272-6420. The examiner can normally be reached M-F 8:30-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL W AYERS/Primary Examiner, Art Unit 2195
Prosecution Insights