Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an
abstract idea without significantly more.
Step 1:
Claim 1 is directed to An apparatus for resource allocation of a central processing unit (CPU) comprising a plurality of cores, the apparatus comprising: at least one memory storing instructions; and at least one processor configured to execute the instructions to: a series of steps, and is therefore directed to a process, which is one of the four statutory categories.
Step 2A, Prong One:
Claim 1 recites the limitations:
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type;
allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type;
assign at least one task of the first type to be performed by the first core;
and transition the first core to an idle state based on the at least one task of the first type being completed;
all of which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Accordingly, claim 1 recites a judicial exception (i.e., an abstract idea).
Step 2A, Prong Two:
The additional elements recited in claim 1 include:
By the first core
Regarding the additional element (i), the limitation recited is mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(f).
Step 2B:
Regarding the additional element (i), the limitation is reciting generic computing components performing the steps which can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f).
The combination of these additional elements amounts to a method comprising steps which can be performed mentally implemented by generic computing components, and comprising a step of insignificant extra-solution and well-understood, routine and conventional activity.
Therefore, the additional elements, when considered individually and in combination, fail to add an inventive concept to the claim.
Consequently, claim 1 as a whole does not amount to significantly more than the recited judicial exceptions and the claim is not eligible.
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 2 recites assign[ing] at least one task of the second type to be performed by the second core, which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 2 recites the additional element by the second core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f).
Accordingly, for the same reasons presented with respect to claim 1, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 2 is not eligible.
Claim 8 is dependent of claim 7, and therefore inherits the same judicial exceptions recited in claims 1 and 7. Further, claim 8 recites transition[ing] the first core to an idle state when both the first task of the first type is completed by the first HT of the first core and the second task of the first type is completed by the second HT of the first core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 3 is dependent on claim 2, and therefore inherits the same judicial exceptions recited in claims 1 and 2. Further, claim 3 recites transition[ing] the first core to an idle state based on the at least one task of the first type being completed and while the at least one task of the second type is being performed by the second core. Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 3 does not recite any additional elements beyond those recited in claims 1 and 2. Accordingly, for the same reasons presented with respect to claims 1 and 2, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 3 is not eligible.
Claim 4 is dependent on claim 2, and therefore inherits the same judicial exceptions recited in claims 1 and 2. Further, claim 4 recites that the tasks of the first type comprise uplink tasks, and wherein the tasks of the second type comprise either downlink tasks or sounding reference signal (SRS) tasks. Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 4 does not recite any additional elements beyond those recited in claims 1 and 2. Accordingly, for the same reasons presented with respect to claims 1 and 2, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 4 is not eligible.
Claim 5 is dependent on claim 2, and therefore inherits the same judicial exceptions recited in claims 1 and 2. Further, claim 5 recites that the tasks of the first type comprise downlink tasks, and wherein the tasks of the second type comprise either uplink tasks or sounding reference signal (SRS) tasks; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 5 does not recite any additional elements beyond those recited in claims 1 and 2. Accordingly, for the same reasons presented with respect to claims 1 and 2, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 5 is not eligible.
Claim 6 is dependent on claim 2, and therefore inherits the same judicial exceptions recited in claims 1 and 2. Further, claim 6 recites that the tasks of the first type comprise sounding reference signal (SRS) tasks, and wherein the tasks of the second type comprise either uplink tasks or downlink tasks; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 6 does not recite any additional elements beyond those recited in claims 1 and 2. Accordingly, for the same reasons presented with respect to claims 1 and 2, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 6 is not eligible.
Claim 7 is dependent on claim 1, and therefore inherits the same judicial exceptions recited in claim 1. Further, claim 7 recites assign[ing] the at least one task of the first type to be performed by the first core by: assigning a first task of the first type to be performed by a first hyperthread (HT) of the first core; and assigning a second task of the first type to be performed by a second HT of the first core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 7 recites the additional element by a first hyperthread (HT) of the first core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 7 also recites the additional element by a second HT of the first core; which is mere instructions to apply the exception for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 1 and 7, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 7 is not eligible.
Claim 8 is dependent of claim 7, and therefore inherits the same judicial exceptions recited in claims 1 and 7. Further, claim 8 recites transition[ing] the first core to an idle state when both the first task of the first type is completed by the first HT of the first core and the second task of the first type is completed by the second HT of the first core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 8 does not recite any additional elements beyond those recited in claims 1 and 7. Accordingly, for the same reasons presented with respect to claims 1 and 7, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 8 is not eligible.
Claim 9 is dependent of claim 7, and therefore inherits the same judicial exceptions recited in claims 1 and 7. Further, claim 9 recites assign[ing] a first task of the second type to be performed by a first HT of the second core; and assign a second task of the second type to be performed by a second HT of the second core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 9 recites the additional element by a first hyperthread (HT) of the second core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 9 also recites the additional element by a second HT of the second core; which is mere instructions to apply the exception for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 1 and 7, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 9 is not eligible.
Claim 10 is dependent of claim 9, and therefore inherits the same judicial exceptions recited in claims 1, 7, and 9. Further, claim 10 recites allocate[ing] a third core of the plurality of cores of the CPU to perform tasks of a third type that is different from both the first type and the second type; assign a first task of the third type to be performed by a first HT of the third core; and assign a second task of the third type to be performed by a second HT of the third core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 10 recites the additional element by a first hyperthread (HT) of the third core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 10 also recites the additional element by a second HT of the third core; which is mere instructions to apply the exception for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 1, 7, and 9, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 10 is not eligible.
Claim 11 is dependent of claim 10, and therefore inherits the same judicial exceptions recited in claims 1, 7, 9, and 10. Further, claim 11 recites that the tasks of the first type comprise uplink tasks, the tasks of the second type comprise downlink tasks, and the tasks of the third type comprise sounding reference signal (SRS) tasks; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 11 recites the additional element by a first hyperthread (HT) of the third core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 11 also recites the additional element by a second HT of the third core; which is mere instructions to apply the exception for the same reasons as the first additional element. Claim 11 also recites an additional element third core, which is also mere instructions to apply the exceptions for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 1, 7, 9, and 10, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 11 is not eligible.
Step 1:
Claim 12 is directed to A method for resource allocation of a central processing unit (CPU) comprising a plurality of cores, the method comprising: a series of steps, and is therefore directed to a process, which is one of the four statutory categories.
Step 2A, Prong One:
Claim 12 recites the limitations:
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type;
allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type;
assign at least one task of the first type to be performed by the first core;
and transition the first core to an idle state based on the at least one task of the first type being completed;
all of which can be performed in the human mind through observation, evaluation, judgement and
opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Accordingly, claim 12 recites a judicial exception (i.e., an abstract idea).
Step 2A, Prong Two:
There are no additional elements in claim 12.
Step 2B:
Therefore, the elements, when considered individually and in combination, fail to add
an inventive concept to the claim.
Consequently, claim 12 as a whole does not amount to significantly more than the recited judicial exceptions and the claim is not eligible.
Claim 13 is dependent on claim 12, and therefore inherits the same judicial exception recited in claim 12. Further, claim 13 recites assign[ing] at least one task of the second type to be performed by the second core, which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 13 recites the additional element by the second core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f).
Accordingly, for the same reasons presented with respect to claim 12, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 13 is not eligible.
Claim 14 is dependent on claim 13, and therefore inherits the same judicial exceptions recited in claims 12 and 13. Further, claim 14 recites transition[ing] the first core to an idle state based on the at least one task of the first type being completed and while the at least one task of the second type is being performed by the second core. Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 14 does not recite any additional elements beyond those recited in claims 12 and 13. Accordingly, for the same reasons presented with respect to claims 12 and 13, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 14 is not eligible.
Claim 15 is dependent on claim 13, and therefore inherits the same judicial exceptions recited in claims 12 and 13. Further, claim 15 recites that the tasks of the first type comprise uplink tasks, and wherein the tasks of the second type comprise either downlink tasks or sounding reference signal (SRS) tasks. Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 15 does not recite any additional elements beyond those recited in claims 12 and 13. Accordingly, for the same reasons presented with respect to claims 12 and 13, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 15 is not eligible.
Claim 16 is dependent on claim 12, and therefore inherits the same judicial exceptions recited in claim 12. Further, claim 16 recites assign[ing] the at least one task of the first type to be performed by the first core by: assigning a first task of the first type to be performed by a first hyperthread (HT) of the first core; and assigning a second task of the first type to be performed by a second HT of the first core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 16 recites the additional element by a first hyperthread (HT) of the first core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 16 also recites the additional element by a second HT of the first core; which is mere instructions to apply the exception for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 12 and 16, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 16 is not eligible.
Claim 17 is dependent of claim 16, and therefore inherits the same judicial exceptions recited in claims 12 and 16. Further, claim 17 recites transition[ing] the first core to an idle state when both the first task of the first type is completed by the first HT of the first core and the second task of the first type is completed by the second HT of the first core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 17 does not recite any additional elements beyond those recited in claims 12 and 16. Accordingly, for the same reasons presented with respect to claims 12 and 16, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 17 is not eligible.
Claim 18 is dependent of claim 16, and therefore inherits the same judicial exceptions recited in claims 12 and 16. Further, claim 18 recites assign[ing] a first task of the second type to be performed by a first HT of the second core; and assign a second task of the second type to be performed by a second HT of the second core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 18 recites the additional element by a first hyperthread (HT) of the second core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 18 also recites the additional element by a second HT of the second core; which is mere instructions to apply the exception for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 12 and 16, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 18 is not eligible.
Claim 19 is dependent of claim 18, and therefore inherits the same judicial exceptions recited in claims 12, 16, and 18. Further, claim 19 recites allocate[ing] a third core of the plurality of cores of the CPU to perform tasks of a third type that is different from both the first type and the second type; assign a first task of the third type to be performed by a first HT of the third core; and assign a second task of the third type to be performed by a second HT of the third core; Which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 19 recites the additional element by a first hyperthread (HT) of the third core, which is reciting generic computing components performing the steps that can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(f). Claim 19 also recites the additional element by a second HT of the third core; which is also mere instructions to apply the exception for the same reasons as the first additional element. Claim 19 also recites an additional element third core, which is also mere instructions to apply the exceptions for the same reasons as the first additional element.
Accordingly, for the same reasons presented with respect to claims 12, 16, and 18, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus, claim 19 is not eligible.
Claim 20 is directed to A non-transitory computer-readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to: a series of steps, and is therefore directed to a process, which is one of the four statutory categories.
Step 2A, Prong One:
Claim 20 recites the limitations:
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type;
allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type;
assign at least one task of the first type to be performed by the first core;
and transition the first core to an idle state based on the at least one task of the first type being completed;
all of which can be performed in the human mind through observation, evaluation, judgement and
opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Accordingly, claim 20 recites a judicial exception (i.e., an abstract idea).
Step 2A, Prong Two:
There are no additional elements in claim 20.
Step 2B:
Therefore, the elements, when considered individually and in combination, fail to add
an inventive concept to the claim.
Consequently, claim 20 as a whole does not amount to significantly more than the recited judicial exceptions and the claim is not eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Axmon (WO 2020064698 A1), henceforth Axmon, in view of Masuda (DE 102017211564 A1), henceforth Masuda, and further in view of Udava (US 20180032376 A1), henceforth Udava.
Regarding Claim 1, Axmon teaches:
An apparatus for resource allocation of a central processing unit (CPU) comprising a plurality of cores, the apparatus comprising: at least one memory storing instructions; and at least one processor configured to execute the instructions to: (see e.g., page [001], lines [0005-0007], “The present disclosure relates to measurement gaps in a wireless communication system and, more specifically, to adapting operations in slots that are partially overlapped by measurement gaps”)
Axmon fails to explicitly teach:
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type; allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type;
assign at least one task of the first type to be performed by the first core;
and transition the first core to an idle state based on the at least one task of the first type being completed.
However, Masuda teaches
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type; allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assign at least one task of the first type to be performed by the first core; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
Axmon and Masuda are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of managing gaps in operations of systems. Thus, it would have been prima facie obvious to one of ordinary skill in the art, before the effective filing date, to have modified the teachings of Axmon in order to incorporate the teachings of Masuda. Doing so would allow for multiple processing cores to access a variable without being denied access or disabled continuously. (see e.g., Masuda: p. [0005], “The present invention addresses the problem described above and has the object to provide an electronic control unit that allows all multiple cores to access a variable without being denied access or disabled continuously.”).
Axmon, in view of Masuda, fails to explicitly teach transition[ing] a first core to an idle state based on the at least one task of the first type being completed.
However, Udava teaches transition[ing] a first core to an idle state based on the at least one task of the first type being completed. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”)
Axmon, in view of Masuda and Udava are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of utilizing a multi-core system to schedule various tasks. Thus, it would have been prima facie obvious to one of ordinary skill in the art, before the effective filing date, to have modified the teachings of Axmon and Masuda in order to incorporate the teachings of Udava. Doing so would enable a better apparatus for scheduling and performing inter-dependent tasks (see e.g., Udava: [0009], “Another aspect of at least some example embodiments of the inventive concepts is to provide an apparatus and a method for scheduling, by a dynamic scheduling unit, at least one inter-dependent task from the at least one task group on a core of the multi-core processor system.”)
Regarding claim 2, Axmon, in view of Masuda, and further in view of Udava disclose:
The apparatus of claim 1, wherein the at least one processor is further configured to execute the instructions to: assign at least one task of the second type to be performed by the second core (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
Regarding claim 3, Axmon, in view of Masuda, and further in view of Udava disclose:
The apparatus of claim 2, wherein the at least one processor is configured to execute the instructions to transition the first core to an idle state based on the at least one task of the first type being completed and while the at least one task of the second type is being performed by the second core. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”)
Regarding claim 4, Axmon, in view of Masuda, and further in view of Udava disclose:
The apparatus of claim 2, wherein the tasks of the first type comprise uplink tasks, and wherein the tasks of the second type comprise either downlink tasks or sounding reference signal (SRS) tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”)
Regarding claim 5, Axmon, in view of Masuda, and further in view of Udava disclose:
The apparatus of claim 2, wherein the tasks of the first type comprise downlink tasks, and wherein the tasks of the second type comprise either uplink tasks or sounding reference signal (SRS) tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”)
Regarding claim 6, Axmon, in view of Masuda, and further in view of Udava disclose:
The apparatus of claim 2, wherein the tasks of the first type comprise sounding reference signal (SRS) tasks, and wherein the tasks of the second type comprise either uplink tasks or downlink tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”) (see e.g., page [007], lines [006-007], “In some embodiments, the scheduled operational task is an operational task associated with Sounding Reference Signal (SRS) transmission.”)
Regarding Claim 12, Axmon, in view of Masuda, and further in view of Udava disclose
A method for resource allocation of a central processing unit (CPU) comprising a plurality of cores, the method comprising: (see e.g., page [001], lines [0005-0007], “The present disclosure relates to measurement gaps in a wireless communication system and, more specifically, to adapting operations in slots that are partially overlapped by measurement gaps”)
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type; allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assign at least one task of the first type to be performed by the first core; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
and transitioning a first core to an idle state based on the at least one task of the first type being completed. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”)
Regarding claim 13, Axmon, in view of Masuda, and further in view of Udava disclose:
The method of claim 12, further comprising assigning at least one task of the second type to be performed by the second core (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
Regarding claim 14, Axmon, in view of Masuda, and further in view of Udava disclose:
The method of claim 13, wherein transitioning the first core to an idle state is performed based on the at least one task of the first type being completed and while the at least one task of the second type is being performed by the second core. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”)
Regarding claim 15, Axmon, in view of Masuda, and further in view of Udava disclose:
The method of claim 13, wherein the tasks of the first type comprise uplink tasks, and wherein the tasks of the second type comprise either downlink tasks or sounding reference signal (SRS) tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”)
Regarding claim 20, Axmon, in view of Masuda, and further in view of Udava disclose:
A non-transitory computer-readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to: (see e.g., page [001], lines [0005-0007], “The present disclosure relates to measurement gaps in a wireless communication system and, more specifically, to adapting operations in slots that are partially overlapped by measurement gaps”)
allocate a first core of the plurality of cores of the CPU to perform tasks of a first type; allocate a second core of the plurality of cores of the CPU to perform tasks of a second type that is different from the first type; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assign at least one task of the first type to be performed by the first core; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
and transition a first core to an idle state based on the at least one task of the first type being completed. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”)
Claims 7-11 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Axmon in view of Masuda, and further in view of Udava as applied to claims 4-6 and 15 above, and further in view of Liao (US 8612949 B2), henceforth Liao.
Regarding Claim 7, Axmon, in view of Masuda, and further in view of Udava teaches:
The apparatus of claim 1, wherein the at least one processor is configured to execute the instructions to assign the at least one task of the first type to be performed by the first core by: (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
Axmon, in view of Masuda, and further in view of Udava fails to explicitly teach:
assigning a first task of the first type to be performed by a first hyperthread (HT) of the first core; and assigning a second task of the first type to be performed by a second HT of the first core.
However, Liao teaches:
assigning a first task of the first type to be performed by a first hyperthread (HT) of the first core; and assigning a second task of the first type to be performed by a second HT of the first core. (see e.g., column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) This software has already automated the process of creating threads that can be used by hyperthreads.
Axmon, in view of Masuda, and further in view of Udava and Liao are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of utilizing a multi-core system to perform various tasks. Thus, it would have been prima facie obvious to one of ordinary skill in the art, before the effective filing date, to have modified the teachings of Axmon, in view of Masuda, and further in view of Udava, in order to incorporate the teachings of Liao. Doing so would enable the multiple core system to achieve timely and effective data prefetching, in addition to improving the effective throughput of the system by allowing for the various cores to still be more utilized even when waiting for I/O than they would be without (see e.g., Liao column [01], lines [0049-0056]). It would also more explicitly define the type of hardware necessary to perform some of the features disclosed.
Regarding claim 8, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The apparatus of claim 7, wherein the at least one processor is configured to transition the first core to an idle state when both the first task of the first type is completed by the first HT of the first core and the second task of the first type is completed by the second HT of the first core. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”) This is the same claim as before, as a core with hyperthreading capabilities would still be considered to be “executing tasks” until all their hyperthreads are no longer executing tasks.
Regarding claim 9, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The apparatus of claim 7, wherein the at least one processor is further configured to execute the instructions to: assign a first task of the second type to be performed by a first hyperthread (HT) of the second core; and assigning a second task of the second type to be performed by a second HT of the second core. (see e.g., column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) The threads are automatically generated custom for each bit of software, so the difference in the purpose of the task is not enough to disqualify it.
Regarding claim 10, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The apparatus of claim 9, wherein the at least one processor is further configured to execute the instructions to: allocate a third core of the plurality of cores of the CPU to perform tasks of a third type that is different from both the first type and the second type; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assign a first task of the third type to be performed by a first HT of the third core; and assign a second task of the third type to be performed by a second HT of the third core. (see e.g., column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) The automatic generation of threads is still valid.
Regarding claim 11, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The apparatus of claim 10, wherein the tasks of the first type comprise uplink tasks, the tasks of the second type comprise downlink tasks, and the tasks of the third type comprise sounding reference signal (SRS) tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”) (see e.g., page [007], lines [006-007], “In some embodiments, the scheduled operational task is an operational task associated with Sounding Reference Signal (SRS) transmission.”)
Regarding Claim 16, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The method of claim 12, wherein assigning the at least one task of the first type to be performed by the first core comprises: (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assigning a first task of the first type to be performed by a first hyperthread (HT) of the first core; and assigning a second task of the first type to be performed by a second HT of the first core. (see e.g. Teach, column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) This software has already automated the process of creating threads that can be used by hyperthreads.
Regarding claim 17, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The method of claim 16, wherein transitioning the first core to an idle state is performed when both the first task of the first type is completed by the first HT of the first core and the second task of the first type is completed by the second HT of the first core. (see e.g., page [001], paragraph [0003], “Accordingly, some of the processing cores in the multi-core processor system can become idle. In an example, there can be cores that stop executing tasks and are on stand-by until other processing cores complete their tasks. The cores that are idle without executing tasks are referred to as idle cores. The presence of these idle cores can be associated with a waste of system resources.”) This is the same claim as before, as a core with hyperthreading capabilities would still be considered to be “executing tasks” until all their hyperthreads are no longer executing tasks.
Regarding claim 18, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The method of claim 16, further comprising: assigning a first task of the second type to be performed by a first hyperthread (HT) of the second core; and assigning a second task of the second type to be performed by a second HT of the second core. (see e.g., column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) The threads are automatically generated custom for each bit of software, so the difference in the purpose of the task is not enough to disqualify it.
Regarding claim 19, Axmon, in view of Masuda, and further in view of Udava, and further in view of Liao discloses:
The method of claim 18, further comprising: allocating a third core of the plurality of cores of the CPU to perform tasks of a third type that is different from both the first type and the second type; (see e.g., page [003], paragraph [0021], “The first core 11 to third core 13 performs tasks that differ from each other. In the microcomputer 100 leads the first core 11 to third core 13 respective tasks simultaneously and in parallel.”)
assigning a first task of the third type to be performed by a first HT of the third core; and assigning a second task of the third type to be performed by a second HT of the third core. (see e.g., column 18, lines [0044 - 0015], “analyze source codes of a main thread to identify helper thread candidate code regions, the source codes including one or more code regions, each code region corresponding to a sequence of instructions representing an iteration loop in the source codes, the one or more code regions sharing at least one instruction in the source codes; estimate a communication cost to communicate live-in information computed by the main thread from the main thread to a helper thread for each code region; estimate a computation cost to compute live-in information by the helper thread for each code region; compare the communication cost to the computation cost for each code region; select a loop level represented by a code region from the one or more code regions for one or more helper threads with respect to the main thread based on a trade-off between the communication cost and the computation cost; generate software codes for the main thread based on the source codes; slice the generated software codes for the main thread to extract a reduced set of instructions relevant to one or more prefetching tasks for the selected region of the main thread; and generate software codes for the one or more helper threads different from the generated software code for the main thread and including the reduced set of instructions, the one or more helper threads being speculatively executed in parallel with the main thread to perform the one or more prefetching tasks; wherein the generated software codes for the one or more helper threads include synchronization code for the one or more helper threads to synchronize with the main thread during the execution.”) The automatic generation of threads is still valid.
wherein the tasks of the first type comprise uplink tasks, the tasks of the second type comprise downlink tasks, and the tasks of the third type comprise sounding reference signal (SRS) tasks. (see e.g., page [006], lines [0014-0020], “In some embodiments, the scheduled operational task is an operational task associated with Physical Downlink Control Channel (PDCCH) monitoring. In some embodiments, identifying the scheduled operational task which can be carried out in the non-overlapped portion of the communication slot comprises determining that there is at least one PDCCH monitoring position configured for the wireless device that fits within the non-overlapped portion of the communication slot, and determining that a reference signal needed for demodulation of PDCCH is available in the non-overlapped portion of the communication slot.”) (see e.g., page [006], lines [0032-0033], “In some embodiments, the scheduled operational task is an operational task associated with Physical Uplink Control Channel (PUUCH) transmission.”) (see e.g., page [007], lines [006-007], “In some embodiments, the scheduled operational task is an operational task associated with Sounding Reference Signal (SRS) transmission.”)
Conclusion
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/C.I.B./Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194