DETAILED ACTION
Status of Claims
Claim(s) 1-10, 17, and 25-33 are pending and are examined herein.
Claim(s) 11-16 and 18-24 are Canceled.
Claim(s) 1-10, 17, and 25-33 are rejected under 35 U.S.C. § 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement IDS(s) submitted on October 27, 2023, September 20, 2024, and February 14, 2025 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: means found in claim [33].
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 10, 17, 26-27, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over McKiernan et al., (Pub. No.: WO 2020168158 A1) in view of Satzinger et al., (Pub. No.: US 20220358392 A1), and further in view of Broughton et al., (NPL: "Tensorflow quantum: A software framework for quantum machine learning." (2020)). Hereinafter, the combination of McKiernan, Satzinger, and Broughton teaches the following.
Regarding Claim 1,
McKiernan discloses the following:
A method of operating a machine learning model in a hybrid computing system, the hybrid computing system comprising a quantum computing resource and a classical computing resource, the quantum computing resource comprising quantum processing unit (QPU) ... comprising a subset of qubit devices, (McKiernan, [0030] “all or part of the computing environment 101 operates as a hybrid computing environment, and the server 108 operates as a host system for the hybrid environment. For example, the programs 112 can be formatted as hybrid computing programs, which include instructions for execution by one or more quantum processor units and instructions that can be executed by another type of computing resource. The server 108 can allocate quantum computing resources (e.g., one or more QPUs, one or more quantum virtual machines, etc.) and other computing resources in the hybrid computing environment according to the schedule, and delegate computing jobs to the allocated computing resources for execution.” [0038] “a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment. ... the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel based on interactions with the controllers 106A.” [0054] “the host system 210 and the neural network 212 can be implemented on a classical computing system, and the quantum resource 214 can be implemented as a quantum processor unit (QPU) or a quantum virtual machine (QVM). For instance, in the computing environment shown in FIG. 1, the host system 210 and the neural network may be implemented by one or more CPUs and GPUs included in the controllers 106A, and the quantum resource 214 may be implemented by the quantum processor unit 103A.”), the method comprising:
defining quantum logic circuits to be executed on the respective QPU sublattices, wherein each of the quantum logic circuits is configured according to parameters of the machine learning model; (McKiernan, [0038] “the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel based on interactions with the controllers 106A.” [0087] “ on each iteration, the agent selects a quantum logic gate from the set of allowable quantum logic gates and appends this quantum logic gate to the end of the current program (which specifies a quantum logic circuit). The set of allowable quantum logic gates may include any combination of parametric gates, non-parametric gates, single qubit gates, two-qubit gates, etc. The selection of the quantum logic gate on each iteration is determined by the agent’s policy, which is given by the classical neural network 312.” Further see [0092], [0093], and [0115].) [Examiner’s Note: McKiernan teaches the quantum logic circuits constructed by appending gates selected using neural network policy. The multiple quantum processor cells within the QPU that run multiple instances of the quantum program (e.g., in parallel) would correspond to the “QPU sublattices.”]
translating the quantum logic circuits into quantum control programs for the respective QPU sublattices; (McKiernan, [0047] “the controllers 106A can interpret the quantum machine instructions and generate a hardware-specific control sequences configured to execute the operations proscribed by the quantum machine instructions. For example, the controllers 106A may generate control information that is delivered to the signal hardware 104A and converted to control signals that control the quantum processor cell 102A.” [0094] “At 352, the agent compiles the current version of the quantum program. In some examples, the un-compiled quantum program includes instructions expressed in quantum machine instruction language (e.g., Quil), or instructions expressed in another language (e.g., pyQuil) that generates quantum machine instructions. In the example shown in FIG. 3, the compiled quantum program includes instructions expressed as binary machine code.”) [Examiner’s Note: McKiernan teaches compiling from quantum logic circuits into hardware-specific control sequences (e.g., binary machine code). This correspond to the translation to quantum control programs.]
determining control parameters for the respective quantum control programs; (McKiernan, [0031]-[0032] In some cases, the server 108 can select the type of computing resource (e.g., quantum or otherwise) to execute an individual computing job in the computing environment 101... the server 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance... The quantum machine instruction library may include, for example, calibration procedures, hardware tests, quantum algorithms, quantum gates, etc.” [0041] “one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A... the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radio frequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processor cell 102A to operate qubit devices, readout devices, bias devices, coupler devices or other types of components in the quantum processor cell 102A.” [0050] “the controllers 106A generate control information (e.g., a digital waveform) that is delivered to the signal hardware 104A and converted to control signals (e.g., analog waveforms) for delivery to the quantum processor cell 102A. The digital control information can be generated based on quantum machine instructions, for example, to execute quantum logic operations, readout operations, or other types of control.”) [Examiner’s Note: McKiernan teaches the generation of control signals/information.]
executing the quantum control programs on the respective QPU sublattices to obtain a plurality of readout samples from the respective QPU sublattices; (McKiernan, [0095]-[0096] “The agent then provides the compiled quantum program to the quantum resource 314, which then executes the compiled current version of the quantum program. In some cases, the quantum resource 314 is a quantum processor unit (QPU) or a quantum virtual machine (QVM). In some cases, the quantum resource 314 is a set of multiple QPUs or QVMs that run multiple instances of the quantum program (e.g., in parallel)... the quantum resource 314 may execute the quantum program many times (e.g., hundreds, thousands, millions of times) to obtain quantum state information representing the quantum state produced by the quantum program.” [0073] “A measurement of this state with respect to the standard computational basis results in a bitstring b = b1b2 ... bn, where bt was the measured state of qubit t. This process of preparation and measurement may be repeated for some number of times (the “number of shots"), resulting in a sequence of bitstrings. After number of shots m, the resulting observation of the quantum state is an m x n binary array B = [b^; ... ; m)]. For example, if m = 100 and n = 10, the resulting observation of the quantum state is a 100 x 10 binary array
B
=
[
b
1
;
…
;
b
100
]
.” [0118] “The hybrid blade 816 may then compile the current program, for example, into binary machine code (e.g., operation 352 in FIGS. 3, 4, 7) or into patchable binary machine code (e.g., operation 352A in FIGS. 5, 6) and then patch the patchable binary machine code (e.g., operation 352B in FIGS. 5, 6).”) [Examiner’s Note: McKiernan the teaches parallel execution of compiled quantum programs on multiple QPUs and the generation of multiple bitstrings measurements (readout samples).] and
calculating activation parameters of the machine learning model based on the plurality of readout samples from the respective QPU sublattices. (McKiernan, [0097] “In the example shown, the agent receives measurements generated by the quantum resource 314 executing the current version of the quantum program, and computes “state” and “reward” information (e.g., according to Table 1 or otherwise) from the measurements. The reward information can be computed by evaluating a cost function (e.g., a cost function based on the Hamiltonian specified by the problem to be solved).” [0081] “At 222, the host system uses the state and the reward to update the parameters of the neural network 212, to define inputs to the neural network 212, or both.” [0076] “A neural network typically represents a sequence of mathematical transformations, mapping an input (e.g., an input vector) to an output (e.g., an output vector). These transformations (often referred to as layers) are typically parameterized by (1) weights that characterize a linear portion of the transformation and (2) activation functions that are typically nonlinear and have the effect of making the composition of layers nontrivial.” [0105] “As shown in FIG. 4 , if the reward does not satisfy the “solved” criteria at 356, then the agent provides the “state” and “reward” information to the neural network 312 for the next iteration of the process 400.”) [Examiner’s Note: McKiernan teaches the layer-wise transformation to update neural network parameters using the state and reward values derived from the qubit measurements.]
While McKiernan teaches quantum computing architecture (QPU) that includes multiple quantum processor cells to operate qubit devices, McKiernan does not explicitly define quantum processing unit (QPU) sublattices each comprising a subset of qubit devices. In other words, McKiernan does not appear to explicitly suggest that the quantum processing unit is segmented into multiple QPU sublattices. Additionally, While McKiernan computes the state and rewards from the readout measurement to update the parameters of the neural network layers, McKiernan does not appear to explicitly suggest: calculating activation parameters of the machine learning model based on the plurality of readout samples.
However, McKiernan in view of Satzinger teaches the limitations:
the hybrid computing system comprising a quantum computing resource and a classical computing resource, (Satzinger, [0031] “The system 100 includes a classical processor 102 in data communication with quantum computing hardware 104. For convenience, the classical processor 102 and quantum computing hardware 104 are illustrated as separate entities, however in some implementations the classical processor 102 can be included in quantum computing hardware 104, e.g., the quantum computing hardware 104 can include one or more components for performing classical computing operations.”) the quantum computing resource comprising quantum processing unit (QPU) sublattices each comprising a subset of qubit devices, (Satzinger, [0032] “The quantum computing hardware 104 includes components for performing quantum computations using quantum circuits. For example, the quantum computing hardware 104 includes a quantum system 120 and control devices 122.” [0039] “The random quantum circuit generator 110 can also be configured to define random benchmarking quantum circuits based on defined initial quantum circuits. Each initial quantum circuit defined by the random quantum circuit generator 110 can be partitioned into multiple layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel. An example partitioning of an initial quantum circuit into multiple layers where instances of the two-qubit gate in each layer can be implemented in parallel is illustrated and described below with reference to FIG. 2A.” [0051]-[0052] “FIG. 2A illustrates an example partitioning of an initial quantum circuit 200 into multiple layers 200 a-200 d that can be implemented in parallel. The example initial quantum circuit 200 operates on a square array of qubits, e.g., qubit 202 (though it will be appreciated that other array shapes may alternatively be used). The example initial quantum circuit 200 includes multiple instances of a two-qubit gate that is configured to operate on nearest-neighboring pairs of qubits, e.g., two-qubit gate 204. Each neighboring pair of qubits in the square array is operated on by a respective two-qubit gate... The example initial quantum circuit 200 can be partitioned into multiple layers of instances of the two-qubit gate, in this example four layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel.”)
defining quantum logic circuits to be executed on the respective QPU sublattices, (Satzinger, [0038]-[0040] “The random quantum circuit generator 110 can be configured to define quantum circuits based on the quantum computing hardware 104 (e.g., the number of qubits included in the quantum computing hardware, how they are arranged and how they interact with one another) and the received input data 106. For example, the random quantum circuit generator 110 can be configured to define initial quantum circuits that include multiple instances of the two-qubit gate specified in the input data 106, where each instance of the two-qubit gate performs a same operation on a respective pair of interacting qubits in the quantum system 120... Each initial quantum circuit defined by the random quantum circuit generator 110 can be partitioned into multiple layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel... each defined random benchmarking quantum circuit corresponds to a respective partitioned layer of instances of the two-qubit gate.”)
translating the quantum logic circuits into quantum control programs for the respective QPU sublattices; (Satzinger, [0044] “The classical processor 102 is configured to transmit data 116 representing defined benchmarking quantum circuits to the quantum computing hardware 104. The quantum computing hardware 104 is configured to implement the defined benchmarking quantum circuits using the quantum system 120 and control devices 122.” Further see [0035].)
determining control parameters for the respective quantum control programs; (Satzinger, [0035] “A control model represents a mapping between parameters of a quantum gate (e.g. qubit rotation angle, phases, etc.) and control parameters of the physical system used to implement the quantum gate (e.g. control line voltages, pulse shapes, operating frequencies etc.).” [0049] “The data processing module 114 is further configured to use the estimated fidelity of the two-qubit gate to determine adjusted control parameters θ′,ϕ′ of the control model U specified by the input data 106. For example, the control parameters θ,ϕ can be adjusted to minimize an error as estimated by the applied benchmarking techniques.” Further see [0066].) [Examiner’s Note: the determined/adjusted control parameters of the control model for implementing the quantum gate correspond to the control parameters for the respective quantum control programs.]
executing the quantum control programs on the respective QPU sublattices to obtain a plurality of readout samples from the respective QPU sublattices; (Satzinger, [0044]-[0045] “The quantum computing hardware 104 is configured to implement the defined benchmarking quantum circuits using the quantum system 120 and control devices 122. Because of the specific construction of the benchmarking quantum circuits defined by the random quantum circuit generator 110, the quantum computing hardware 104 implements two-qubit gates in each layer of instances of the two-qubit gate in parallel... The quantum computing hardware 104 can provide as output data representing results of the circuit implementations, e.g., experimental benchmarking data 124, and transmit the data to the classical processor 102... the experimental benchmarking data 124 can include multiple n-bit bit strings representing results of measuring all qubits at the same time.” [0063] “To implement each constructed benchmarking circuit, the system initializes each qubit in the 2D array of qubits in an initial state |0>⊗n, applies the constructed benchmarking circuit to the initialized qubits in the 2D array of qubits, and measures each qubit in the 2D array of qubits to obtain measurement data for each qubit.” Further see [0066].) [Examiner’s Note: the constructed quantum circuits (control programs) executed on the QPU to obtain bit strings measurements for each qubit pair.]
McKiernan and Satzinger are from the same field of endeavor and their disclosure generally relates to (quantum computing).
Accordingly, at the effective filing date, it would have been prima facie obvious to one ordinarily skill in the art to modify the combination of McKiernan and Satzinger to incorporate the method for benchmarking quantum computing hardware as taught by Satzinger. One would have been motivated to make such a combination in order to determine adjustments that may improve the accuracy of existing quantum computing hardware, e.g., improve the accuracy at which the quantum computing hardware performs quantum operations (Satzinger [0018]).
McKiernan in view of Satzinger may not appear to explicitly suggest: calculating activation parameters of the machine learning model based on the plurality of readout samples. However, it would have been obvious in view of Broughton.
Hereinafter, Broughton, in combination with McKiernan in view of Satzinger, teaches:
executing the quantum control programs on the respective QPU sublattices to obtain a plurality of readout samples from the respective QPU sublattices; (Broughton, [p. 10, Section: II-E] “Sampling from quantum circuits is an important use case in quantum computing... TFQ implements tfq.layers.Sample , a Keras layer which enables sampling from batches of circuits in support of design objective... the Sample layer produces a tf.RaggedTensor of shape [batch_size, num_samples, n_qubits] , where the n qubits dimension is ragged to account for the possibly varying circuit size over the input batch of quantum data.” [p.7, Section: II-D] “In the simplest case, expectation values are simply averages over samples. In quantum computing, expectation values are typically taken with respect to a measurement operator M. This involves sampling bitstrings from the quantum circuit as described above, applying M to the list of bitstring samples to produce a list of numbers, then taking the average of the result... The expectation layer is capable of using either a simulator or a real device for execution, and this choice is simply specified at run time. While Cirq simulators may be used for the backend, TFQ provides its own native TensorFlow simulator written in performant C++. A description of our quantum circuit simulation code is given in section IIF.”) [Examiner’s Note: The paper describes the execution of parametrized circuits ops on QPU to obtain readout samples (i.e., bitstrings measurements) such as [batch_size, num_samples, n_qubits] measurement tensor.]
calculating activation parameters of the machine learning model based on the plurality of readout samples from the respective QPU sublattices. (Broughton, [p.11, Section: II-E] “In the simplest case, expectation values are simply averages over samples. In quantum computing, expectation values are typically taken with respect to a measurement operator M. This involves sampling bitstrings from the quantum circuit as described above, applying M to the list of bitstring samples to produce a list of numbers, then taking the average of the result... The expectation layer is capable of using either a simulator or a real device for execution, and this choice is simply specified at run time. While Cirq simulators may be used for the backend, TFQ provides its own native TensorFlow simulator written in performant C++. A description of our quantum circuit simulation code is given in section IIF.” [P. 8, Section: II-D] “Once classical information has been extracted, it is in a format amenable to further classical post-processing... classical deep neural networks can be applied to distill such correlations. Since TFQ is fully compatible with core TensorFlow, quantum models can be attached directly to classical tf.keras.layers.Layer objects such as tf.keras.layers.Dense.” [Pp. 17-18, Section: III-D] “Hence, if we would like the QNN to become more like a classical neural network block, i.e. mapping vectors to vectors f : RM → RN, we can obtain a vector-valued differentiable function from the QNN by considering it as a function of the parameters which outputs a vector of expectation values of different operators, (see Eq (17) and (18).” [P. 19, Section: III-C] Fig.12 “Here we have classical deep neural networks (DNN) both preceding and postceding the quantum neural network (QNN). In this example, the preceding DNN outputs a set of parameters θ which are used as then used by the QNN as parameters for inference. The QNN outputs a vector of expectation values (estimated through several runs) whose components are (hθ)k = ˆ hk θ . This vector is then fed as input to another (post-ceding) DNN, and the loss function L is computed from this output.”) [Examiner’s Note: The paper describes a quantum-classical neural network where QNN block takes parameterized quantum circuits programs, generate samples of bitstrings, and computes expectation value vectors from the readout samples. The vectors of the expectation values fed into subsequent classical neural network layer, which represents the activation parameters.]
McKiernan, Satzinger, and Broughton are from the same field of endeavor and their disclosure generally relates to (quantum computing).
Accordingly, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, having the combination of McKiernan, Satzinger, and Broughton before them, to incorporate the TensorFlow Quantum (TFQ) framework as taught by Broughton. One would have been motivated to make such a combination in order to apply TFQ to tackle advanced quantum learning tasks. Doing so would accelerate the development of quantum machine learning algorithms for a wide array of applications (Broughton [Section: VI]).
Regarding Claim 2, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 1 as outlined above, and further teaches:
wherein each of the quantum logic circuits comprises a sequence of quantum logic gates comprising one or more single-qubit quantum logic gates and one or more multi-qubit quantum logic gates. (McKiernan, [0039] “In some examples, the operations can be expressed as single-qubit logic gates, two-qubit logic gates, or other types of quantum logic gates that operate on one or more qubits. A sequence of quantum logic operations can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.”)
Regarding Claim 3, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 1 as outlined above, and further teaches:
wherein the quantum logic circuits are configured according to topologies of the respective QPU sublattices. (Satzinger, [0038] “The random quantum circuit generator 110 can be configured to define quantum circuits based on the quantum computing hardware 104 (e.g., the number of qubits included in the quantum computing hardware, how they are arranged and how they interact with one another) and the received input data 106. For example, the random quantum circuit generator 110 can be configured to define initial quantum circuits that include multiple instances of the two-qubit gate specified in the input data 106, where each instance of the two-qubit gate performs a same operation on a respective pair of interacting qubits in the quantum system 120.” [0051]-[0052] “The example initial quantum circuit 200 operates on a square array of qubits,.. The example initial quantum circuit 200 includes multiple instances of a two-qubit gate that is configured to operate on nearest-neighboring pairs of qubits,... The example initial quantum circuit 200 can be partitioned into multiple layers of instances of the two-qubit gate, in this example four layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel.”) [Examiner’s Note: The quantum logic circuits (benchmarking circuits) are configured based on the arrangement/topology of qubits in each partitioned layer (e.g., square array with nearest-neighbor pairs). The qubit gates assignments is based on the topology/arrangement of the qubit pairs in the layer. See [0062].]
Regarding Claim 5, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 1 as outlined above, and further teaches:
wherein each of the quantum logic circuits comprises a respective sequence of quantum logic gates, (Satzinger, [0026] “A quantum circuit is a model for quantum computation in which quantum logic gates are applied in a specific sequence to a register of qubits to encode quantum information. In theory, any quantum algorithm can be implemented with high precision by applying a correctly chosen sequence of quantum logic gates.” Further see McKiernan [0039].) and determining the control parameters for each of the quantum control programs comprises: (Satzinger, [0050] “The classical processor 102 provides as output data representing the adjusted control model U(θ′,ϕ′). In some implementations an outer loop may be performed to find optimal values of the control parameters to further improve the performance of the quantum computing hardware 104, i.e. the method may be iterated.” [0065] “The system adjusts control parameters of the control model for implementing the two-qubit quantum gate using the generated experimental benchmarking data (step 312).” Further see [0049].)
translating a subset of the parameters of the machine learning model to quantum logic gate parameters; (McKiernan, [0017]-[0018] “neural networks are used to generate quantum programs. For instance, a training process can be used to train the neural network (e.g., using deep reinforcement learning or another type of machine learning process), and then the neural network can be sampled to construct quantum programs configured to generate solutions to specific problems. a quantum program is synthesized by iteratively adding quantum logic gates to a quantum logic circuit, and a statistical model is used to select the quantum logic gate to be added to the quantum logic circuit on each iteration. For instance, a neural network may provide a distribution of values for a set of allowed quantum logic gates, such that the distribution indicates each gate’s relative likelihood of improving the quantum program.” [0105]-[0107] “at 350 the agent can choose from a set of quantum logic gates that includes one or more parametric gates... the updated version of the quantum program may be generated at 350 with a variable parameter (e.g., a variable rotation angle or another type of variable parameter)... At 362, the agent optimizes the variable parameters in the quantum program. For example, the agent may use the GPU 316 to determine an updated value for one or more variable parameters to improve performance of the quantum program.”)
determining the control parameters for the quantum control program based on device parameters of a QPU sublattice and the quantum logic gate parameters. (Satzinger, [0033] “in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency.” [0035] “ A control model represents a mapping between parameters of a quantum gate (e.g. qubit rotation angle, phases, etc.) and control parameters of the physical system used to implement the quantum gate (e.g. control line voltages, pulse shapes, operating frequencies etc.).” [0050] “An adjusted control model U(θ′,ϕ′) can be used by the system 100 to perform the two-qubit quantum gate in future applications, e.g., as part of a quantum computation performed by the quantum computing hardware 104.”)
Regarding Claim 10,
the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 1 as outlined above, and further teaches:
prior to executing the quantum control programs, patching the quantum control programs based on the respective control parameters. (McKiernan, [0106]-[0107] “At 352B, definite values of the variable parameters are selected, and the patchable binary machine code is patched to generate the full, compiled quantum program... On each iteration of the internal optimization loop, the patchable binary machine code (from 352A) is patched based on new values for the variable parameters (from 362) to generate a new compiled version of the quantum program. The agent then obtains (at 354) additional quantum processor output data generated by the quantum resource 314 executing the new compiled version of a quantum program...”) [Examiner’s Note: McKiernan teaches generating the binary machine code that is patched with selected parameters values before being executed on the quantum processor.]
Regarding Claim 17,
The claim recites substantially similar limitations as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. Claim 1 is directed to a method, and claim 17 is directed to a hybrid computing system.
McKiernan, in combination with Satzinger and Broughton, also discloses a hybrid computing system comprising: a quantum computing resource, the quantum computing resource comprising quantum processing unit (QPU) sublattices each comprising a subset of qubit devices. (McKiernan, [0019] “In some cases, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system.” [0030] “In some implementations, all or part of the computing environment 101 operates as a hybrid computing environment, and the server 108 operates as a host system for the hybrid environment. For example, the programs 112 can be formatted as hybrid computing programs, which include instructions for execution by one or more quantum processor units and instructions that can be executed by another type of computing resource. The server 108 can allocate quantum computing resources (e.g., one or more QPUs, one or more quantum virtual machines, etc.) and other computing resources in the hybrid computing environment according to the schedule, and delegate computing jobs to the allocated computing resources for execution.”)
Regarding Claim 26,
The claim recites substantially similar limitations as corresponding claim 10 and is rejected for similar reasons as claim 10 using similar teachings and rationale.
Regarding Claim 27, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan teaches: executing the quantum control programs comprises executing the quantum control programs on the first and second QPU sublattices in parallel. (McKiernan, [0095] “The agent then provides the compiled quantum program to the quantum resource 314, which then executes the compiled current version of the quantum program. In some cases, the quantum resource 314 is a quantum processor unit (QPU) or a quantum virtual machine (QVM). In some cases, the quantum resource 314 is a set of multiple QPUs or QVMs that run multiple instances of the quantum program (e.g., in parallel). [0115] “The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel.” [0117]-[0119] “The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel. The two parallel QPU systems 810 and respective control racks 814 may be operated independently, for example, in parallel. For instance, each system may be used to train distinct neural networks in parallel, and the two neural networks may then be combined to form a larger neural network.”)
Satzinger, in combination with McKiernan, further teaches: wherein the hybrid computing system comprises: a first QPU comprising first QPU sublattices; and a second, distinct QPU comprising second QPU sublattices, and wherein executing the quantum control programs comprises executing the quantum control programs on the first and second QPU sublattices in parallel. (Satzinger, [0039] “The random quantum circuit generator 110 can also be configured to define random benchmarking quantum circuits based on defined initial quantum circuits. Each initial quantum circuit defined by the random quantum circuit generator 110 can be partitioned into multiple layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel. An example partitioning of an initial quantum circuit into multiple layers where instances of the two-qubit gate in each layer can be implemented in parallel is illustrated and described below with reference to FIG. 2A.” [0044] “Because of the specific construction of the benchmarking quantum circuits defined by the random quantum circuit generator 110, the quantum computing hardware 104 implements two-qubit gates in each layer of instances of the two-qubit gate in parallel.” [0052] “For example, layers 200 a-200 d each include a respective subset of the multiple instances of the two-qubit gate included in the example initial quantum circuit 200. Since each qubit in each layer 200 a-200 d is only operated on by one two-qubit gate, the two-qubit gates in each of the layers 200 a-200 d can be implemented in parallel.”) [Examiner’s Note: Satzinger teaches the initial quantum circuits consist of one or more quantum circuits that are being partitioned into multiple layers and executed in parallel.]
Regarding Claim 29, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan, in combination with Satzinger and Broughton, teaches: wherein the quantum logic circuits are first quantum logic configured according to model parameters of nodes in a first layer of the machine learning model, and the operations comprise: (McKiernan, [0076] “A neural network typically represents a sequence of mathematical transformations, mapping an input (e.g., an input vector) to an output (e.g., an output vector). These transformations (often referred to as layers) are typically parameterized by (1) weights that characterize a linear portion of the transformation and (2) activation functions that are typically nonlinear and have the effect of making the composition of layers nontrivial. In this context, the initial layer is the first transformation applied to the measured bitstrings...” [0087] “on each iteration, the agent selects a quantum logic gate from the set of allowable quantum logic gates and appends this quantum logic gate to the end of the current program (which specifies a quantum logic circuit)... The selection of the quantum logic gate on each iteration is determined by the agent’s policy, which is given by the classical neural network 312.”) updating the model parameters according to the activation parameters; (McKiernan, [0100]-[0102] “The input vector can be of length one (i.e., n=l), specifying the most recent (state, reward) pair, or it can be longer (n>l) and include a "memory" over the last several (state, reward) pairs. The input vector is used to compute a loss function, and derivatives of the loss function are taken with respect to each parameter of the neural network. The derivatives are used to update the parameters of the neural network, for example, according to an optimization technique such as stochastic gradient descent or otherwise... the GPU 316 is used to compute updated parameters for the neural network, and the agent updates the neural network 312 based on the new parameters computed by the GPU 316... After the parameters of the neural network 312 have been modified, the agent executes another iteration of the process 300. For example, each iteration of the iterative process may include: operating the updated neural network to produce neural network output data for the iteration based on the current “state” and “reward” information (at 350); selecting a quantum logic gate for the iteration based on the neural network output data (at 350); generating an updated version of the quantum program that includes the selected quantum logic gate for the iteration (at 350).”) translating the updated model parameters to updated quantum logic gate parameters; (McKiernan, [0102] “compiling the quantum program for the iteration (at 352); generating quantum processor output data for the iteration by executing the quantum program; computing quantum state information and reward information for the iteration based on the quantum processor output data (at 354); and updating the neural network (at 358) if the “solved” criteria are not met. As such, in each iteration, a new version of the quantum program is generated based on the updated neural network, and the quantum resource 314 executes the new version of the quantum program.”) ... and using the updated control parameters to execute the quantum control programs on the respective QPU sublattices. (McKiernan, [0021] “The computing environment 101 shown in FIG. 1 includes a server 108, quantum processor units 103A, 103B and other computing resources 107. The computing environment 101 may also include one or more of the access nodes (e.g., the example access node HOA) and other features and components” [0038] “ a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment... the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel based on interactions with the controllers 106A.” [0094] “he quantum resource 314 is a set of multiple QPUs or QVMs that run multiple instances of the quantum program (e.g., in parallel).” [0115] “The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel.”)
Satzinger, in combination with McKiernan and Broughton, further teaches: updating the model parameters according to the activation parameters; (Satzinger, [0036] “The classical processor 102 processes the received input data 106 to generate as output data 108 representing an adjusted control model U(θ′,ϕ′). For example, the output data 108 may include a control model whose model parameters θ,ϕ have been adjusted such that the control model U(θ′,ϕ′) provides a representation of the two-qubit gate that, when implemented by the quantum computing hardware 104, achieves improved gate fidelity.”) [Examiner’s Note: the adjusted model parameters of the control model based on benchmarking circuit result reads on the updating the model parameters according to the activation parameters.] translating the updated model parameters to updated quantum logic gate parameters; (Satzinger, [0035]-[0036] “A control model represents a mapping between parameters of a quantum gate (e.g. qubit rotation angle, phases, etc.) and control parameters of the physical system used to implement the quantum gate (e.g. control line voltages, pulse shapes, operating frequencies etc.)... The classical processor 102 processes the received input data 106 to generate as output data 108 representing an adjusted control model U(θ′,ϕ′). For example, the output data 108 may include a control model whose model parameters θ,ϕ have been adjusted such that the control model U(θ′,ϕ′) provides a representation of the two-qubit gate that, when implemented by the quantum computing hardware 104, achieves improved gate fidelity.” [0014] “the control parameters of the control model comprise control angles of one or more quantum gates.”) determining updated control parameters for the respective quantum control programs based on the updated quantum logic gate parameters; (Satzinger, [0035] “A control model represents a mapping between parameters of a quantum gate (e.g. qubit rotation angle, phases, etc.) and control parameters of the physical system used to implement the quantum gate (e.g. control line voltages, pulse shapes, operating frequencies etc.).” [0049]-[0050] “The data processing module 114 is further configured to use the estimated fidelity of the two-qubit gate to determine adjusted control parameters θ′,ϕ′ of the control model U specified by the input data 106.... An adjusted control model U(θ′,ϕ′) can be used by the system 100 to perform the two-qubit quantum gate in future applications, e.g., as part of a quantum computation performed by the quantum computing hardware 104.”) and using the updated control parameters to execute the quantum control programs on the respective QPU sublattices. (Satzinger, [0050]-[0052] “An adjusted control model U(θ′,ϕ′) can be used by the system 100 to perform the two-qubit quantum gate in future applications, e.g., as part of a quantum computation performed by the quantum computing hardware 104... where instances of the two-qubit gate in a respective layer can be implemented in parallel.” [0044] “the quantum computing hardware 104 implements two-qubit gates in each layer of instances of the two-qubit gate in parallel.”) [Examiner’s Note: the updated/adjusted control model is implement quantum operations across the partitioned layers (qubits array).]
Claim(s) 4, 9, 25, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of McKiernan, Satzinger, and Broughton as outlined above, and further in view of in view of Scheer et al., (Pub. No.: WO 2020036673 A2).
Regarding Claim 4,
the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 3 as outlined above, and further teaches:
wherein the hybrid computing system comprises one or more QPUs that comprise: the QPU sublattices; and tunable-frequency coupler devices coupled to one or more of the qubit devices, (Satzinger, [0031] “The system 100 includes a classical processor 102 in data communication with quantum computing hardware 104. For convenience, the classical processor 102 and quantum computing hardware 104...” [0033] “The multi-level quantum subsystems can be frequency tunable. For example, each qubit may have associated operating frequencies that can be adjusted, e.g., using one or more control devices 122, through application of voltage pulses via one or more drivelines coupled to the qubit... in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. In other cases, e.g., when the qubits interact via tunable couplers, qubits can be configured to interact with one another by setting the parameters of their respective couplers to enable interactions between the qubits and then by setting the qubit's respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency.” [0052] “The example initial quantum circuit 200 can be partitioned into multiple layers of instances of the two-qubit gate, in this example four layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel.”) [Examiner’s Note: Satzinger teaches the tunable couplers as part of the control devices to enable interactions between qubits and controlling the partition of the qubit array into multiple layers (subset) where neighboring pair of qubits are connected.]
The combination of McKiernan, Satzinger, and Broughton does not appear to explicitly teach:
wherein the method comprises determining the topologies of the respective QPU sublattices based on device parameters of the tunable-frequency coupler devices.
However, Scheer, in combination with McKiernan, Satzinger, and Broughton, teaches the limitation:
wherein the method comprises determining the topologies of the respective QPU sublattices based on device parameters of the tunable-frequency coupler devices. (Scheer, [0049] “he example caps 350A, 350B each include traces 314 and active coupler devices 356 that connect respective pairs of the bonds 312... The active coupler devices 356 may be implemented, for example, by tunable resonator devices (e.g., by tunable transmon devices or other types of tunable resonators).” [0072] “quantum logic gate performance is tested at 604. Quantum logic gate performance criteria may be tested at cryogenic temperatures (e.g., below 10 mK). In some cases, single-qubit performance characteristics such as, for example, single-qubit quantum logic gate fidelities and single-qubit quantum state readout fidelities, are evaluated. In some cases, multi-qubit performance characteristics such as, for example, two-qubit quantum logic gate fidelities are evaluated.” [0077] “ In some cases, other types of components may be evaluated and categorized at 604 and 606. For example, the caps 306 shown in FIGS. 3A, 3B, 3C, 3D or the substrates 402 shown in FIGS. 4A and 4B may be evaluated and categorized. For instances, the caps 306 may be categorized according to cap room temperature, electrical conductivity (e.g., whether the cap is electrically conductive or not), and other types of properties.” [0078] “At 608, a subset of the quantum processor modules is selected from appropriate categories determined at 606.”) [Examiner’s Note: Scheer selecting/arranging modules based on evaluating parameters including tunable coupler devices (e.g., gate fidelities, flux bias, cap properties, etc.).]
Accordingly, at the effective filing date, it would have been prima facie obvious to one ordinarily skilled in the art to modify the combination of McKiernan, Satzinger, Broughton, and Scheer to incorporate the modular quantum processor architectures as taught by Scheer. One would have been motivated to make such a combination in order to provide an improved spatial layout for connecting the qubit devices to external control systems. Doing so would optimize the pitch of vertical connections to input and output signal connections (Scheer [0022]).
Regarding Claim 9, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 1 as outlined above, and further teaches:
wherein the hybrid computing system comprises one or more QPUs that comprise: the QPU sublattices; and tunable-frequency coupler devices operably coupled between neighboring QPU sublattices, (Satzinger, [0031] “The system 100 includes a classical processor 102 in data communication with quantum computing hardware 104. For convenience, the classical processor 102 and quantum computing hardware 104...” [0033] “The multi-level quantum subsystems can be frequency tunable. For example, each qubit may have associated operating frequencies that can be adjusted, e.g., using one or more control devices 122, through application of voltage pulses via one or more drivelines coupled to the qubit... in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. In other cases, e.g., when the qubits interact via tunable couplers, qubits can be configured to interact with one another by setting the parameters of their respective couplers to enable interactions between the qubits and then by setting the qubit's respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency.” [0052] “The example initial quantum circuit 200 can be partitioned into multiple layers of instances of the two-qubit gate, in this example four layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel.”) [Examiner’s Note: Satzinger teaches the tunable couplers as part of the control devices to enable interactions between qubits and controlling the partition of the qubit array into multiple layers (subset) where neighboring pair of qubits are interconnected.]
While Satzinger describes the control devices that represents tunable couplers and uses a control lines to enable interactions between the qubits, the combination of McKiernan, Satzinger, and Broughton:
wherein executing the quantum control programs comprises communicating control signals to the tunable-frequency coupler devices to deactivate couplings between the neighboring QPU sublattices.
However, Scheer, in combination with McKiernan, Satzinger, and Broughton, teaches the limitation:
wherein executing the quantum control programs comprises communicating control signals to the tunable-frequency coupler devices to deactivate couplings between the neighboring QPU sublattices. (Scheer, [0050]-[0051] “The example caps 350A, 350B shown in FIG. 3D also include control lines configured to activate or deactivate the active coupler devices 356. Each of the control lines includes a respective flux bias device 354 that can generate a magnetic flux, and the magnetic flux generated by a control line can be controlled to activate or deactivate the neighboring active coupler device 356... Each control line includes an input port 352, 358 that can receive the coupler device control signal that controls the magnetic flux that activates or deactivates the associated coupler device 356... In some aspects of operation, the magnetic flux generated by a control line tunes a resonance frequency of the associated active coupler device 356. The resonance frequency of the active coupler device 356 may be tuned to an active state, for example, a state that activates coupling between qubit devices on different quantum circuit chips. Or the resonance frequency of the active coupler device 356 may be tuned to an inactive state, for example, a state that deactivates coupling between qubit devices on different quantum circuit chips.”)
The same motivation that was utilized for combining McKiernan, Satzinger, Broughton, and Scheer as set forth in claim 4 is equally applicable to claim 9.
Regarding Claim 25,
The claim recites substantially similar limitations as corresponding claim 9 and is rejected for similar reasons as claim 9 using similar teachings and rationale.
Regarding Claim 30, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan, in combination with Satzinger and Broughton, teaches: wherein the hybrid computing system comprises at least one modular QPU comprising a plurality of quantum processor modules, qubit devices in two distinct quantum processing modules are communicably coupled through at least one inter-chip coupler device, and executing the quantum control programs ...(McKiernan, [0115] “The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel.” [0119] “The two parallel QPU systems 810 and respective control racks 814 may be operated independently, for example, in parallel. For instance, each system may be used to train distinct neural networks in parallel, and the two neural networks may then be combined to form a larger neural network.”)
The combination of McKiernan, Satzinger, and Broughton does not appear to explicitly teach:
communicating control signals to the at least one inter-chip coupler device to deactivate couplings between the qubit devices in the two distinct quantum processor modules.
However, Scheer, in combination with McKiernan, Satzinger, and Broughton, teaches the limitation:
wherein the hybrid computing system comprises at least one modular QPU comprising a plurality of quantum processor modules, qubit devices in two distinct quantum processing modules are communicably coupled through at least one inter-chip coupler device, and executing the quantum control programs comprises: (Scheer, [0012] “a quantum processor includes multiple distinct quantum processor modules. For example, in some implementations, a quantum processor that includes N qubit devices may be manufactured from M distinct quantum processor modules that each include N/M qubit devices.” [0026] “The example quantum processor 102 shown in FIG. 1 includes multiple quantum processor modules. For example, the quantum processor 102 may include a two-dimensional or three-dimensional array of quantum processor modules, and each quantum processor module may include an array of circuit devices.” [0040] “FIG. 3 A is a diagram of an example modular superconducting quantum processor 300 that includes four superconducting quantum circuit chips 304 on one printed circuit board (PCB) 302.” [0049] “The example caps 350A, 350B each include traces 314 and active coupler devices 356 that connect respective pairs of the bonds 312. As shown in FIG. 3D, each bond 312 in the example caps 350A, 350B is connected to one other bond 312 at a neighboring corner of the cap. The active coupler devices 356 may be implemented, for example, by tunable resonator devices (e.g., by tunable transmon devices or other types of tunable resonators).” [0059] “ The coupling resonators in the resonator buses 506 are used for exchanging information or mediating entanglement between the respective quantum circuit chips 504. In the example shown, the resonator buses 506 include a series of resonators arranged as resonator buses, tunable couplers, etc.”) communicating control signals to the at least one inter-chip coupler device to deactivate couplings between the qubit devices in the two distinct quantum processor modules. (Scheer, [0050] “The example caps 350A, 350B shown in FIG. 3D also include control lines configured to activate or deactivate the active coupler devices 356. Each of the control lines includes a respective flux bias device 354 that can generate a magnetic flux, and the magnetic flux generated by a control line can be controlled to activate or deactivate the neighboring active coupler device 356.” [0093] “The cap structure may include a control line configured to activate or deactivate the active coupler device. Activating the active coupler device selectively couples at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. The control line may comprise a flux bias device configured to generate a magnetic flux to activate or deactivate the active coupler device.” Further see [0106].)
The same motivation that was utilized for combining McKiernan, Satzinger, Broughton, and Scheer as set forth in claim 4 is equally applicable to claim 30.
Regarding Claim 31, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan, in combination with Satzinger and Broughton, teaches: wherein the hybrid computing system comprises a plurality of QPUs in distinct thermal environments, ..., and executing the quantum control programs comprises: (McKiernan, [0021] “The example computing environment 101 includes computing resources and exposes their functionality to the access nodes 110A, 110B, HOC (referred to collectively as “access nodes 110”). The computing environment 101 shown in FIG. 1 includes a server 108, quantum processor units 103A, 103B and other computing resources 107. The computing environment 101 may also include one or more of the access nodes (e.g., the example access node HOA) and other features and components... The computing environment 101 or the access nodes 110 may also have access to one or more remote QPUs (e.g., QPU 103C). A” [0027] “the server 108 may send a computing job to the quantum processor unit 103A, the quantum processor unit 103B or any of the other computing resources 107.”) [Examiner’s Note: the QPU units are located in a separate environments (e.g., 103A, 103B, and 103C). See Fig. 1.]
The combination of McKiernan, Satzinger, and Broughton does not appear to explicitly teach:
qubit devices in two distinct QPUs are communicably coupled through at least one optical link, ... communicating control signals to the at least one optical link to deactivate couplings between the qubit devices in the two distinct QPUs.
However, Scheer, in combination with McKiernan, Satzinger, and Broughton, teaches the limitation:
qubit devices in two distinct QPUs are communicably coupled through at least one optical link, and executing the quantum control programs comprises: communicating control signals to the at least one optical link to deactivate couplings between the qubit devices in the two distinct QPUs. (Scheer, [0049]-[0050] “The active coupler devices 356 may be implemented, for example, by tunable resonator devices (e.g., by tunable transmon devices or other types of tunable resonators)... The example caps 350A, 350B shown in FIG. 3D also include control lines configured to activate or deactivate the active coupler devices 356.” [0059]-[0062] “The coupling resonators in the resonator buses 506 are used for exchanging information or mediating entanglement between the respective quantum circuit chips 504. In the example shown, the resonator buses 506 include a series of resonators arranged as resonator buses, tunable couplers, etc... In some cases, each of the resonator buses 506 is implemented as a multi- mode resonator bus that allows selective coupling between pairs of devices on distinct chips 504... In some instances, the architecture shown in FIG. 5A uses a parametric coupling technique to communicate between the qubits on separate chips 504 in a memory structure.” [0067] “The resonator bus 556 can provide coupling between the qubit devices in distinct quantum circuit chips 554.” [0040] “FIG. 3 A is a diagram of an example modular superconducting quantum processor 300 that includes four superconducting quantum circuit chips 304 on one printed circuit board (PCB) 302.”) [Examiner’s Note: the “optical link” is broadly interpreted as coupling link that provides communication for data transfer/exchange. The resonator buses or tunable transmon devices exchange control signals/links to deactivates coupling between qubit devices on different quantum circuit chips. ]
The same motivation that was utilized for combining McKiernan, Satzinger, Broughton, and Scheer as set forth in claim 4 is equally applicable to claim 31.
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of McKiernan, Satzinger, and Broughton as outlined above, and further in view of Havlicek et al., (NPL: "Supervised learning with quantum enhanced feature spaces." (2018)).
Regarding Claim 6, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 5 as outlined above, and further teaches:
While the combination of McKiernan, Satzinger, and Broughton the parameters of the machine learning model comprise input parameters and model parameters and translating the subset of the parameters of the machine learning model to the quantum logic gate parameters. Broughton also teaches the TFQ framework used to define quantum neural networks as products of parameterized unitary matrices, and describes the unitaries that prepare each initial state and the unitaries representing the quantum circuit. The combination of McKiernan, Satzinger, and Broughton does not appear to explicitly teach:
translating a first subset of the input parameters of the machine learning model to a first subset of the quantum logic gate parameters of the first unitary transformation.
However, Havlicek, in combination with McKiernan, Satzinger, and Broughton, teaches the limitations:
wherein the parameters of the machine learning model comprise input parameters, each of the quantum logic circuits comprises a first unitary transformation, and translating the subset of the parameters of the machine learning model to the quantum logic gate parameters comprises: translating a first subset of the input parameters of the machine learning model to a first subset of the quantum logic gate parameters of the first unitary transformation. (Havlicek, [Pp. 2-3] “We define a feature map on n-qubits generated by the unitary UΦ(x) = UΦ(x) H⊗nUΦ(x)H⊗n, where H denotes the conventional Hadamard gate and is a diagonal gate in the Pauli Z-basis, c.f. Fig1(b). We use the coefficients φS(x)∈R, to encode the data x∈Ω. ... We use the map for n=d=2-qubitsinFig.1(b) with φ{i}(x)=xi and φ{1,2}(x)=(π−x1)(π−x2)... The first classification protocol follows four steps. First, the data. x ∈ Ω is mapped to a quantum state by applying the feature map circuit UΦ(x) in Fig. 1(b) to a reference state
|
0
n
.” [Pp. 12-13] “In the quantum setting, the feature map is an injective encoding of classical information x ∈ Rd into a quantum state |Φ Φ| on an n-qubit register.”) [Examiner Note: the unitary UΦ(x) represents the first unitary transformation and the input vector x represents the input parameters, and the encoding process into a quantum state reads on the translation to quantum logic gate parameters (i.e., gate coefficients).]
Therefore, it would have been prima facie obvious to one of ordinary skill in the art, before the effective date of the claimed invention, having the combination of McKiernan, Satzinger, Broughton, and Havlicek to incorporate the supervised learning with quantum enhanced feature spaces as taught by Havlicek. One would have been motivated to make such a combination in order to find suitable feature maps for this technique with provable quantum advantages while providing significant improvement on real world data sets (Havlicek [Conclusion]).
Regarding Claim 7,
the combination of McKiernan, Satzinger, Broughton, and Havlicek teaches the elements of claim 6 as outlined above, and further teaches:
While the combination of McKiernan, Satzinger, and Broughton the parameters of the machine learning model comprise input parameters and model parameters and translating the subset of the parameters of the machine learning model to the quantum logic gate parameters. Broughton also teaches the TFQ framework used to define quantum neural networks as products of parameterized unitary matrices, and describes the unitaries that prepare each initial state and the unitaries representing the quantum circuit. The combination of McKiernan, Satzinger, and Broughton does not appear to explicitly teach:
translating a second subset of the model parameters to a second subset of the quantum logic gate parameters of the second unitary transformation.
However, Havlicek, in combination with McKiernan, Satzinger, and Broughton, teaches the limitations:
wherein the parameters of the machine learning model comprise model parameters, each of the quantum logic circuits comprises a second unitary transformation, and translating the subset of the parameters of the machine learning model to the quantum logic gate parameters comprises: translating a second subset of the model parameters to a second subset of the quantum logic gate parameters of the second unitary transformation. (Havlicek, [Pp. 2-3] “Second, a short depth quantum circuit W(θ), described in Fig 2(b) is applied to the feature state. A circuit with l- layers is parametrized by θ ∈ R2n(l+1) that will be optimized during training... Fig. 2, Here we choose a rather common Ansatz for the variational unitary W(θ) = U(l) loc(θl) Uent ...U(2) loc (θ2) Uent U(1) loc (θ1). We alternate layers of entangling gates... with full layers single qubit rotations...” [Pp. 11-12] “Recall that in our setting, we first take the data x ∈ Rd and map it to a quantum state |Φ(x) Φ(x)| ∈ S(H⊗n 2 ) on n-qubits, c.f. eqn. (22). Then we apply a variational circuit W(θ) to the initial state that depends on some variational parameters θ, c.f. eqn.” [P. 15, Quantum variational classification] “We apply a circuit of l repeated entanglers as depicted in Fig S3.b and interleave them with layers comprised of local single qubit rotations: (see Eqn 32) parametrized by θt ∈ R2n and θi,t ∈ R2.” [P. 8, Fig. S1] “FIG. S1. Quantum variational classification: The circuit takes a references state, |0n, applies the unitary UΦ(vecx) followed by the variational unitary W(θ) and applies a measurement in the Z-basis.” Further see Fig. S3) [Examiner Note: the unitary transformation W(θ) represents the second unitary transformation and the learnable parametrized
θ
∈
R
2
n
(
l
+
1
)
vectors represents the model parameters, and the encoding to gate rotation angles represents the translated quantum logic gate parameters.]
The same motivation that was utilized for combining McKiernan, Satzinger, Broughton, and Havlicek as set forth in claim 6 is equally applicable to claim 7.
Regarding Claim 8,
the combination of McKiernan, Satzinger, Broughton, and Havlicek teaches the elements of claim 7 as outlined above, and further teaches:
updating the model parameters of the machine learning model according to the activation parameters of the machine learning model; (Broughton, [P. 8, Section: II-D] “Quantum models are constructed using cirq.Circuit objects containing SymPy symbols, and can be attached to quantum data sources using the tfq.AddCircuit layer.... (6) Evaluate Gradients & Update Parameters: After evaluating the cost function, the free parameters in the pipeline is updated in a direction expected to decrease the cost. This is most commonly per formed via gradient descent. To support gradient de scent, TFQ exposes derivatives of quantum operations to the TensorFlow backpropagation machinery via the tfq.differentiators.Differentiator interface. This allows both the quantum and classical models’ parameters to be optimized against quantum data via hybrid quantum classical backpropagation.” [P. 18, Section: III-E] “The composition of functions from the input data to the output loss is then the sequentially composited function (L◦fpost◦fqnn◦fpre). This scenario is depicted in Fig. 12. Now, let us describe the process of backpropagation through this composition of functions. As is standard in backpropagation of gradients through feedforward networks, we begin with the loss function evaluated at the output units and work our way back through the several layers of functional composition of the network to get the gradients. The first step is to obtain the gradient of the loss function ∂L/∂yout and to use classical (regular) backpropagation of gradients to obtain the gradient of the loss with respect to the output of the QNN, i.e. we get ∂(L ◦ fpost)/∂h via the usual use of the chain rule for backpropagation.”)
calculating updated quantum logic gate parameters based on the updated model parameters of the machine learning model; (Broughton, [P. 8, Section: II-D] “the architecture of TensorFlow is optimized around backpropagation of errors for efficient updates of model parameters; one of the core contributions of TFQ is integration with TensorFlow’s backpropagation mechanism. TFQ implements this functionality with our differentiators module... Since there are many ways to calculate gradients of quantum circuits, TFQ provides the tfq.differentiators.Differentiator interface. Expectation and Our SampledExpectation layers rely on classes inheriting from this interface to specify how TensorFlow should compute their gradients.” [P. 19, Section: III-E] “Thus, by taking gradients of the expectation value of the backpropagated effective Hamiltonian, we can get the gradients of the loss function with respect to QNN parameters, thereby successfully backpropagating gradients through the QNN. Further backpropagation through the preceding function block fpre can be done using standard classical backpropagation by using this evaluated QNN gradient.” [p. 29, Section: V-B] “# Update model parameters and add # new 0 parameters for new layers. model.set_weights( [np.pad(weights, (n_qubits, 0))]) model.fit(x_train, y_train, batch_size=128, epochs=10, verbose=1, validation_data=(x_test, y_test))...”)
McKiernan, in combination with Satzinger and Broughton, further teaches:
updating the model parameters of the machine learning model according to the activation parameters of the machine learning model; (McKiernan, [0099]-[0100] “If the reward does not satisfy the “solved” criteria at 356, then at 358, the agent modifies the parameters of the neural network 312. The neural network is updated based on the “state” and “reward” data computed from the quantum processor output data at 354... Using the PPO algorithm in the process 300, an input vector (state, reward) that includes the “state” and “reward” data from the last n steps (where n is an integer greater than or equal to 1) is provided as input for updating the neural network 312. The input vector can be of length one (i.e., n=l), specifying the most recent (state, reward) pair, or it can be longer (n>l) and include a "memory" over the last several (state, reward) pairs. The input vector is used to compute a loss function, and derivatives of the loss function are taken with respect to each parameter of the neural network. The derivatives are used to update the parameters of the neural network, for example, according to an optimization technique such as stochastic gradient descent or otherwise.”) calculating updated quantum logic gate parameters based on the updated model parameters of the machine learning model; (McKiernan, [0102]-[0105] “After the parameters of the neural network 312 have been modified, the agent executes another iteration of the process 300. For example, each iteration of the iterative process may include: operating the updated neural network to produce neural network output data for the iteration based on the current “state” and “reward” information (at 350); selecting a quantum logic gate for the iteration based on the neural network output data (at 350); generating an updated version of the quantum program that includes the selected quantum logic gate for the iteration (at 350)... In the example shown in FIG. 5, at 350 the agent can choose from a set of quantum logic gates that includes one or more parametric gates. The parametric gates are quantum logic gates that are defined in terms of a variable parameter... As such, the updated version of the quantum program may be generated at 350 with a variable parameter (e.g., a variable rotation angle or another type of variable parameter).”) and determining updated control parameters based on the updated quantum logic gate parameters. (McKiernan, [0106]-[0107] “At 352A, the quantum program with unspecified values for one or more variable parameters is compiled by the compiler 318. In the example shown, the compiler 318 generates a patchable binary machine code, which is an example of a compiled quantum program in which definite values of the variable parameters have not yet been specified. At 352B, definite values of the variable parameters are selected, and the patchable binary machine code is patched to generate the full, compiled quantum program... At 362, the agent optimizes the variable parameters in the quantum program. For example, the agent may use the GPU 316 to determine an updated value for one or more variable parameters to improve performance of the quantum program. In some cases, the agent iterates an optimization loop (352B, 354, 362) to modify the value of the variable parameter until a terminating condition is reached... On each iteration of the internal optimization loop, the patchable binary machine code (from 352A) is patched based on new values for the variable parameters (from 362) to generate a new compiled version of the quantum program. The agent then obtains (at 354) additional quantum processor output data generated by the quantum resource 314 executing the new compiled version of a quantum program, and the agent the selects (at 362) new values for the variable parameters based on the additional quantum processor output data.”)
Claim(s) 28 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of McKiernan, Satzinger, and Broughton as outlined above and further in view of Neven et al., (Pub. No.: US 20200169396 A1).
Regarding Claim 28, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan, in combination with Satzinger and Broughton, teaches: wherein the QPU sublattices comprise first QPU sublattices, the hybrid computing system comprises second QPU sublattices, the quantum logic circuits are first quantum logic circuits configured according to parameters of nodes in a first layer of the machine learning model, (McKiernan, [0021] “The computing environment 101 shown in FIG. 1 includes a server 108, quantum processor units 103A, 103B and other computing resources 107. The computing environment 101 may also include one or more of the access nodes (e.g., the example access node HOA) and other features and components” [0038] “ a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment... the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel based on interactions with the controllers 106A.” [0108] “FIG. 6 is a flow diagram of another example process 600 for synthesizing quantum logic circuits. The example process 600 in FIG. 6 is similar to the example process 500 in FIG. 5, except that operation 358 is omitted and therefore the neural network 312 is not trained (or otherwise modified) by the process 600. Accordingly, the process 600 in FIG. 6 can be used to sample the neural network 312 after the neural network 312 has been trained (e.g., by the process 500 in FIG. 5 or otherwise). As shown in FIG. 6, if the reward does not satisfy the “solved” criteria at 356, then the agent provides the “state” and “reward” information to the neural network 312 for the next iteration or the process. Also shown in FIG. 6, the internal optimization loop (362, 352B, 354) is preserved so that the parameters of parametric gates can be optimized upon each iteration, as in the example process 500.” [0115] “The example QPU systems 810 each include dual 32-qubit quantum processor units (QPUs). A dual 32-qubit QPU includes two independently-operated QPUs in the same controlled environment (e.g., on the same chip, in the same cryostat, or in another type of shared environment). The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel.”)
Satzinger, in combination with McKiernan and Broughton, teaches: wherein the QPU sublattices comprise first QPU sublattices, the hybrid computing system comprises second QPU sublattices, the quantum logic circuits are first quantum logic circuits ... defining second quantum logic circuits to be executed on the second QPU sublattices, wherein each of the second quantum logic circuits is configured according to the updated input parameters (Satzinger, [0039] “The random quantum circuit generator 110 can also be configured to define random benchmarking quantum circuits based on defined initial quantum circuits. Each initial quantum circuit defined by the random quantum circuit generator 110 can be partitioned into multiple layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel. An example partitioning of an initial quantum circuit into multiple layers where instances of the two-qubit gate in each layer can be implemented in parallel is illustrated and described below with reference to FIG. 2A.” [0044] “Because of the specific construction of the benchmarking quantum circuits defined by the random quantum circuit generator 110, the quantum computing hardware 104 implements two-qubit gates in each layer of instances of the two-qubit gate in parallel.” [0052] “For example, layers 200 a-200 d each include a respective subset of the multiple instances of the two-qubit gate included in the example initial quantum circuit 200. Since each qubit in each layer 200 a-200 d is only operated on by one two-qubit gate, the two-qubit gates in each of the layers 200 a-200 d can be implemented in parallel.”) [Examiner’s Note: Satzinger teaches the initial quantum circuits consist of one or more quantum circuits that are being partitioned into multiple layers and executed in parallel. The adjusted control parameters for the next iteration/cycle reads on the updated input parameters.]
The combination of McKiernan, Satzinger, and Broughton may not appear to explicitly describe the multi-layer machine learning model in which each layer comprises logic gates based on layer-specific parameters and being updated/adjusted during training/processing. Specifically, the combination does not explicitly describe:
updating input parameters of nodes in a second layer of the machine learning model according to the activation parameters;... wherein each of the second quantum logic circuits is configured according to the updated input parameters of the nodes in the second layer of the machine learning model.
However, Neven, in combination with McKiernan, Satzinger, and Broughton, teaches the limitations:
the quantum logic circuits are first quantum logic circuits configured according to parameters of nodes in a first layer of the machine learning model, and the operations comprise: (Neven, [0008] “each intermediate quantum neural network layer comprises (i) single qubit quantum logic gates, (ii) two qubit quantum logic gates, or (iii) both single qubit and two qubit quantum logic gates.” [0056] “The quantum logic gates included in each intermediate quantum neural network layer may include single qubit quantum logic gates, two qubit quantum logic gates, or both single qubit and two qubit quantum logic gates. For example, in the example quantum neural network 100 the first intermediate quantum neural network layer 106 a includes multiple single qubit gates, e.g., single qubit gate 112, that operate on each of the plurality of qubits 110. The subsequent intermediate quantum neural network layers 106 b-108 e include two qubit gates, e.g., two qubit gate 118. In some implementations the single qubit quantum gates may include single qubit gates of the form exp(−iθjXj) where θj represents gate parameters ...” [0059] “The control devices 110 may further include hardware used for controlling the quantum logic gates that are applied to the plurality of qubits, e.g., hardware used to set or adjust the values of the quantum logic gate parameters. In some implementations the control devices may include microwave control devices.”) [Examiner’s Note: the first intermediate quantum neural network layer (i.e., first layer of the machine learning model) that includes quantum logic gates parameterized by gate parameter (i.e., first quantum logic circuits).] updating input parameters of nodes in a second layer of the machine learning model according to the activation parameters; (Neven, [0057] “The sequence of intermediate quantum neural network layers 106 a-106 e operate on the plurality of qubits 110, evolving a quantum state describing the plurality of qubits 110 to an evolved quantum state. The evolved quantum state encodes the solution to the machine learning task. More specifically, the sequence of quantum neural network layers 104, 106 a-106 e map the initial quantum state encoding the machine learning task data input 150 to an evolved state of the target qubit encoding the solution to the machine learning task.” [0064]-[0067] “The system then processes the machine learning task input using one or more intermediate quantum neural network layers (step 204 b). Each quantum neural network layer includes multiple quantum logic gates that operate on the multiple qubits and a target qubit that is also in the input quantum neural network layer. Processing the machine learning task input using one or more intermediate quantum neural network layers may therefore include, for each intermediate quantum neural network layer and in a sequence, applying quantum logic gates for the intermediate quantum neural network layer to a current quantum state representing the multiple qubits and the target qubit... the action of applying multiple intermediate quantum neural network layers to an input quantum neural network layer output is equivalent to evolving the initial state of qubits included in the input quantum neural network layer under a sequence of unitary operators that is parameterized by the quantum logic gate parameters for the quantum logic gates included in the multiple intermediate quantum neural network layers.... The system then adjusts values of the gate parameters from initial values to trained values (step 204 e).”) [Examiner’s Note: the iterative processing of quantum neural network layers where the output of the first layer becomes input to the next/second layer, the gate parameters across layers are adjusted based on the model parameters. This reads on the concept of updating input parameters of nodes in a second layer of the machine learning model according to the activation parameters.] defining second quantum logic circuits to be executed on the second QPU sublattices, wherein each of the second quantum logic circuits is configured according to the updated input parameters of the nodes in the second layer of the machine learning model. (Neven, [0056] “Each of the intermediate quantum neural network layers 106 a-106 e includes multiple quantum logic gates that operate on the plurality of qubits 110 (i.e., the multiple qubits prepared in the initial state encoding the machine learning task data input and the target qubit.) The quantum logic gates included in each intermediate quantum neural network layer may include single qubit quantum logic gates, two qubit quantum logic gates, or both single qubit and two qubit quantum logic gates. For example, in the example quantum neural network 100 the first intermediate quantum neural network layer 106 a includes multiple single qubit gates, e.g., single qubit gate 112, that operate on each of the plurality of qubits 110. The subsequent intermediate quantum neural network layers 106 b-108 e include two qubit gates, e.g., two qubit gate 118.” [0066]-[0067] “Therefore, only one gradient descent or other optimization routine needs to be performed to determine parameter adjustments for all the quantum logic gate parameters (i.e., parameter adjustments for all the intermediate quantum neural network layers) when performing an optimization on functions of the evolved quantum state. The system then adjusts values of the gate parameters from initial values to trained values (step 204 e).”) [Examiner’s Note: the subsequent intermediate layer (i.e., second layer of the machine learning model) which includes quantum logic gates being adjusted based on the parameter adjustment.]
Accordingly, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, having the combination of McKiernan, Satzinger, Broughton, and Neven to incorporate the method of using a quantum neural network trained to perform a machine learning task as taught by Neven. One would have been motivated to make such a combination in order to improve and reduce the computational costs and resources required when training and using the quantum neural network, i.e., compared to using just a quantum neural network (Neven [0044]).
Claim(s) 32 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of McKiernan, Satzinger, and Broughton as outlined above and further in view of Chong et al., (Pub. No.: US 20210334081 A1).
Regarding Claim 32, the combination of McKiernan, Satzinger, and Broughton teaches the elements of claim 17 as outlined above, and further teaches:
McKiernan, in combination with Satzinger and Broughton, teaches: wherein the hybrid computing system comprises a compiler unit, the quantum logic circuits are native quantum logic circuits, (McKiernan, [0030] “In some implementations, all or part of the computing environment 101 operates as a hybrid computing environment, and the server 108 operates as a host system for the hybrid environment. For example, the programs 112 can be formatted as hybrid computing programs, which include instructions for execution by one or more quantum processor units and instructions that can be executed by another type of computing resource.” [0114] “the hybrid blade 816 (e.g., the CPU included in the hybrid blade 816) may perform the operations of the compiler 318 and the neural network 312 in FIGS. 3, 4, 5, 6, and 7; the GPUs included in the hybrid blade 816 may perform the operations of the GPU 316 shown in FIGS. 3, 4, 5, 6, and 7;...”) and the operations comprise: receiving a user program at the compiler unit from a user device; (McKiernan, [0022] “As shown in FIG. 1, to access computing resources of the computing environment 101, the access nodes 110 send programs 112 to the server 108 and in response, the access nodes 110 receive data 114 from the server 108.” [0028] “the server 108 operates as a host system for the computing environment 101. For example, the access nodes 110 may send programs 112 to server 108 for execution in the computing environment 101. The server 108 can store the programs 112 in a program queue, generate one or more computing jobs for executing the programs 112, generate a schedule for the computing jobs, allocate computing resources in the computing environment 101 according to the schedule, and delegate the computing jobs to the allocated computing resources.”) and compiling, by operation of the compiler unit, the user program to generate the native quantum logic circuits for the respective QPU sublattices. (McKiernan, [0047] “the controllers 106A can interpret the quantum machine instructions and generate a hardware-specific control sequences configured to execute the operations proscribed by the quantum machine instructions.” [0106] “the quantum program with unspecified values for one or more variable parameters is compiled by the compiler 318. In the example shown, the compiler 318 generates a patchable binary machine code, which is an example of a compiled quantum program in which definite values of the variable parameters have not yet been specified.” [0118] “The hybrid blade 816 may then compile the current program, for example, into binary machine code (e.g., operation 352 in FIGS. 3, 4, 7) or into patchable binary machine code (e.g., operation 352A in FIGS. 5, 6) and then patch the patchable binary machine code (e.g., operation 352B in FIGS. 5, 6). The hybrid blade 816 may then dispatch the compiled program to multiple QPUs, collect the quantum processor output data from the QPUs, and process the QPU measurements (e.g., operation 354 in FIGS. 3, 4, 5, 6, 7).”)
McKiernan does not explicitly define the access node as user device or define the received program as user program. However, it would have been obvious in view of Chong. Hereinafter, Chong, in combination with McKiernan, Satzinger, and Broughton, teaches the limitations:
wherein the hybrid computing system comprises a compiler unit, the quantum logic circuits are native quantum logic circuits, and the operations comprise: (Chong, [0023] “The quantum computing system 100 includes a control computing device 110 that is configured to prepare (e.g., compile and optimize) a quantum program 112 for execution on the quantum computing device 130.” [0028] “the control computing device 110 includes a compilation engine 114 that, during operation, is configured to compile the quantum program 112 (e.g., from source code) into an optimized physical schedule 116.”)
receiving a user program at the compiler unit from a user device; and compiling, by operation of the compiler unit, the user program to generate the native quantum logic circuits for the respective QPU sublattices. (Chong, [0050] “The method comprises (i) receiving a quantum program from a user, the quantum program defining a plurality of instructions in a source language; (ii) compiling the quantum program into logical assembly instructions in an intermediate language; (iii) aggregating the logical assembly instructions together into a plurality of logical blocks of instructions; (iv) generating a logical schedule for the quantum program based on commutativity between the plurality of logical blocks; (v) generating a tentative physical schedule based on the logical schedule, the tentative physical schedule including a mapping of the logical assembly instructions in the logical schedule onto a plurality of qubits of a quantum processor; ...” [0020] “ the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor).” [0036] “The compilation engine 114 starts with the source code of the quantum program 112. The compilation engine 114 performs loop unrolling on the quantum program 112 (see operation 310), as described with respect to the loop unrolling module 212 of FIG. 2, as well as module flattening (see operation 312), as described with respect to the module flattening module 214 of FIG. 2. The compilation engine 114 then compiles the quantum program 112 into logical assembly 316 (operation 314).”)
Accordingly, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, having the combination of McKiernan, Satzinger, Broughton, and Chong, to incorporate the method for compiling instructions for a quantum computer as taught by Chong. One would have been motivated to make such a combination in order to be able to generate adequate optimization solutions for the subset of instructions; (B) addressing parallelism problems inherent in breaking up the logical operations into blocks; and (C) optimizing the logical operations based on the strengths and weaknesses of the underlying physical hardware (Chong [0029]).
Claim(s) 33 is rejected under 35 U.S.C. 103 as being unpatentable over McKiernan et al., (Pub. No.: WO 2020168158 A1) in view of Satzinger et al., (Pub. No.: US 20220358392 A1).
Regarding Claim 33,
McKiernan discloses the following:
A hybrid computing system comprising: (McKiernan, [0030] “all or part of the computing environment 101 operates as a hybrid computing environment, and the server 108 operates as a host system for the hybrid environment. For example, the programs 112 can be formatted as hybrid computing programs, which include instructions for execution by one or more quantum processor units and instructions that can be executed by another type of computing resource.”)
a quantum computing resource, the quantum computing resource comprising quantum processing unit (QPU) sublattices each comprising a subset of qubit devices, and a classical computing resource communicably coupled to the quantum computing resource; (McKiernan, [0026] “Each of the example quantum processor units 103A, 103B operates as a quantum computing resource in the computing environment 101. The other computing resources 107 may include additional quantum computing resources (e.g., quantum processor units, quantum virtual machines (QVMs) or quantum simulators)” [0038] “ a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment. For instance, the dual-QPU may include two independently-operated superconducting quantum processor circuits in the same cryogenic environment, on the same chip or substrate, or in another type of shared circuit environment. In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel based on interactions with the controllers 106A.”) and
means for operating a machine learning model in the hybrid computing system, wherein the means for operating the machine learning model executes quantum control programs on at least a subset of the respective QPU sublattices in parallel. (McKiernan, [0017] “neural networks are used to generate quantum programs. For instance, a training process can be used to train the neural network (e.g., using deep reinforcement learning or another type of machine learning process), and then the neural network can be sampled to construct quantum programs configured to generate solutions to specific problems.” [0087] “on each iteration, the agent selects a quantum logic gate from the set of allowable quantum logic gates and appends this quantum logic gate to the end of the current program (which specifies a quantum logic circuit). The set of allowable quantum logic gates may include any combination of parametric gates, non-parametric gates, single qubit gates, two-qubit gates, etc. The selection of the quantum logic gate on each iteration is determined by the agent’s policy, which is given by the classical neural network 312.” [] “ After the parameters of the neural network 312 have been modified, the agent executes another iteration of the process 300. For example, each iteration of the iterative process may include: operating the updated neural network to produce neural network output data for the iteration based on the current “state” and “reward” information (at 350); selecting a quantum logic gate for the iteration based on the neural network output data (at 350); generating an updated version of the quantum program that includes the selected quantum logic gate for the iteration (at 350); compiling the quantum program for the iteration (at 352); generating quantum processor output data for the iteration by executing the quantum program;” [0094] “ In some cases, the quantum resource 314 is a set of multiple QPUs or QVMs that run multiple instances of the quantum program (e.g., in parallel).” [0113]-[0115] “The hardware elements shown in FIG. 8 can be used, in some instances, to execute various operations of a quantum program synthesis process in parallel... The two independently-operated QPUs can be operated independently of each other, for example, to execute two instances of a quantum program in parallel.” Further see [0092], [0093], and [0115].)
While McKiernan teaches quantum computing architecture (QPU) that includes multiple quantum processor cells to operate qubit devices, McKiernan does not explicitly define quantum processing unit (QPU) sublattices each comprising a subset of qubit devices.
However, McKiernan in view of Satzinger teaches the limitation. Hereinafter, Satzinger, in combination with McKiernan, teaches:
a quantum computing resource, the quantum computing resource comprising quantum processing unit (QPU) sublattices each comprising a subset of qubit devices, and a classical computing resource communicably coupled to the quantum computing resource; (Satzinger, [0031] “The system 100 includes a classical processor 102 in data communication with quantum computing hardware 104. For convenience, the classical processor 102 and quantum computing hardware 104 are illustrated as separate entities, however in some implementations the classical processor 102 can be included in quantum computing hardware 104, e.g., the quantum computing hardware 104 can include one or more components for performing classical computing operations.”)
operating the machine learning model executes quantum control programs on at least a subset of the respective QPU sublattices in parallel. (Satzinger, [0032] “The quantum computing hardware 104 includes components for performing quantum computations using quantum circuits. For example, the quantum computing hardware 104 includes a quantum system 120 and control devices 122.” [0039] “The random quantum circuit generator 110 can also be configured to define random benchmarking quantum circuits based on defined initial quantum circuits. Each initial quantum circuit defined by the random quantum circuit generator 110 can be partitioned into multiple layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel. An example partitioning of an initial quantum circuit into multiple layers where instances of the two-qubit gate in each layer can be implemented in parallel is illustrated and described below with reference to FIG. 2A.” [0051]-[0052] “FIG. 2A illustrates an example partitioning of an initial quantum circuit 200 into multiple layers 200 a-200 d that can be implemented in parallel. The example initial quantum circuit 200 operates on a square array of qubits, e.g., qubit 202 (though it will be appreciated that other array shapes may alternatively be used). The example initial quantum circuit 200 includes multiple instances of a two-qubit gate that is configured to operate on nearest-neighboring pairs of qubits, e.g., two-qubit gate 204. Each neighboring pair of qubits in the square array is operated on by a respective two-qubit gate... The example initial quantum circuit 200 can be partitioned into multiple layers of instances of the two-qubit gate, in this example four layers, where instances of the two-qubit gate in a respective layer can be implemented in parallel.”)
McKiernan and Satzinger are from the same field of endeavor and their disclosure generally relates to (quantum computing).
Accordingly, at the effective filing date, it would have been prima facie obvious to one ordinarily skill in the art to modify the combination of McKiernan and Satzinger to incorporate the method for benchmarking quantum computing hardware as taught by Satzinger. One would have been motivated to make such a combination in order to determine adjustments that may improve the accuracy of existing quantum computing hardware, e.g., improve the accuracy at which the quantum computing hardware performs quantum operations (Satzinger [0018]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
(Pub. No.: US 20210295198 A1) – “Ryan Babbush” relates to “Training quantum evolutions using sublogical controls.”
(Pub. No.: US 10922460 B1) – “Jae Young Lee” relates to “Apparatus and method for constructing parameterized quantum circuit.”
(Pub. No.: US 10949768 B1) – “William J. Zeng” relates to “Constructing quantum processes for quantum processors.”
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/S.A.A./Examiner, Art Unit 2121
/Li B. Zhen/Supervisory Patent Examiner, Art Unit 2121
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