DETAILED ACTION
This Office action is in response to the application/amendment filed on .
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant's arguments filed 26 January 2026 with respect to claims 1, 11 and 15 have been fully considered but they are not persuasive.
Applicant argues that claims 1, 11 and 15 have been amended to include “subject matters similar to those of claim previously-presented claim 2,” which the non-final Office action had indicated to be allowable (Remarks at p. 9). However, it is respectfully submitted that claim 2 was indicated to contain allowable subject matter encompassing the claim as a whole—that is, all of the limitations of claim 2, combined with all of the limitations of its parent claim 1.
Applicant has merely taken a subset of the limitations from claim 2 and inserted them into claims 1 and 15, while simultaneously broadening other aspects of each of these claims, thus presenting a scope that is significantly different than the previously-presented claim 2. Additionally, in the case of claim 11, the amendments made do not appear to track those of claim 2, contrary to Applicant’s assertions. Moreover, claim 11 has also been significantly broadened in the filed amendments. After consideration of the applied prior art and in view of the new scope of the claims, the previous rejections made in view of Lee (US 2016/0049864) have been maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11, as amended, recites, “responsive to the clamp enable input having a first state, set a clamp voltage to a first value, and clamp a voltage at the output terminal using the clamp voltage; and responsive to the clamp enable input having a first state, removing the clamping of the voltage at the output terminal by ramping the clamp voltage” (emphasis for clarity) at lines 6-10. That is, the claim apparently requires that the control circuitry perform two distinct, and seemingly opposing, actions responsive to the same condition of the clamp enable input having the first state.
It is not clear how the control circuitry can both clamp the voltage at the output terminal and remove said clamping responsive to the same condition. Further, it is not clear if the claim is referring to two different first states, or if the later instance should actually be “a second state”.
For purposes of examination, the last limitation of claim 11 is being interpreted as though it referred to a second state instead of a first state.
Claims 12-14 each depend, either directly or indirectly, from claim 11 and thus inherit the above deficiency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-8, 11 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2016/0049864).
In re claims 1, Lee discloses a circuit (Fig. 2) comprising:
an output terminal (output voltage of regulator circuit 200, at drain of unlabeled pass transistor);
a first transistor (unlabeled pass transistor) having a first terminal (source), a second terminal (drain), and a control terminal (gate), the second terminal of the first transistor coupled to the output terminal (as defined above); and
a second transistor (108) having a first terminal (source), a second terminal (drain), and a control terminal (gate), the first terminal of the second transistor coupled to the control terminal of the first transistor (at node OC);
a first switch (104 or 100) coupled between the control terminal of the second transistor (108) and a first voltage terminal (VDD: in the case where 104 is the first switch, it is coupled directly between gate of 108 and VDD; in the case where 100 is the first switch, it is coupled indirectly between gate of 108 and VDD, via 104);
a second switch (116) coupled between the control terminal of the second transistor (108) and a second voltage terminal (ground), the first and second switches each having a control terminal coupled to a clamp enable input (the clamp enable input may be voltage V1 at node O1, with gate of 104 coupled directly thereto, while gate of 116 coupled indirectly via elements 100 and 110); and
a capacitor (106) coupled to the control terminal of the second transistor (108);
In re claims 5-8, Lee discloses a resistor (118) having a first terminal (top) and second terminal (bottom), the first terminal of the resistor coupled to the output terminal (through 108);
a third transistor (104) having a first terminal (source/drain at V2), a second terminal (source/drain at VDD), and a control terminal (gate), the first terminal of the third transistor coupled to the output terminal (through 108);
an enable controller (100, 110, 112, 102) having a first terminal (gate of 100) and a second terminal (at V1), the second terminal of the enable controller coupled to the control terminal of the third transistor (at V1);
wherein the enable controller is configured to:
receive a control signal (101) at its first terminal (gate of 100) indicating whether power supply for the circuit is ready or not ([0017]-[0018]: 101 represents activation pulses to start up the power supply 200; thus it is considered to indicate that the power supply 200’s power supply, VDD, is ready to start up the power supply 200); and
provide an enable signal (V1) at its second terminal responsive to the control signal indicating the power supply for the circuit is ready ([0017], [0019]); and
an operational amplifier (202) having a first terminal (either input of 202), a second terminal (other input of 202), and a third terminal (output of 202), the third terminal of the operational amplifier coupled to the control terminal of the first transistor (Fig. 2).
In re claim 11, Lee discloses a circuit (Fig. 2) comprising:
an output terminal (OC);
control circuitry (rest of Fig. 2) coupled to the output terminal, the control circuitry including a transistor (unlabeled pass transistor) and a clamp circuit (1), the transistor having a control terminal (gate, at node OA=node OC), and the control circuitry having a clamp enable input (voltage V1 on node O1) and configurable to:
responsive to the clamp enable input having a first state (zero), set a clamp voltage to a first value ([0024]: during an initial state, clamp voltage V2 at node O2 is kept in a low state by transistor 116), and clamp a voltage at the output terminal using the clamp voltage [0026]: voltage Voc at output terminal OC is clamped at V2+Vth or less); and
responsive to the clamp enable input having a [second] state (a value above zero, when it increases in a step-wise manner per [0028]), removing the clamping of the voltage at the output terminal by ramping the clamp voltage ([0028] and Fig. 3: as V1 increases step-wise, clamp voltage V2 ramps gradually and output terminal Voc is able to rise as the clamping is removed).
In re claim 14, Lee discloses wherein the transistor is a first transistor (unlabeled pass transistor) and the control circuitry includes:
a second transistor (108) having a first terminal (source), a second terminal (drain), and a control terminal (gate), the first terminal of the second transistor coupled to the control terminal of the first transistor (node OC = node OA); and
a capacitor (106) having a first terminal and a second terminal, the first terminal (top) of the capacitor coupled to the control terminal of the second transistor (node O2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Zhao et al. (US 2017/0271972; “Zhou”).
In re claim 4, Lee discloses wherein the first switch, and the second switch are a n-channel metal-oxide semiconductor (NMOS) transistor (Fig. 2: 104 and 116 are NMOS), and the second transistor is a p-channel metal-oxide semiconductor (PMOS) transistor (Fig. 2: 108 is PMOS). Lee does not disclose that the first transistor (pass transistor in regulator 200) is NMOS.
However, Lee teaches that, “the low-dropout (LDO) regulator 200 can be implemented in various circuit topologies known by those skilled in the art and is not limited by the configuration illustrated in FIG. 2”. Moreover, an LDO regulator using an NMOS pass device was a known topology of linear regulators, as indicated by Zhou (Fig. 2). Zhou teaches a linear regulator with an NMOS pass device (211 in Fig. 2) and teaches that the NMOS may be selected over PMOS because control of a PMOS device becomes difficult at lower input voltages ([0002]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Lee by using an NMOS pass device in the linear regulator as shown by Zhou in order to improve performance at low input voltages.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2016/0049864) in view of Abesingha et al. (US 2023/0163676; “Abesingha”).
In re claim 15, Lee discloses the system comprising a DC/DC converter (see Fig. 2 and [0033] teaching generic buck, boost, or charge pump applications) having an output terminal and including the first transistor, the second transistor, the first switch, the second switch, the clamp enable input and the capacitor, all of which have been cited above in this Office action with respect to the identical limitations found in claim 1. However, Lee does not disclose that the converter is a multiphase DC/DC converter.
Whereas Abesingha demonstrates the use of various startup or initialization control circuits in a multiphase DC/DC converter (see examples of Figs. 1-3, 6-12; see also [0027]-[0028] teaching multiphase DC-DC embodiments and [0031],[0089] teaching various startup control functionality) for their well-known purposes including protecting the multiphase DC/DC converter from various fault conditions (as taught by Abesingha as cited above as well as by Lee for similar circuitry as explained above in this Office action).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used a clamping circuit such as that of Lee in a multiphase DC/DC converter, as such use is at least implied by Lee at [0033] in a generic DC-DC converter circuit such as buck or boost, and further because this would have merely entailed the use of known devices (soft-start clamping circuits with fault protection functionality) in a conventional manner for their intended purpose, such as system initialization and protection from faults, as further demonstrated by Abesingha as cited above.
In re claim 19, Abesignha further teaches the implementation in a system having first and additional multiphase DC/DC converters (see [0002], [0030], [0033]: the embodiments may be used as modular components together in a package or implemented in distribution systems for multiple loads such as data centers, etc.). It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention, considering the combination of teachings of the two references as presented above, to implement the additional multiphase DC/DC converters to have the same or similar features, with the result that they would likewise include the limitations recited in claim 19. This would enable the same beneficial functionality, explained above with respect to claim 15, for all of the multiphase DC/DC converters as for the first.
Allowable Subject Matter
Claims 2, 9-10, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the closest prior art in Lee discloses the invention of claim 1, but does not further disclose a current source coupled between the first voltage terminal and the first switch, and an inverter coupled between the clamp enable input and the control terminal of the first switch as recited in claim 2. The additional prior art on record does not suggest a modification to Lee that would arrive at the claimed solution.
With respect to claim 9, the closest prior art in Lee discloses the invention of claims 1 and 5-8, but does not further disclose wherein the operational amplifier and the first transistor are configured to control a temperature sense signal at the output terminal when the output terminal is enabled as recited in claim 9. The additional prior art on record does not suggest a modification to Lee that would arrive at the claimed solution.
With respect to claim 10, the closest prior art in Lee discloses the invention of claim 1, but does not further disclose wherein the output terminal, the first transistor, and the clamp circuit are components of a multiphase direct-current to direct-current (DC/DC) converter, the multiphase DC/DC converter configured to: provide a first voltage level below a first threshold at the output terminal if the output terminal is not enabled; provide a second voltage level above a second threshold at the output terminal if the output terminal is enabled and there is an overcurrent condition; and provide a third voltage level between the first threshold and the second threshold at the output terminal if the output terminal is enabled and there is not an overcurrent condition, the third voltage level indicating a temperature. as recited in claim 10. The additional prior art on record does not suggest a modification to Lee that would arrive at the claimed solution.
With respect to claim 12, the closest prior art in Lee discloses the invention of claim 11 as it is best understood, but does not further disclose wherein the transistor and the control circuitry are configurable to: provide a first voltage level below a first threshold at the output terminal if the output terminal is not enabled; provide a second voltage level above a second threshold at the output terminal if the output terminal is enabled and there is an overcurrent condition; and provide a third voltage level between the first threshold and the second threshold at the output terminal if the output terminal is enabled and there is not an overcurrent condition as recited in claim 12. The additional prior art on record does not suggest a modification to Lee that would arrive at the claimed solution.
Claim 13 depends from claim 12 and thus would be allowable for the same reasons.
Claim 16 recites substantially similar limitations as, and is similar in scope to, claim 2. Thus, claim 16 would be allowable for substantially the same reasons as provided above, mutatis mutandis.
Claims 17-18 depend from claim 16 and thus would be allowable for the same reasons.
With respect to claim 20, the closest prior art in Lee as combined with Abesingha discloses the invention of claims 15 and 19, but does not further disclose a controller having a sense terminal coupled to the respective output terminal of the first multiphase DC/DC converter and of each of the additional multiphase DC/DC converters, wherein the controller is configured to: interpret a voltage level below a first threshold at its sense terminal for less than a threshold amount of time as an indication of at least one of the respective output terminals not being enabled; interpret a voltage level below the first threshold at its sense terminal for more than the threshold amount of time as an indication of a power supply error; interpret a voltage level above a second threshold at its sense terminal as an overcurrent condition of at least one of the first multiphase DC/DC converter and each of the additional multiphase DC/DC converters; and interpret a voltage level between the first threshold and the second threshold at its sense terminal as a highest temperature sense signal of the first multiphase DC/DC converter and the additional multiphase DC/DC converters. as recited in claim 20. The additional prior art on record does not suggest a modification to Lee that would arrive at the claimed solution.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838