DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed on 10/01/2025 with respect to the amendments of claims 1 and 20 have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Otsubo et al (USPN 2020/0303338) and Hwang et al (USPN 2016/0141594).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-5, 14-18, 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Otsubo et al (USPN 2020/0303338).
Regarding claim 1, Otsubo discloses an integrated circuit (a chip package shown in figure 1) comprising:
an internal circuit (such as a semiconductor element 3, see par. 0017);
a contact pad (a contact pad shown in figure 1); and
a protective element (a fusible link 7) coupled between the internal circuit (3) and the contact pad (the contact pad shown in figure 1);
the protective element (7) being operable in a first state or a second state (close state and a melt open state); wherein:
the internal circuit (3), the contact pad, and the protective element (7) are integrated in a package (a package 10, see figure 1);
a first end of the protective element (7) is coupled to the contact pad, a second end of the protective element is coupled to the internal circuit (3); and
in the first state (the closed state) the protective element (7) is configured to pass a current between the internal circuit (3) and the contact pad, and wherein when the current is above a threshold value the protective element (the fusible link 7) is configured to change from the first state to the second state (the melt open state) to reduce or prevent the current from flowing between the internal circuit (3) and the contact pad (e.g. see par. 0026-0027).
Regarding claim 2, Otsubo discloses wherein in the first state the protective element has a low impedance (the close state of the fusible link 7) to allow current flow.
Regarding claim 3, Otsubo discloses wherein in the second state the protective element has a high impedance (the melt open state of the fusible link 7) to reduce or prevent current flow (see par. 0026-0027).
Regarding claim 4, Otsubo discloses wherein the protective element (7) is a fusible link (e.g. par. 0027).
Regarding claim 5, Otsubo discloses wherein the protective element (7) comprises a resistor configured to change its impedance upon temperature change (the protective element 7 functions as a resistor, see par. 0022-0023, 0026).
Regarding claims 14-15, Otsubo discloses wherein the protective element (7) comprises a plurality of resistors (the protective element 7 includes a plurality of resistors are coupled in parallel (see par. 1, par. 0022-0023).
Regarding claims 16-17, Otsubo discloses a connector (bonding wire 8) connecting the contact pad to a package pin (5) of the package (10, see figure 1).
Regarding claim 18, Otsubo discloses a system comprising an integrated circuit (figure 1) coupled to an external circuit (see par. 0018).
Regarding claim 20, Otsubo discloses a method for protecting an external circuit coupled to an integrated circuit (see par. 0018) having an internal circuit (an internal circuit 3) and a contact pad (a contact pad shown in figure 1), the method comprising:
providing the integrated circuit with a protective element (protective element 7) coupled between the internal circuit (3) and the contact pad, the protective element being operable in a first state or a second state (a closed state and a melt open state),
wherein: the internal circuit (3), the contact pad and the protective element (7) are integrated in a package (a package 10, see figure 1);
a first end of the protective element (7) is coupled to the contact pad, a second end of the protective element is coupled to the internal circuit (3); and
wherein in the first state (the closed state of the protective element 7), the method further comprises passing, by the protective element, is configured to pass a current between the internal circuit (7) and the contact pad, and wherein when the current is above a threshold value, the method further comprises changing, by the protective element, is configured to change from the first state to the second state to reduce or prevent the current from flowing between the internal circuit and the contact pad (see par. 0026-0027).
4. Claims 1-3, 5-7, 12, 18-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hwang et al (USPN 2016/0141594).
Regarding claim 1, Hwang discloses an integrated circuit (a chip package 300, figure 5) comprising:
an internal circuit (such as a chip 100);
a contact pad (a contact pad 51); and
a protective element (a PTC resistor 350) coupled between the internal circuit (the chip 100) and the contact pad (the pad 51),
the protective element (the PTC resistor) being operable in a first state or a second state (a low resistance state and a high resistance state) (see par. 0075); wherein:
the internal circuit (the chip 100), the contact pad (51), and the protective element (350) are integrated in a package (a package 300, see figure 5);
a first end of the protective element (350) is coupled to the contact pad (51), a second end of the protective element (350) is coupled to the internal circuit (the chip 100); and
in the first state (the low resistance state) the protective element (350) is configured to pass a current between the internal circuit (the chip 100) and the contact pad (the pad 51), and wherein when the current is above a threshold value the protective element (an overcurrent occurs) is configured to change from the first state to the second state (the high resistance state) to reduce or prevent the current from flowing between the internal circuit (the chip 100) and the contact pad (the pad 51)( e.g. see par. 0075).
Regarding claim 2, Hwang discloses wherein in the first state the protective element has a low impedance (the low resistance state of the PTC resistor 350) to allow current flow.
Regarding claim 3, Hwang discloses wherein in the second state the protective element has a high impedance (the high resistance state of the PTC resistor 350) to reduce or prevent current flow (see par. 0075).
Regarding claim 5, Hwang discloses wherein the protective element (the PTC resistor 350) comprises a resistor (the PTC resistor 350) configured to change its impedance upon temperature change (see par. 0075).
Regarding claim 6, Hwang discloses wherein the resistor (350) comprises a single layer having a single resistance (the PTC resistor 350 includes a single layer crystalline polymer layer, see figure 5) (see par. 0075).
Regarding claim 7, Hwang discloses wherein when the current is above the threshold value (the over-current occurs), the single layer liquifies (the crystalline polymer layer liquifies by heating), hence increasing the impedance of the resistor (see par. 0075).
Regarding claim 12, Hwang discloses wherein the resistor (the PTC resistor 350) has a geometry (a geometry of a crystalline polymer) which defines the impedance of the protective element in at least one of the first state and second state (see par. 0075).
Regarding claims 18-19, Hwang discloses a system (a system shown in figure 1) comprising an integrated circuit (100) coupled to an external circuit (battery cell 700, see figure 12), wherein the external circuit comprises a battery cell circuit (700) and wherein the system (the system in figure 1) forms a battery management system.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo et al (USPN 2020/0303338) in view of Bohr et al (USPN 5708291).
Regarding claims 8, 9, 10, 11, Otsubo discloses the protective element (7) includes a resistor (see par. 0022-0023), but does not explicitly disclose the resistor as claimed.
Bohr discloses a silicide fuse device (see figure 1A) comprises a resistor (100) comprises a first layer (a silicide layer 104) having a first resistance and a second layer (a polysilicon layer 105) having a second resistance, the first resistance being lower than the second resistance (the resistance of the silicide layer 104 is lower than the resistance of the polysilicon layer 105) (see col. 4, lines 41-42),
wherein when the current is above the threshold value, the first layer (the silicide layer 104) liquifies (heat up), hence increasing the impedance of the resistor (100),
wherein the resistor is a silicide polysilicon resistor in which the first layer is a silicide layer (104), and the second layer is a polysilicon layer (P-doped polysilicon layer 105) (see figure 1A).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the resistor of Otsubo to incorporate a resistor as disclosed by Bohr in order to lower sheet resistance so that improving a resistor performance.
6. Claims 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo et al (USPN 2020/0303338) in view of Mallikarjunaswamy (USPN 9,355,971).
Regarding claims 12, 13, Otsubo discloses all limitations of claim 1 as discussed above, but does not explicitly disclose the protective element comprises a resistor as claimed.
Mallikarjunaswamy discloses a protection device (see figures 2, 6-7) comprises a protective element (50) comprises a resistor (64)(see figure 2, 6), wherein the resistor (64) has a geometry (a geometry shown in figure 6) which defines the impedance of the protective element in at least one of the first state and second state (closed state and open state) (see col. 7, lines 12-27, col. 8, lines 17-36), wherein the resistor (64) extends between a first end and second end and has a plurality of contact points (62, 63) at the first end and second end, wherein the protective element comprises a plurality of resistors (the fuse structure 50 forms multiple parallel fuse paths, each fuse path including a fuse structure in figure 6, see col. 8, lines 13-16).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the protective element of Otsubo to incorporate a resistor as disclosed by Mallikarjunaswamy in order to facilitate a heat transfer to the fuse element so that aiding in a melting and breaking the fuse during an overcurrent event.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/Primary Examiner, Art Unit 2838