DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on October 27, 2023.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 10/27/2023 and 10/24/2025 have been considered by the examiner.
Drawings
4. The drawings were received on October 27, 2023. These drawings are accepted.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-2, 9, and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2020/0021227).
Regarding claim 1, Lee et al discloses a circuit (i.e. circuits of Figure 1 and 2) comprising:
a battery monitoring circuit (Fig. 1, circuit of DC link capacitor 20 and voltage detector across DC link capacitor 20) configured to monitor a positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and a negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) with respect to a neutral node (i.e. neutral node of energy storage device 10 of Figure 1);
an inverter (Figs. 1 and 2, inverter 30) configured to provide a plurality of modulated phase voltages (Fig. 1, signals S1-S6 outputted from controller 100) representing a reference voltage vector (See ¶[0061] and Abstract); and
a space vector modulator (Fig. 1, controller 100) configured to generate modulated drive signals (Fig. 1, signals S1-S6) for the inverter (Figs. 1 and 2, inverter 30) based on the reference voltage vector (See ¶[0061] and Abstract), wherein duty cycles of the modulated drive signals (Fig. 1, signals S1-S6 outputted from controller 100) depend on the monitored positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the monitored negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) (See ¶[0043] and ¶[0057]).
Regarding claim 2, Lee et al further discloses a first battery (Fig. 1, bottom battery of energy storage device 10) and a second battery (Fig. 1, top battery of energy storage device 10) connected to the neutral node (i.e. neutral node of energy storage device 10 of Figure 1) and configured to provide the positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10).
Regarding claim 9, Lee et al discloses a method comprising:
monitoring a positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and a negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) of an inverter (Figs. 1 and 2, inverter 30) with respect to a neutral node (i.e. neutral node of energy storage device 10 of Figure 1);
generating, by a space vector modulator (Fig. 1, controller 100), modulated drive signals (Fig. 1, signals S1-S6) for the inverter (Figs. 1 and 2, inverter 30) based on a reference voltage vector (See ¶[0061] and Abstract), wherein duty cycles of the modulated drive signals (Fig. 1, signals S1-S6 outputted from controller 100) depend on the monitored positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the monitored negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10); and
providing the modulated drive signals (Fig. 1, signals S1-S6 outputted from controller 100) to the inverter (Figs. 1 and 2, inverter 30), wherein the inverter (Figs. 1 and 2, inverter 30) is configured to provide a plurality of modulated phase voltages (Figs. 1 and 2, signals outputted from inverter 30) representing the reference voltage vector (See ¶[0061] and Abstract) in response to the modulated drive signals (Fig. 1, signals S1-S6 outputted from controller 100).
Regarding claim 11, Lee et al further discloses providing the positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) by a first battery (Fig. 1, top battery of energy storage device 10) connected to the neutral node (i.e. neutral node of energy storage device 10 of Figure 1); and
providing the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) by a second battery (Fig. 1, bottom battery of energy storage device 10) connected to the neutral node (i.e. neutral node of energy storage device 10 of Figure 1).
Regarding claim 12, Lee et al discloses a three-level inverter system (i.e. circuits of Figure 1 and 2) comprising:
a first power supply (Fig. 1, top battery of energy storage device 10) connected to a neutral node (i.e. neutral node of energy storage device 10 of Figure 1) and configured to supply a positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10);
a second power supply (Fig. 1, bottom battery of energy storage device 10) connected to the neutral node (i.e. neutral node of energy storage device 10 of Figure 1) and configured to supply a negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10);
a battery monitoring circuit (Fig. 1, circuit of DC link capacitor 20 and voltage detector across DC link capacitor 20) configured to monitor the positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10);
an inverter (Figs. 1 and 2, inverter 30) supplied by the positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10); and
a space vector modulator (Fig. 1, controller 100) configured to generate modulated drive signals (Fig. 1, signals S1-S6) for the inverter (Figs. 1 and 2, inverter 30) based on the monitored positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) (See ¶[0043] and ¶[0057]), wherein the generated modulated drive signals (Fig. 1, signals S1-S6 outputted from controller 100) are configured to cause the positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10) to remain substantially balanced (See ¶[0039] and ¶[0053]).
Regarding claim 13, Lee et al further discloses wherein
the inverter (Figs. 1 and 2, inverter 30) is configured to provide a plurality of modulated phase voltages (Figs. 1 and 2, signals outputted from inverter 30) representing a reference voltage vector (See ¶[0061] and Abstract);
the space vector modulator (Fig. 1, controller 100) is configured to generate the modulated drive signals (Figs. 1 and 2, signals outputted from inverter 30) for the inverter (Figs. 1 and 2, inverter 30) based on the reference voltage vector (See ¶[0061] and Abstract); and
duty cycles of the modulated drive signals (Figs. 1 and 2, signals outputted from inverter 30) depend on the monitored positive supply voltage (Fig. 1, positive supply voltage from energy storage device 10) and the monitored negative supply voltage (Fig. 1, negative supply voltage from energy storage device 10).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 3-4, 10, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0021227) in view of Wang et al (US 2018/0062537).
Regarding claim 3, Lee et al discloses an inverter (Figs. 1 and 2, inverter 30).
Lee et al fails to explicitly disclose wherein the inverter is an active-neutral-point-clamped (ANPC) multi-level converter.
However, Wang et al discloses wherein an inverter (i.e. inverter of Figure 15B) is an active-neutral-point-clamped (ANPC) multi-level converter (See ¶[0187]).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lee et al, by including the inverter of Wang et al, in order to obtain an inverter with improved voltage balancing and efficiency.
Regarding claim 4, Lee et al fails to disclose wherein: the ANPC multi-level converter includes three phases, each phase of the three phases being coupled between a first supply node and a second supply node and configured to receive a DC supply voltage corresponding to a difference between the positive supply voltage and the negative supply voltage, and each phase of the three phases is configured to provide a respective one of the three phase voltages by outputting either the positive supply voltage, the negative supply voltage or a neutral point voltage dependent on a switching state of the ANPC multi-level converter.
However, Wang et al discloses wherein: an ANPC multi-level converter (i.e. inverter of Figure 15B) includes three phases (i.e. phases A, B, and C) (See ¶[0187]), each phase of the three phases (i.e. phases A, B, and C) being coupled between a first supply node (Fig. 15B, node P) and a second supply node (Fig. 15B, node N) and configured to receive a DC supply voltage (Fig. 15B, voltage outputted from Vdc) corresponding to a difference between the positive supply voltage and the negative supply voltage, and each phase of the three phases (i.e. phases A, B, and C) is configured to provide a respective one of the three phase voltages by outputting either the positive supply voltage, the negative supply voltage or a neutral point voltage dependent on a switching state of the ANPC multi-level converter (See ¶[0187]-¶[0193]).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lee et al, by including the inverter of Wang et al, in order to obtain an inverter with improved voltage balancing and efficiency.
Regarding claim 10, Lee et al discloses an inverter (Figs. 1 and 2, inverter 30).
Lee et al fails to explicitly disclose wherein the inverter is an active-neutral-point-clamped (ANPC) multi-level converter.
However, Wang et al discloses wherein an inverter (i.e. inverter of Figure 15B) is an active-neutral-point-clamped (ANPC) multi-level converter (See ¶[0187]).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of Lee et al, by including the inverter of Wang et al, in order to obtain an inverter with improved voltage balancing and efficiency.
Regarding claim 14, Lee et al discloses an inverter (Figs. 1 and 2, inverter 30).
Lee et al fails to explicitly disclose wherein the inverter is an active-neutral-point-clamped (ANPC) multi-level converter.
However, Wang et al discloses wherein an inverter (i.e. inverter of Figure 15B) is an active-neutral-point-clamped (ANPC) multi-level converter (See ¶[0187]).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lee et al, by including the inverter of Wang et al, in order to obtain an inverter with improved voltage balancing and efficiency.
Regarding claim 15, Lee et al fails to disclose wherein: the ANPC three-level converter includes three phases, each phase of the three phases being coupled between a first supply node and a second supply node and configured to receive a DC supply voltage corresponding to a difference between the positive supply voltage and the negative supply voltage, and each phase of the three phases is configured to provide a respective one of the three phase voltages by outputting either the positive supply voltage, the negative supply voltage or a neutral point voltage dependent on a switching state of the ANPC three-level converter.
However, Wang et al discloses wherein: an ANPC three-level converter (i.e. inverter of Figure 15B) includes three phases (i.e. phases A, B, and C) (See ¶[0187]), each phase of the three phases (i.e. phases A, B, and C) being coupled between a first supply node (Fig. 15B, node P) and a second supply node (Fig. 15B, node N) and configured to receive a DC supply voltage (Fig. 15B, voltage outputted from Vdc) corresponding to a difference between the positive supply voltage and the negative supply voltage, and each phase of the three phases (i.e. phases A, B, and C) is configured to provide a respective one of the three phase voltages by outputting either the positive supply voltage, the negative supply voltage or a neutral point voltage dependent on a switching state of the ANPC three-level converter (See ¶[0187]-¶[0193]).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lee et al, by including the inverter of Wang et al, in order to obtain an inverter with improved voltage balancing and efficiency.
Allowable Subject Matter
9. Claims 5-8 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art fails to disclose or suggest the emboldened and italicized features below:
A circuit,
wherein the space vector modulator is configured to generate the modulated drive signals such that the inverter runs through a selectable modulation sequence of switching states within one cycle period, and the selectable modulation sequence is configured to be selected based on the reference voltage vector.
Regarding claim 16, the prior art fails to disclose or suggest the emboldened and italicized features below:
A three-level inverter system, wherein
the space vector modulator is configured to generate the modulated drive signals such that the inverter runs through a selectable modulation sequence of switching states within one cycle period, and
the selectable modulation sequence is configured to be selected based on the reference voltage vector.
Regarding claim 17, the prior art fails to disclose or suggest the emboldened and italicized features below:
A three-level inverter system, wherein
the space vector modulator is configured to generate the modulated drive signals such that the inverter runs through a selected modulation sequence of switching states within one cycle period, and
the selected modulation sequence is configured to determined based on a reference voltage vector such that the positive supply voltage and the negative supply voltage remain substantially balanced.
Regarding claim 18, the prior art fails to disclose or suggest the emboldened and italicized features below:
A three-level inverter system, wherein
the space vector modulator is configured to generate the modulated drive signals such that, within one cycle period, each switching state of a selectable modulation sequence is active for a specific on-time;
the on-times of the switching states are configured to be determined based on duty cycles of the drive signals; and
the duty cycles of the drive signals depend on the monitored positive supply voltage and the monitored negative supply voltage.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tomigashi (US 7,898,197) deals with a motor control device, Hashimoto et al (US 2010/0060211) deals with an inverter control apparatus and motor drive system, Hashimoto et al (US 7,598,698) deals with a motor control device, and Tomigashi (US 2008/0061728) deals with a motor control device and current detecting unit.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY A NASH/Primary Examiner, Art Unit 2838