DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 10/15/2025.
Response to Arguments
Applicant’s arguments, see Remarks, filed on 10/15/2025, with respect to claims 1-8 have been fully considered and are persuasive. The 102 Rejections of claims 1-8 has been withdrawn, and now allowed.
Applicant's arguments filed on 10/15/2025, regarding claims 9-20, have been fully considered but they are not persuasive. Note that Applicant mainly argued regarding independent claims 9 & 15; wherein, the respective dependent claims were merely argued, simply for depending from claims 9 & 15. Therefore, going forward Examiner’s response will only be toward Applicant’s arguments, regarding independent claims.
Before proceeding to respond to the Applicant’s arguments, please see following Applicant’s annotated Fig. 2 (see, Applicant’s Spec., para 45-60) and Fig. 4 (see, Applicant’s Spec., para 69-88), provided for comparison purposes,
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Followings are related excerpt from Applicant’s own Description
[0021] Using a PMOS transistor as a pass device in a LDO voltage regulator (VR), results in high impedance (at an output of the LDO VR) or result in a dominant pole (being external to the LDO VR).
[0022] A LDO VR include first and second feedback circuits (140; Para 36). The first feedback circuit, include an amplifier (adjusting a voltage, i.e., using gate voltage of pass device, resulting adjustment on Vout ‘112 or 212’) and a feedback voltage provided to the amplifier.
[0023] the second feedback circuit 140, includes a voltage follower configuration, acting as a buffer between the amplifier and the pass device … to create a low impedance at the output of the pass device.
[0036-0039]140, facilitating a reduced impedance at node 112 by using a voltage follower of a MOSFET transistor (i.e., of a p-channel or an n-channel transistor), reducing the impedance, improving a transient performance of 100. 140, facilitating a dominant pole for 100, increasing stability in response to a load change. 140, buffering the circuit 150, from 112, allowing 150 to provide a dominant pole for VR 100 with respect to a frequency response of VR 100 and reduce an effect of a change of the load 120 with respect to the frequency response of the VR 100.
[0044] The first feedback circuit 130, adjusting the voltage 142 applied to the pass device 110 based on an output node 112 voltage. 140, reducing an impedance of the output node 112. 150 to increase a phase margin of 100. 130 include one or more of a first resistor, a second resistor, or an amplifier. 140, includes a voltage follower.
[0045] In FIG. 2 … The first feedback circuit 230a, 230b, to adjust the voltage applied to the pass device 210 based on an output node 212 voltage. The second feedback circuit 240, to adjust the voltage applied to the pass device based on a change to the output node 212 voltage.
[0052] 240, include one or more of the transistors 245, 246, 247, or the resistor 244. The transistor 246 is a voltage follower configuration with the drain 246c and the gate 246b of the transistor 246 directly coupled to the output node 212, reducing the impedance of the output node 212. Additionally, the transistor 246 and the transistor 247 may draw a current from the pass device 210 to maintain the pass device 210 in the saturation region.
[0053] The transistor 245 include a gate 245b coupled to 230a, 230b and a drain 245c coupled to 210. In these and other examples, the output voltage at the connection 236 of the amplifier 233 of the first feedback circuit 230a, 230b, provided to the gate 245b. The transistor 245, adjust the current passing through the transistor 245 and thereby adjust the PD-gate voltage provided to the pass device 210. As such, the second feedback circuit 240, adjust the pass device 210 based on an output of the first feedback circuit 230a, 230b. The transistor 246, acts as a current source .... The transistor 247 may be biased by a voltage, nbias.
[0054] The transistor 245 and the transistor 246 may be sized to have a conductance (e.g., gn) that may be adequate to decrease the impedance of the output node 212 to a value that provides for proper operation of the voltage regulator circuit 200.
Therefore, per above excerpt, it is evident that reduction of impedance is performed in 2nd FB circuit, using a voltage follower (i.e., 246) in a MOSFET configuration.
Additionally, note that Applicant includes a circuit ‘250 or 450’ to perform the improvement of PSRR bandwidth or a transient response of voltage regulator (VR); wherein, to one of ordinary skill in the art, it is common to know that to perform the improvement of PSRR bandwidth or a transient response of the VR, a compensation element is required (i.e., a capacitor or a capacitor-resistor element(s). In Applicant’s case, Applicant used capacitor 251 in Fig. 2 and capacitor 434 in Fig. 4). Furthermore, Applicant also used the compensation element being somehow arranged between 1st & 2nd FB circuits, in such a way that Vg of ‘210 or 410’ can be adjusted, resulting the improvement of PSRR bandwidth or a transient response of voltage regulator (i.e., at the output).
However, as far as input-output connection concerns in relationship to different operational elements or limitations, Applicant never claimed such limitations.
However, following two alternative operations are evident,
From Applicant’s above annotated Fig. 2, one evident example is that the circuit 250 includes a capacitor 252, coupled between 1st FB circuit 230a’s output, and 2nd FB circuit 240, in such a way that Vg of 210 is adjusted to improve PSRR performance of voltage regulator (VR).
From Applicant’s above annotated Fig. 4, another alternative evident example is that capacitor 434, coupled from 1st FB circuit 430a’s output, also couples to circuit 450 (which includes one or more current mirror config.), via 2nd FB circuit 440’s output, in such a way that Vg of 410 is adjusted to improve PSRR performance of VR.
Additionally, note that in claims 9 or 15, Applicant fails to claim the following limitation(s),
how “a voltage is applied to the pass device” (i.e., input/output connection configuration, let alone no detail of the operation or voltage);
how “a first feedback circuit” operable to “adjust a voltage output to the pass device” (i.e., input/output connection configuration, let alone no detail of the operation for voltage adjustment);
how “a second feedback circuit” included “first n- channel transistor and a second feedback circuit second n-channel transistor” relationship with the “pass device”, “first feedback circuit” (i.e., input/output connection configuration, let alone no detail of the operation for the purpose of the second feedback circuit, especially in claim 15);
how “a circuit” is operable “to increase a phase margin of the voltage regulator” in relationship with the “pass device”, “first feedback circuit” and “second feedback circuit” (i.e., input/output connection configuration, let alone no detail of the operation in relationship to other claimed elements, especially in claim 9); and
how “a circuit comprising one or more circuit transistors in a mirror configuration” used “to increase one or more of a power supply rejection ratio (PSRR) bandwidth or a transient response of the voltage regulator” in relationship with the “pass device”, “first feedback circuit” and “second feedback circuit” (i.e., input/output connection configuration, let alone no detail of the operation in relationship to other claimed elements, especially in claim 15).
Therefore, under broadest reasonable interpretations (BRI), as a voltage can be applied to any one of the input, output &/or control terminal of the pass device, wherein depending on where the voltage is applied, as long as there is a compensation element (i.e., filtering element like capacitor or a resistor-capacitor element) is used for or on the path of claimed same applied voltage of the pass transistor, then an anticipated configuration of performance for improving “phase margin” and/or “PSRR bandwidth or a transient response” of voltage regulator (i.e., at the output) is expected.
Next, Applicant’s first argument is as follows,
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However, respectfully the Examiner disagrees. As stated above, per Applicant's own description from above cited Spec., reduction of impedance is performed in 2nd FB circuit, using a voltage follower (i.e., 246) in a MOSFET configuration.
However, Applicant never claimed use of a voltage follower in claim 9.
However, note that Wang teaches, “a second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) operable to reduce an impedance (i.e., transistor M8’s drain is directly receiving Vout of PMOS pass. M7; wherein M8’s gate & drain is connected in a diode configuration & thus performing as a voltage follower to reduce impedance at the output node. Note that Wang’s M8 is same as Applicant’s claimed voltage follower Fig. 4: 246) of the output node (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220); and a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) operable to increase a phase margin (i.e., Fig. 4; PSRR plot; Col. 10 L62-Col. 11 L39) of the voltage regulator (LDO 300) (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO).
Applicant’s second arguments is as follows,
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However, respectfully Examiner disagrees. Based on above rationale, also please see Wang et al. (“Wang”, US Pat 11573585)’s following annotated Fig. 3 with two feedback paths,
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Also see, following Wang’s excerpts, related to PSRR teaching,
Wang’s Excerpt related to Wang’s taught 2nd FB circuit’s NMOS and PSRR improvements for LDO VR:
Col. 6 L16-41
With reference to FIG. 3, the operational amplifier 310 includes transistors M1-M2 …, are NMOS transistors, transistors M3-M4 …. are p-type metal oxide semiconductor transistors (PMOS transistor), and a transistor M5 … is an NMOS transistor…the operational amplifier 310 … to apply signal with low gain but a wide frequency bandwidth including a high frequency bandwidth. Therefore, the amplified signal outputted from the operational amplifier 310 corresponds to low frequency bandwidth that keeps sufficient low frequency high power supply rejection ratio (PSRR), which will be discussed below with reference to FIG. 4.
Col. 9 L44-48
With reference to FIG. 3, the current mirror unit 331 is implemented by including transistors M8-M9 and a resistor Rb, in some embodiments, the transistors M8-M9 are NMOS transistors. Alternatively stated, the transistors M8-M9 and the resistor Rb function as a current mirror.
Col. 11 L30-Col. 12 L44
With reference to FIG. 3, the compensation circuit 340 includes a resistor Rc and a capacitor Cc…coupled in series.
One terminal of the resistor Rc is coupled to the output terminal of the operational amplifier 310 (i.e., the node Vop), and the other one is coupled to the capacitor Cc. One terminal of the capacitor Cc is coupled to the resistor Rc, and the other one is coupled to the output terminal of the LDO regulator 300 (i.e., the output node Vout).
In some approaches, the LDO regulator only includes an operational amplifier and a pass element. The LDO regulator provides the specific voltage within a specific voltage dropout merely based on the signal generated from the power supply. the ripple signal is included in the signal generated from the power supply. Accordingly, the ripple signal is transmitted between the operational amplifier and the pass element, and is subsequently outputted to the load for operation. In such arrangements, when the LDO regulator is applied in the system-on-chip (SOC), the signal outputted from the LDO regulator has poor PSRR which leads to bad performance for operating the load. The details of the PSRR will be discussed in the following paragraphs.
…, at least one feedback path is provided to eliminate the ripple signal (i.e., feedback signal (for example, the current signal I2) coupled to one input terminal of the operational amplifier 310) …. the feedback circuit 330 … is configured to couple the feedback signals, for example, including the current signal I2 from the output circuit 320 to the operational amplifier 310. Therefore, the amplified signal is generated, under the operations, including, for example, eliminating the feedback signal VFB coupled from the output node Vout and the current signal I2 coupled from the feedback circuit 330, by the operational amplifier 310. Accordingly, the signal outputted from the LDO regulator 300 does not affect by the ripple signal in the power supply A1. In this situation, when the LDO regulator 300 is applied in the SOC, the signal outputted from the LDO regulator 300 has good PSRR, which would lead to good performance for operating the load.
FIG. 4 (the bode diagram indicates frequency on x-axis and PSRR on y-axis) illustrates at least one example of a bode diagram with PSRR as a function of frequency for the LDO regulator in accordance with the conventional approach, and at least one of the LDO regulator 300 of FIG. 3, the LDO regulator 500 of FIG. 5, or the LDO regulator 600 of FIG. 6, in accordance with some embodiments of the present disclosure.
Since the LDO regulator is coupled between the power supply and the load, the PSRR is generally used as a parameter, to describe the capability of the LDO regulator for suppressing the variation, including, for example, the ripple signal, of supply signal to the output signal of the LDO regulator. The lower PSRR indicates a better suppressing ability, which results in the less ripple signal in the output signal provided to the load.
Accordingly, the signal outputted from the LDO regulator 500 does not affected by the ripple signal in the power supply A1. In this situation, when the LDO regulator 500 is applied in the SOC, the signal outputted from the LDO regulator 500 has good PSRR, which would lead to good performance for operating the load.
Accordingly, the signal outputted from the LDO regulator 600 does not affected by the ripple signal in the output terminal of the LDO regulator 600 and the ripple signal in the power supply A1. In this situation, when the LDO regulator 600 is applied in the SOC, the signal outputted from the LDO regulator 600 has good PSRR, which would lead to good performance for operating the load.
Based on above Wang’s excerpt, therefore, Examiner still believes, the following,
Wang teaches (Fig. 2-3; col. 4 L62-col. 12 L58) “a first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) operable to adjust the voltage applied to the pass device based on an output node voltage (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220); a second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) comprising a second feedback circuit first n- channel transistor (i.e., NMOS M8-9) and a second feedback circuit second n-channel transistor (i.e., NMOS M8-9); and a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) comprising … to increase one or more of a power supply rejection ratio (PSRR) bandwidth (i.e., Fig. 4; PSRR plot; Col. 10 L62-Col. 11 L39) or a transient response (i.e., the term transient response is not explicitly spelled out, however it is anticipated, since Vout is expected to be at a stable voltage, within specific range, as required by load 220) of the voltage regulator (LDO 300) (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO).
However, Wang fails to teach a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device.
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Above Fig. 8 is from Lionel Guiraud (“Lionel”, US Pat 11940829)
However, Lionel Guiraud (“Lionel”, US Pat 11940829) teaches (Fig. 8; col. L58-col. 11 last line) a circuit (i.e., 30 where PSRR performance is improved using capacitor usage within) comprising one or more transistors in a mirror configuration (i.e., M6-7) to facilitate one or more of: an increased transient response for the voltage regulator (10), or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR (col. 1 L30- col. 2 L51, col. 3 L33-col. 3 L43) when an n-channel transistor is used at the pass device (M5 can be NMOS or PMOS; Col. 5 L64-Col. L13).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Furthermore, see following excerpt from Lionel teaching PSRR,
Col. 1; Lionel
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
11. Claims 9-11, 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (“Wang”, US Pat 11573585).
Regarding independent claim 9, Wang teaches (Fig. 2-3; col. 4 L62-col. 12 L58) a voltage regulator (LDO 300) comprising:
an output node (output node providing an output voltage Vout) operable to be coupled to a load (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220);
a pass device (PMOS M6-7 in a current mirror configuration, driven by voltage Vop) operable to pass current (I1 or M6’s provided current) to the output node (output node providing an output voltage Vout) based on a voltage (Vop) applied to the pass device, wherein the pass device comprises a p-channel transistor;
a first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) operable to adjust the voltage applied to the pass device based on an output node voltage (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220);
a second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) operable to reduce an impedance (i.e., transistor M8’s drain is directly receiving Vout of PMOS pass. M7; wherein M8’s gate & drain is connected in a diode configuration & thus performing as a voltage follower to reduce impedance at the output node. Note that Wang’s M8 is same as Applicant’s claimed voltage follower Fig. 4: 246) of the output node (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220); and
a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) operable to increase a phase margin (i.e., Fig. 4; PSRR plot; Col. 10 L62-Col. 11 L39) of the voltage regulator (LDO 300) (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO).
Regarding claim 10, Wang teaches
wherein the first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) comprises a first resistor (Rfb1), a second resistor (Rfb2), and an amplifier (310), and
wherein the first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) is operable to generate voltage feedback (V1 is divided voltage of Vout, provided from mid-node of Rfb1-2) to be input to the amplifier (op-amp 310’s one input being gate of M1, receiving V1) using the first resistor (Rfb1) and the second resistor (Rfb2)
Regarding claim 11, Wang teaches wherein the second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) is operable to facilitate a reduced impedance at the output node by using a voltage follower (i.e., transistor M8’s drain is directly receiving Vout of PMOS pass. M7; wherein M8’s gate & drain is connected in a diode configuration & thus performing as a voltage follower to reduce impedance at the output node. Note that Wang’s M8 is same as Applicant’s claimed voltage follower Fig. 4: 246).
Regarding claim 13, Wang teaches (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO) a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) comprising:
one or more of a capacitor (Cc in 340) or a resistor (Rc in 340),
wherein the circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) is operable to increase a phase margin (Col. 10 L62-Col. 11 L39) of the voltage regulator (LDO 300) based on one or more of a dominant pole (i.e., Fig. 4; PSRR plot) for the voltage regulator or a zero for the voltage regulator (LDO 300).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US Pat 11573585), in view of Wang II (“Wang II”, US Pub 2014/0340058).
Regarding claim 12, Wang teaches wherein the second feedback circuit (non-scaled 2nd feedback circuit 330, 340 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) comprises an … current … feedback loop facilitating dynamic current (i.e., amplified current I2’s manipulation, which is based on M7’s output) to increase a transient response (i.e., the term transient response is not explicitly spelled out, however it is anticipated, since Vout is expected to be at a stable voltage, within specific range, as required by load 220) of the voltage regulator (LDO 300).
However, Wang fails to teach the second feedback circuit includes adjustment an alternating current (AC) feedback loop.
However, Wang II teaches (Para 33-47) the second feedback circuit (18) includes adjustment an alternating current (AC) feedback loop (Fig. 4; i.e., using 7, which includes RC elements for PSRR improvements during transient events).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to replace the second feedback circuit for adjusting an alternating current (AC) feedback loop facilitating dynamic current to increase a transient response of the voltage regulator, as disclosed by Wang II, as doing so would have provided an improved PSRR operation that is specific to AC current output adjustment, as taught by Wang II (abstract).
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US Pat 11573585), in view of Lionel Guiraud (“Lionel”, US Pat 11940829).
Regarding claim 14, Wang teaches (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO) a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’): an increased transient response for the voltage regulator (i.e., the term transient response is not explicitly spelled out, however it is anticipated, since Vout is expected to be at a stable voltage, within specific range, as required by load 220; Col. 10 L62-Col. 11 L39), or an increased power supply rejection ratio (PSRR) (i.e., Fig. 4; PSRR plot) for the voltage regulator (LDO 300) to match the PSRR.
However, Wang fails to teach a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device.
However, Lionel teaches (Fig. 8; col. L58-col. 11 last line) a circuit (i.e., 30 where PSRR performance is improved using capacitor usage within) comprising one or more transistors in a mirror configuration (i.e., M6-7) to facilitate one or more of: an increased transient response for the voltage regulator (10), or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR (col. 1 L30- col. 2 L51, col. 3 L33-col. 3 L43) when an n-channel transistor is used at the pass device (M5 can be NMOS or PMOS; Col. 5 L64-Col. L13).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Regarding independent claim 15, Wang teaches (Fig. 2-3; col. 4 L62-col. 12 L58) a voltage regulator (LDO 300) comprising:
an output node (output node providing an output voltage Vout) operable to be coupled to a load (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220);
a pass device (PMOS M6-7 in a current mirror configuration, driven by voltage Vop) operable to pass current (I1 or M6’s provided current) to the output node (output node providing an output voltage Vout) based on a voltage (Vop) applied to the pass device, wherein the pass device comprises a p-channel transistor;
a first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) operable to adjust the voltage applied to the pass device based on an output node voltage (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220);
a second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) comprising a second feedback circuit first n- channel transistor (i.e., NMOS M8-9) and a second feedback circuit second n-channel transistor (i.e., NMOS M8-9); and
a circuit (using an RC circuit 340 coupled between 1st FB & 2nd FB, which is same as Applicant’s ‘150, 250 or 435’) comprising … to increase one or more of a power supply rejection ratio (PSRR) bandwidth (i.e., Fig. 4; PSRR plot; Col. 10 L62-Col. 11 L39) or a transient response (i.e., the term transient response is not explicitly spelled out, however it is anticipated, since Vout is expected to be at a stable voltage, within specific range, as required by load 220) of the voltage regulator (LDO 300) (note similar to Fig. 3, Fig. 6 teaches more precise control of phase margin control based on dominant pole control for the LDO regulator, using various capacitor & resistors connection, all intended to further improve the PSRR performance (i.e., Fig. 4) in LDO).
However, Wang fails to teach a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device.
However, Lionel teaches (Fig. 8; col. L58-col. 11 last line) a circuit (i.e., 30 where PSRR performance is improved using capacitor usage within) comprising one or more transistors in a mirror configuration (i.e., M6-7) to facilitate one or more of: an increased transient response for the voltage regulator (10), or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR (col. 1 L30- col. 2 L51, col. 3 L33-col. 3 L43) when an n-channel transistor is used at the pass device (M5 can be NMOS or PMOS; Col. 5 L64-Col. L13).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Regarding claim 16, Wang fails to teach the one or more circuit transistors comprise one or more circuit p-channel transistors and one or more circuit n- channel transistors.
However, Lionel teaches the one or more circuit transistors (i.e., 30 where PSRR performance is improved using capacitor usage within) comprise one or more circuit p-channel transistors and one or more circuit n- channel transistors (i.e., when interchangeably using p-channel vs. n-channel for M6-7).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration with a specific use of p vs. n-channel transistors to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Regarding claim 17, Wang teaches … are operable to input current to one or more of the pass device p- channel transistor (PMOS M6-7) or the second feedback circuit first n-channel transistor (i.e., 330’s uses NMOS M8-9).
However, Wang fails to teach the one or more circuit transistors comprise a circuit first p-channel transistor and a circuit first mirrored p-channel transistor that are operable to input current to one or more of the pass devices or the second feedback circuit.
However, Lionel teaches the one or more circuit transistors (i.e., 30 where PSRR performance is improved using capacitor usage within) comprise a circuit first p-channel transistor (i.e., when interchangeably using p-channel M7) and a circuit first mirrored p-channel transistor (i.e., when interchangeably using p-channel M6) that are operable to input current to one or more of the pass devices (i.e., M5) or the second feedback circuit (i.e., using RC compensation circuit that is used between M5’s output and gate of M5).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration with a specific use of p vs. n-channel transistors to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Regarding claim 18, Wang teaches … operable to receive current from the second feedback circuit (330).
However, Wang fails to teach the one or more circuit transistors comprise a circuit first n-channel transistor and a circuit first mirrored n-channel transistor that are operable to receive current from the second feedback circuit first n-channel transistor.
However, Lionel teaches the one or more circuit transistors (i.e., 30 where PSRR performance is improved using capacitor usage within) comprise a circuit first n-channel transistor (i.e., n-channel M7) and a circuit first mirrored n-channel transistor (i.e., n-channel M6) that are operable to receive current (Iout) from the second feedback circuit (i.e., using RC compensation circuit that is used between M5’s output and gate of M5) first n-channel transistor (i.e., n-channel M7).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s regulator to include a circuit comprising one or more transistors in a mirror configuration with a specific use of p vs. n-channel transistors to facilitate one or more of: an increased transient response for the voltage regulator, or an increased power supply rejection ratio (PSRR) for the voltage regulator to match the PSRR when an n-channel transistor is used at the pass device, as disclosed by Lionel, as doing so would have improved an accuracy and stability of the generated voltage is a key performance parameter, regardless of component mismatch (in a differential pair or current mirror), or finite gain of an error amplifier in a feedback-loop based regulator, and thus ensuring a safer operation of the voltage regulator, as taught by Lionel (col. 1 L10-19 and abstract).
Allowable Subject Matter
Claims 1-8 are allowed.
Regarding independent claim 1. Wang et al. (“Wang”, US Pat 11573585) teaches (Fig. 2-3; col. 4 L62-col. 12 L58) a voltage regulator (LDO 300), comprising: an output node (output node providing an output voltage Vout) operable to be coupled to a load (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220); a pass device (PMOS M6-7 in a current mirror configuration, driven by voltage Vop) operable to pass current (I1 or M6’s provided current) to the output node (output node providing an output voltage Vout) based on a voltage (Vop) applied to the pass device, wherein the pass device comprises a p-channel transistor; a first feedback circuit (a 1st feedback circuit ‘FB1: op. amp 310, voltage divider Rfb1-2’, providing an output Vop, used to adjust PMOS M6-7. Op. amp 310 compares Vbg with a scaled feedback V1; wherein, V1 is based on divided Vout, using Rfb1-2) operable to adjust the voltage applied to the pass device based on an output node voltage (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220), wherein the first feedback circuit (FB1) comprises an error amplifier (op. amp 310) and a resistor divider (voltage divider Rfb1-2) coupled between the output node (Vout) and an input node of the error amplifier (M1’s gate being one of the input node of the 310 that receives VFB); and a second feedback circuit (non-scaled 2nd feedback circuit 330 to further adjusts Vop, used to drive PMOS M6-7 in a current mirror configuration) operable to adjust the voltage (Vop) applied to the pass device based on a change to the output node voltage (voltage Vop drives pass device PMOS M6-7, wherein M6-7’s output is Vout, provided at the output node with an output voltage Vout, received by load 220), wherein the second feedback circuit (non-scaled 2nd feedback circuit 330) comprises a capacitor (i.e., Cc or C3) coupled … a resistor of the resistor divider (voltage divider Rfb1-2).
However, cited prior art(s) failed to teach having “the second feedback circuit (which is operable to adjust the voltage applied to the pass device based on a change to the output node voltage) comprises a capacitor coupled in parallel with a resistor of the resistor divider (which is part of the first feedback circuit; and wherein the first feedback circuit comprises an error amplifier and the resistor divider coupled between the output node and an input node of the error amplifier to adjust the voltage applied to the pass device based on an output node voltage)”.
Claims 2-8 are depending from claim 1.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 19, cited art(s) fails to teach, “the one or more circuit transistors comprise: a circuit first p-channel transistor operable to direct an input current to the second feedback circuit second n-channel transistor, and a circuit first n-channel transistor operable to direct an output current from the second feedback circuit second n-channel transistor, wherein the output current to the input current has a ratio greater than 1.0”.
Claim 20 is depending from claim 19.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838