Office Action Predictor
Last updated: April 15, 2026
Application No. 18/496,854

THROUGH BOARD VIA HEAT SINK

Non-Final OA §102§103
Filed
Oct 28, 2023
Examiner
NG, SHERMAN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Aptiv Technologies AG
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
403 granted / 534 resolved
+7.5% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
6 currently pending
Career history
540
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
59.0%
+19.0% vs TC avg
§102
32.0%
-8.0% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 534 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application No. 18/496,854 filed on 10/28/2023. Information Disclosure Statement The information disclosure statement filed 10/28/2023 has been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered. Claim Objections Claims 8 and 17 are objected to because of the following informalities: Note that dependent claims 8 and 17 should be amended to depend from dependent claims 7 and 16; respectively, since antecedent basis for “second cooling plate” is established in dependent claims 7 and 16. Appropriate correction is required. Allowable Subject Matter Independent claim 1 would be allowable by incorporating dependent claims 2 and 5 and the additional claim limitation “wherein the thermal interface material further provides contact and thermal conduction between the thermally conductive material and the metallic liners within the plurality of openings of the substrate.” Independent claim 10 would be allowable by incorporating dependent claims 11 and 14 and the additional claim limitation “wherein the thermal interface material further provides contact and thermal conduction between the thermally conductive material and the metallic liners within the plurality of openings of the substrate.” See allowable subject matter below. 1. (Proposed Examiner’s Amendment) An electronic device, comprising: an integrated circuit component including a plurality of solder balls on one side; a substrate including a first side adjacent the one side of the integrated circuit component, the substrate including a plurality of openings in the substrate, at least some of the plurality of openings being aligned with the solder balls; a cooling plate situated toward a second side of the substrate; a thermally conductive material within the plurality of openings and thermally coupled with the cooling plate, at least some of the thermally conductive material being thermally coupled with the solder balls; wherein the cooling plate comprises the thermally conductive material and the thermally conductive material within the plurality of openings forms extensions from the cooling plate; wherein the plurality of openings comprise vias through the substrate, the vias are lined with a conductive material that surrounds the thermally conductive material to form metallic liners; and a thermal interface material between the cooling plate and the second side of the substrate, wherein the thermal interface material further provides contact and thermal conduction between the thermally conductive material and the metallic liners within the plurality of openings of the substrate. 10. (Currently Amended) A method of cooling an electronic device including an integrated circuit component having a plurality of solder balls on one side and a substrate having a first side adjacent the one side of the integrated circuit component, the method comprising: situating a cooling plate toward a second side of the substrate; situating a thermally conductive material within a plurality of openings in the substrate such that the thermally conductive material is coupled with the cooling plate and at least some of the thermally conductive material is thermally coupled with the solder balls; dissipating heat from the integrated circuit component by conducting the heat along the thermally conductive material whereby the heat can be radiated from the cooling plate; wherein: the cooling plate comprises the thermally conductive material, the thermally conductive material within the plurality of openings forms extensions from the cooling plate, situating the thermally conductive material comprises inserting the extensions into the openings in the substrate, wherein the plurality of openings comprise vias through the substrate, and the vias are lined with a conductive material that surrounds the thermally conductive material to form metallic liners, and placing a thermal interface material between the cooling plate and the second side of the substrate, wherein the thermal interface material further provides contact and thermal conduction between the thermally conductive material and the metallic liners within the plurality of openings of the substrate. Claims 7, 8, 16, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 9-13, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Braunisch et al. (US 7,646,093). Regarding claim 1, Braunisch discloses (in Fig. 1) an electronic device [100], comprising: an integrated circuit component [108] including a plurality of solder balls [Not labeled but shown in Fig. 1, the solder balls are formed on the top side of die component 108] on one side [top side of die component 108]; a substrate [104] including a first side [top side of substrate 104] adjacent the one side [top side of die component 108] of the integrated circuit component [108], the substrate [104] including a plurality of openings [120] in the substrate [104], at least some of the plurality of openings [120] being aligned with the solder balls [Not labeled but shown in Fig. 1, the solder balls are formed on the top side of die 108]; a cooling plate [116] situated toward a second side of the substrate [bottom side of substrate 104]; and a thermally conductive material [114] within the plurality of openings [120] and thermally coupled with the cooling plate [116], at least some of the thermally conductive material [114] being thermally coupled with the solder balls [Not labeled but shown in Fig. 1, the solder balls are formed on the top side of die 108]; wherein the cooling plate [116] comprises the thermally conductive material [114] and the thermally conductive material [114] within the plurality of openings [120] forms extensions from the cooling plate [116]. Regarding claim 2, Braunisch, as applied to claim 1, further discloses (in Fig. 1) wherein the plurality of openings [120] comprise vias [120] through the substrate [104], and the vias [120] are lined with a conductive material [124] that surrounds the thermally conductive material [114]. Regarding claim 3, Braunisch, as applied to claim 1, further discloses (in Fig. 1) wherein the thermally conductive material [114] within the plurality of openings [120] is configured as a plurality of fins [The thermally conductive material 114 are pins, which are fin-shaped extensions]. Regarding claim 4, Braunisch, as applied to claim 1, further discloses (in Fig. 1) wherein the thermally conductive material [114] within the plurality of openings [120] is configured as a plurality of posts [The thermally conductive material 114 are pins, which act as posts]. Regarding claim 9, Braunisch, as applied to claim 1, further discloses (in Fig. 1) wherein the thermally conductive material [114] comprises a metal including at least one of copper, aluminum or bronze (See Column 2, lines 41-52). Regarding claim 10, Braunisch discloses (in Fig. 1) a method of cooling an electronic device [100] including an integrated circuit component [108] having a plurality of solder balls [Not labeled but shown in Fig. 1, the solder balls are formed on the top side of die component 108] on one side [top side of die component 108] and a substrate [104] having a first side [top side of substrate 104] adjacent the one side [top side of die component 108] of the integrated circuit component [108], the method comprising: situating a cooling plate [116] toward a second side of the substrate [bottom side of substrate 104]; situating a thermally conductive material [114] within a plurality of openings [120] in the substrate [104] such that the thermally conductive material [114] is coupled with the cooling plate [116] and at least some of the thermally conductive material [114] is thermally coupled with the solder balls [Not labeled but shown in Fig. 1, the solder balls are formed on the top side of die 108]; and dissipating heat from the integrated circuit component [108] by conducting the heat along the thermally conductive material [114] whereby the heat can be radiated from the cooling plate [116]; wherein: the cooling plate [116] comprises the thermally conductive material [114], the thermally conductive material [114] within the plurality of openings [120] forms extensions from the cooling plate [116], and situating the thermally conductive material [114] comprises inserting the extensions [114] into the openings [120] in the substrate [104]. Regarding claim 11, Braunisch, as applied to claim 10, further discloses (in Fig. 1) wherein the plurality of openings [120] comprise vias [120] through the substrate [104], and the vias [120] are lined with a conductive material [124] that surrounds the thermally conductive material [114]. Regarding claim 12, Braunisch, as applied to claim 10, further discloses (in Fig. 1) wherein the thermally conductive material [114] within the plurality of openings [120] is configured as a plurality of fins [The thermally conductive material 114 are pins, which are fin-shaped], and situating the thermally conductive material [114] comprises inserting the fins [The thermally conductive material 114 are pins, which are fin-shaped extensions] into the openings [120] in the substrate [104]. Regarding claim 13, Braunisch, as applied to claim 10, further discloses (in Fig. 1) wherein the thermally conductive material [114] within the plurality of openings [120] is configured as a plurality of posts [The thermally conductive material 114 are pins, which act as posts], and situating the thermally conductive material [114] comprises inserting the posts [The thermally conductive material 114 are pins, which act as posts] into the openings [120] in the substrate [104]. Regarding claim 18, Braunisch, as applied to claim 10, further discloses (in Fig. 1) wherein the thermally conductive material [114] comprises a metal including at least one of copper, aluminum or bronze (See Column 2, lines 41-52). Claim Rejections - 35 USC § 103 This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch et al. (US 7,646,093) in view of Berlin et al. (US 2006/0109632). Regarding claim 5, Braunisch, as applied to claim 1, does not disclose a thermal interface material between the cooling plate and the second side of the substrate. Berlin teaches (in Fig. 2) a thermal interface material [34] (See paragraph 0017: Solder layer 34 made of indium, which has a high thermal conductivity) between the cooling plate [22] and the second side of the substrate [bottom side of substrate 10]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Braunisch to have a thermal interface material between the cooling plate and the second side of the substrate, as taught by Berlin, in order to provide a direct path for heat transfer between the integrated circuit component and the cooling plate (as taught by Berlin in paragraph 0019). Regarding claim 14, Braunisch, as applied to claim 10, does not disclose placing a thermal interface material between the cooling plate and the second side of the substrate. Berlin teaches (in Fig. 2) placing a thermal interface material [34] (See paragraph 0017: Solder layer 34 made of indium, which has a high thermal conductivity) between the cooling plate [22] and the second side of the substrate [bottom side of substrate 10]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Braunisch to have a thermal interface material placed between the cooling plate and the second side of the substrate, as taught by Berlin, in order to provide a direct path for heat transfer between the integrated circuit component and the cooling plate (as taught by Berlin in paragraph 0019). Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch et al. (US 7,646,093) in view of Vandentop et al. (US 6,580,611). Regarding claim 6, Braunisch, as applied to claim 1, does not disclose a plurality of fins thermally coupled to the cooling plate, the plurality of fins being on a side of the cooling plate that is opposite the second side of the substrate. Vandentop teaches (in Fig. 3) a plurality of fins [extension portions of heat sink 18] thermally coupled to the cooling plate [heat sink 18], the plurality of fins [extension portions of heat sink 18] being on a side of the cooling plate [heat sink 18] that is opposite the second side of the substrate [bottom side of substrate 6]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Braunisch to have a plurality of fins thermally coupled to the cooling plate, the plurality of fins being on a side of the cooling plate that is opposite the second side of the substrate, as taught by Vandentop, in order to significantly increase the ability to dissipate heat from the integrated circuit component (as taught by Vandentop in Column 3, lines 7-12). Regarding claim 15, Braunisch, as applied to claim 10, does not disclose thermally coupling a plurality of fins to the cooling plate on a side of the cooling plate that is opposite the second side of the substrate. Vandentop teaches (in Fig. 3) thermally coupling a plurality of fins [extension portions of heat sink 18] to the cooling plate [heat sink 18] on a side of the cooling plate [heat sink 18] that is opposite the second side of the substrate [bottom side of substrate 6]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Braunisch to thermally couple a plurality of fins to the cooling plate on a side of the cooling plate that is opposite the second side of the substrate, as taught by Vandentop, in order to significantly increase the ability to dissipate heat from the integrated circuit component (as taught by Vandentop in Column 3, lines 7-12). Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERMAN NG whose telephone number is (571)270-3131. The examiner can normally be reached Mon-Fri 10AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHERMAN NG/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 28, 2023
Application Filed
Jun 26, 2025
Examiner Interview (Telephonic)
Aug 05, 2025
Non-Final Rejection — §102, §103
Apr 07, 2026
Response after Non-Final Action

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+22.1%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 534 resolved cases by this examiner. Grant probability derived from career allow rate.

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