DETAILED ACTION
Claims 1-2, 4-6, 8, 10-12 and 20-30 are pending.
Claims 3, 7, 9 and 13-19 are canceled.
Claims 21-30 are newly added.
Claims 1-2, 4-6, 8, 10-12 and 20-30 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the 35 U.S.C. 103 rejections (Remarks pp. 8-10) have been fully considered. All of the arguments, except one argument regarding the combination of references, are moot in view of the Examiner’s new ground of rejections based on added references to address applicant’s amendments.
The Applicant made general allegations that, without specific arguments, stated “the Office Action has not provided a sufficient reason why a person of ordinary skill would have combined Rago's telecommunication transaction-context system, Vivekraja's queue-arbitration read pointer, Xie's time-series summary tree, and Bentkofsky's cache-sensitive database index to arrive at the amended limitation.” The Examiner’s references are analogous because they are in the same field of computer architecture or pertinent to the particular problem that the claimed invention addresses. Office Action, pp. 10-11.
Furthermore, a new reference, Simkins (US 20040210588 A1) has been added specifically to address the storage of child identification data within the nodes of the tree taught by Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), and Bentkofsky (US 20120278335 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Simkins (US 20040210588 A1).
Regarding Claim 1, Rago teaches an apparatus comprising:
a plurality of event reporting circuitries that are each configured to store context data for one or more detected events, including an event identifier for each of the one or more detected events (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract.
The claimed “event reporting circuitries” is mapped to the disclosed “plurality of processors” on a responding node (also known as a service control point (SCP)) that store context information regarding transactions between the responding node and different originating nodes (also known as signalling transfer points (STPs)).
The claimed “context data” is mapped to the disclosed “context information”.
The claimed “event identifier” is mapped to the disclosed “transaction identifier field” associated with a transaction event between an originating node and a responding node.);
an event map circuitry configured to control one or more notification channels based on an input event identifier (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, and “The specific destination routing number is specified in a customer record stored within one or more databases residing within a service control point (SCP). This record typically contains one and often more destination routing numbers and associated inter-exchange carrier selections that are associated with a dialed 800 number and the manner in which one of these destination routing numbers and its associated inter-exchange carrier is to be selected, e.g. time of day, day of month, originating numbering plan of the caller and the like. An SCP is an on-line real time fault tolerant transaction processing system that provides call processing information (responses) in response to queries received via STPs connected within the signalling network. This call processing information includes call routing instructions, and for enhanced network services, as discussed below, instructions to obtain additional information from a caller. In particular, several different database applications can be concurrently executing on an SCP,” Col 7, Lines 39-58.
The claimed “event map circuitry” is mapped to the circuitry of the “service control point” (responding node) that controls communication routes (notification channels) between different STPs (signalling transfer point, or originating node).
The claimed “input event identifier” is mapped to the disclosed transaction identifier of the messages associated with the communication between the STP (originating node) and the SCP (responding node).
The claimed “notification channels” is mapped to the communication routes established between the service control point/responding node and different signalling transfer points/originating nodes. Each of these routes will have associated transaction identifiers from the messages sent between the associated originating node and the responding node.);
and an event summarization circuitry that is part of a tree including multiple levels of summarization nodes and that is configured to: receive event identifiers from a plurality of child nodes, wherein each child node is one of the plurality of event reporting circuitries or another event summarization circuitry configured to output an event identifier from one of the plurality of event reporting circuitries (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device,” Abstract, and “Specifically, BE processors 220.sub.1, 220.sub.2, 220.sub.3, . . . , 220.sub.n access corresponding transaction database sets 560.sub.1, 560.sub.2, 560.sub.3, . . . , 560.sub.n that collectively form databases 560 through respective software links 541.sub.1, 541.sub.2, 541.sub.3, . . . , 541.sub.n that collectively form links 541,” Col 16, Lines 10-14, and “Access occurs by using the specific values of a responding transaction identifier embedded within the transaction ID field of the transaction portion of a TCAP conversational message, as described above, as a relative address to an appropriate location in the desired context file. Disk drives 262 store transaction databases 570 for BE processors 220 and specifically transaction database sets 570.sub.1, 570.sub.2, 570.sub.3, . . . , 570.sub.n for BE processors 220.sub.1, 220.sub.2, 220.sub.3, . . . , 220n, respectively. Each of these transaction database sets associated with a specific BE processor contains a separate context file for records created by each call processor executing thereon. Specifically, context files 575 residing within transaction database set 570.sub.1 are collectively formed of individual context files 575.sub.1, 575.sub.2, . . . , 575.sub.m that contain records created by call processors 221.sub.1, 221.sub.2, . . . , 221.sub.m, respectively. As part of each transaction database set, disk drives 262 also store databases 579, such as customer records and other remaining files, which are needed in processing calls that require remote database translation and appropriately accessed by the call processors executing on the back end processors. Other routines (not shown) located within transaction database access routines 227.sub.1 provide access to databases 579,” Col 24, Lines 4-28.
The claimed “event summarization circuitry” is mapped to the disclosed overall “databases 560” that collectively stores each of the transaction identifiers from the plurality of processors within the responding node. This is a summarization circuitry because it can be used to summarize a communication history between each of the originating nodes and the responding node, and the databases are associated with corresponding processors.
The claimed “child nodes” is mapped to the disclosed “processors” within the responding node. Each of these processors sends a transaction identifier to the database from within a context file.).
Rago does not teach that the event summarization circuitry is part of a tree including multiple levels of summarization nodes,
or to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes;
output the selected event identifier to the event map circuitry;
and store, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier,
the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
wherein the pointer provides access to iteratively traverse successive child nodes in the tree, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Vivekraja teaches to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes (
Vivekraja discloses, “In some examples, the read pointer can also be controlled by an arbiter which can determine the priority of the newly stored exchange tasks. If the arbiter determines that the newly stored exchange tasks are of highest priority,” ¶ 0027.
Here, the highest priority tasks are selected. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and only the processor with the highest priority level is selected.);
output the selected event identifier to the event map circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, the selected highest priority task is outputted to be processed. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will be outputted.);
and store (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with the processor.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of distributed computer processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; output the selected event identifier to the event map circuitry; and store a pointer to the child node that outputs the selected event identifier. Doing so would help provide easier access to the highest priority identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Rago in view of Vivekraja does not teach that the event summarization circuitry is part of a tree including multiple levels of summarization nodes,
and store, in a memory-mapped register, the pointer to the child node and child identification data for the child node that outputs the selected event identifier,
the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
wherein the pointer provides access to iteratively traverse successive child nodes in the tree, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Xie teaches that the event summarization circuitry is part of a tree including multiple levels of summarization nodes (
Xie discloses, “determining a time interval to be queried and a key of the time sequence corresponding to a summary data to be queried; searching the hard disk file corresponding to the summary data to be queried from the on-board hard disk according to the key of the time sequence corresponding to the summary data to be queried; loading the summary tree corresponding to the summary data to be queried from the hard disk file; and matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶¶ 0056-0059.
The claimed “tree” is mapped to the disclosed “summary tree”, which consists of multiple levels/layers of nodes. The summary tree is iterated through each node until a satisfactory node is found and then accessed in order to obtain summary data corresponding to a queried time interval.
After the combination of Rago in view of Vivekraja, with Xie, the selected event identifier from Rago in view of Vivekraja is used to find and then access Xie’s tree’s node in order to obtain context data for the event.).
Rago in view of Vivekraja, and Xie are both considered to be analogous to the claimed invention because they are in the same field of computer data storage architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja to incorporate the teachings of Xie and provide that the event summarization circuitry is part of a tree including multiple levels of summarization nodes. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the tree structure. (Xie discloses, “matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶ 0059.).
Rago in view of Vivekraja and Xie does not teach to store, in a memory-mapped register, the pointer to the child node and child identification data for the child node that outputs the selected event identifier,
the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
wherein the pointer provides access to iteratively traverse successive child nodes in the tree, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Bentkofsky teaches wherein the pointer provides access to iteratively traverse successive child nodes in the tree (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer data structure architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide that the event summarization circuitry is part of a tree including multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Rago in view of Vivekraja, Xie, and Bentkofsky does not teach to store, in a memory-mapped register, the pointer to the child node and child identification data for the child node that outputs the selected event identifier,
the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates.
However, Simkins teaches to store, in a memory-mapped register, the pointer to the child node and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries (
Simkins discloses, “One or more memory accesses are performed by using at least one memory address defined at least in part by the selected one or more bits and the pointer from the first node information structure. The one or more memory accesses access another node information structure comprising another pointer. In an illustrative embodiment, this process is repeated until a resultant address is determined. Node information structures may comprise leaf/branch indicators, which indicate whether a node is a leaf or a branch. When a leaf branch indicator indicates a leaf, the resultant address is found,” Abstract, “There is a root node that connects through branches to two additional nodes. Each of these two additional nodes are connected through branches to two more nodes and so on until leaves of the radix tree are reached,” ¶ 0003, and “Node 160 comprises a selector 161, a first leaf/branch indicator 162, a first pointer 163, a second leaf/branch indicator 164 and a second pointer 165… The second leaf/branch indicator 164 indicates that the second pointer 165 references a leaf 171 at address ‘110’ (as shown by reference numeral 174). Leaf 171 contains a resultant address, which in this case indicates a VC context of B0h… In general, a VC context is used to access memory in order to determine connection information for an ATM cell,” ¶ 0025.
The claimed “memory-mapped register” is mapped to the memory address, associated with a pointer variable and contained inside a node, that stores the disclosed “pointer 165”, which points to a leaf/child node. This is consistent with paragraph 43 of the present application’s specification, which states “For example, the child node may include memory-mapped registers and the pointer may include a base address associated with the child node”.
The claimed “child identification data” is mapped to the disclosed “node information structure”, which contains a child type indicator (disclosed “leaf/branch indicator”). This is consistent with paragraph 29 of the present application’s specification, which states that “the child identification data may include a version number and/or a child type indicator (e.g., branching summary node vs. leaf storage node).”
The disclosed “branch” node is a branching summarization node because it provides access to a leaf node, as a traversal must be performed through the branches to reach a leaf node. This aligns with paragraph 21 of the present application’s specification, which states “The integrated circuit 110 includes an event summarization tree 140 including an event summarization circuitry 142 that serves as a branching node in the event summarization tree 140. The event summarization circuitry 142 may be configured to take a plurality of event identifiers output by its child nodes as input and output a highest priority event identifier from this set of inputs.”
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Stefanov, the node information structure from Simkins is stored in the processor that outputs the transaction identifier, from Rago in view of Vivekraja, Xie, and Bentkofsky.),
and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates (
Simkins discloses, “Address lookup techniques are presented that process input data and that utilize a number of node information structures. One or more of the node information structures is part of a radix tree. A bit or bits of the input data are selected by using a next node selector from a first node information structure. The first node information structure also comprises a pointer. One or more memory accesses are performed by using at least one memory address defined at least in part by the selected one or more bits and the pointer from the first node information structure. The one or more memory accesses access another node information structure comprising another pointer. In an illustrative embodiment, this process is repeated until a resultant address is determined. Node information structures may comprise leaf/branch indicators, which indicate whether a node is a leaf or a branch. When a leaf branch indicator indicates a leaf, the resultant address is found,” Abstract.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Simkins are both considered to be analogous to the claimed invention because they are in the same field of data access using pointers/references. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Simkins and provide to store, in a memory-mapped register, the pointer to the child node and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates. Doing so would help allow for more memory-efficient data access (Simkins discloses, “Because of high memory requirements for direct mapped memory lookup, other memory organizations have been used. One type of structure used to perform memory lookup is a radix tree. A radix tree is separated into nodes. There is a root node that connects through branches to two additional nodes. Each of these two additional nodes are connected through branches to two more nodes and so on until leaves of the radix tree are reached. A leaf is an end of the tree. A benefit to this structure is that nodes may be added, deleted or modified. Thus, if it is known that only a certain number of nodes need be created, the memory requirement for a radix tree can be smaller than that required for direct mapped address lookup,” ¶ 0003.).
Claim 20 is a non-transitory computer readable medium claim corresponding to the method Claim 1 (Rago Col 32, Lines 66-68, Col 33, Lines 1-38.). Therefore, Claim 20 is rejected for the same reasons set forth in the rejection of Claim 1.
Regarding Claim 2, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1, comprising: a processor core configured to execute instructions (
Rago discloses, “(BE) processors that is connected within the SCP to each physical link for handling the processing of packets appearing on that link. Each FE processor is connected to a corresponding link in a link set and is, also, connected to an associated BE processor. All the BE processors are connected through an appropriate coupling device, such as a star coupler, to a shared disk farm in order to provide access to files stored therein. The protocol, hereinafter referred to as signalling system 7 (SS7), is the ANSI (American National Standards Institute) implementation, as recommended by the ANSI T1X1.1 working group of the signalling system 7 standard that has been initially promulgated by CCITT. All the FE and BE processors are loosely coupled together, through various local area networks, for purposes of processor synchronization and re-assignment,” Col 2, Lines 28-44.);
and a memory storing instructions that, when executed by the processor core, cause the processor core to: load the pointer to the child node that output the selected event identifier that is stored by the event summarization circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with it.);
and accessing, using the pointer, the child node that outputs the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with it.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of distributed computer processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide a memory storing instructions that, when executed by the processor core, cause the processor core to: load the pointer to the child node that output the selected event identifier that is stored by the event summarization circuitry; and accessing, using the pointer, the child node that outputs the selected event identifier. Doing so would help provide easier access to the highest priority event identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Regarding Claim 6, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1, wherein the event map circuitry is configurable by software to associate a list of one or more event identifier values with one of the one or more notification channels (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, “Consequently, a resulting conversational message containing this op code and these originating and responding transaction identifiers is routed by call processor 221.sub.2 through an appropriate output queue (not shown) to TCAP Processes 551 to fabricate an appropriate TCAP conversational message,” Col 25, Lines 23-28, and “For each subsequent TCAP conversational message that forms part of the current transaction and has been generated by SSP 30 and routed as a packet through STP 56 to any FE processor within SCP 200, the corresponding BE processor utilizes the value of the responding transaction identifier in that message to access a specific record stored within context file 575.sub.2 to obtain the current state of transaction processing for this call,” Col 26, Lines 36-44.
The “notification channels”, or the communication routes between the responding node (SCP) and the originating nodes (STPs) have at least one transaction identifier (which are part of a conversational message between the SCP and a STP) associated with them. The conversational message contains a list of said transaction identifiers.).
Regarding Claim 12, Rago teaches a method comprising: receiving event identifiers from a plurality of child nodes, wherein each child node is one of a plurality of event reporting circuitries or an event summarization circuitry configured to output an event identifier from one of the plurality of event reporting circuitries (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract.
The claimed “event reporting circuitries” is mapped to the disclosed “plurality of processors” on a responding node (also known as a service control point (SCP)) that store context information regarding transactions between the responding node and different originating nodes (also known as signalling transfer points (STPs)).
The claimed “context data” is mapped to the disclosed “context information”.
The claimed “event identifier” is mapped to the disclosed “transaction identifier field” associated with a transaction event between an originating node and a responding node.);
Rago does not teach selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; outputting the selected event identifier to an event map circuitry;
and storing, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree,
and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier.
However, Vivekraja teaches selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes (
Vivekraja discloses, “In some examples, the read pointer can also be controlled by an arbiter which can determine the priority of the newly stored exchange tasks. If the arbiter determines that the newly stored exchange tasks are of highest priority,” ¶ 0027.
Here, the highest priority tasks are selected. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and only the processor with the highest priority level is selected.);
outputting the selected event identifier to an event map circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, the selected highest priority task is outputted to be processed. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the processor with the highest priority level will be outputted.);
and storing(
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the context data.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of distributed computer processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; outputting the selected event identifier to an event map circuitry; and storing a pointer to the child node that output the selected event identifier. Doing so would help provide easier access to the highest priority event identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Rago in view of Vivekraja does not teach storing, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes,
and wherein the pointer provides access to iteratively traverse successive child nodes in the tree, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier.
However, Xie teaches wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes (
Xie discloses, “determining a time interval to be queried and a key of the time sequence corresponding to a summary data to be queried; searching the hard disk file corresponding to the summary data to be queried from the on-board hard disk according to the key of the time sequence corresponding to the summary data to be queried; loading the summary tree corresponding to the summary data to be queried from the hard disk file; and matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶¶ 0056-0059.
The claimed “tree” is mapped to the disclosed “summary tree”, which consists of multiple levels/layers of nodes. The summary tree is iterated through each node until a satisfactory node is found and then accessed in order to obtain summary data corresponding to a queried time interval.
After the combination of Rago in view of Vivekraja, with Xie, the selected event identifier from Rago in view of Vivekraja is used to find and then access Xie’s tree’s node in order to obtain context data for the event.).
Rago in view of Vivekraja, and Xie are both considered to be analogous to the claimed invention because they are in the same field of computer data storage architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja to incorporate the teachings of Xie and provide wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the tree structure. (Xie discloses, “matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶ 0059.).
Rago in view of Vivekraja and Xie does not teach storing, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
and wherein the pointer provides access to iteratively traverse successive child nodes in the tree, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates, until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier.
However, Bentkofsky teaches wherein the pointer provides access to iteratively traverse successive child nodes in the tree (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer data structure architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Rago in view of Vivekraja, Xie, and Bentkofsky does not teach to store, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier,
the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries,
and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates.
However, Simkins teaches to store, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries (
Simkins discloses, “One or more memory accesses are performed by using at least one memory address defined at least in part by the selected one or more bits and the pointer from the first node information structure. The one or more memory accesses access another node information structure comprising another pointer. In an illustrative embodiment, this process is repeated until a resultant address is determined. Node information structures may comprise leaf/branch indicators, which indicate whether a node is a leaf or a branch. When a leaf branch indicator indicates a leaf, the resultant address is found,” Abstract, “There is a root node that connects through branches to two additional nodes. Each of these two additional nodes are connected through branches to two more nodes and so on until leaves of the radix tree are reached,” ¶ 0003, and “Node 160 comprises a selector 161, a first leaf/branch indicator 162, a first pointer 163, a second leaf/branch indicator 164 and a second pointer 165… The second leaf/branch indicator 164 indicates that the second pointer 165 references a leaf 171 at address ‘110’ (as shown by reference numeral 174). Leaf 171 contains a resultant address, which in this case indicates a VC context of B0h… In general, a VC context is used to access memory in order to determine connection information for an ATM cell,” ¶ 0025.
The claimed “memory-mapped register” is mapped to the memory address, associated with a pointer variable and contained inside a node, that stores the disclosed “pointer 165”, which points to a leaf/child node. This is consistent with paragraph 43 of the present application’s specification, which states “For example, the child node may include memory-mapped registers and the pointer may include a base address associated with the child node”.
The claimed “child identification data” is mapped to the disclosed “node information structure”, which contains a child type indicator (disclosed “leaf/branch indicator”). This is consistent with paragraph 29 of the present application’s specification, which states that “the child identification data may include a version number and/or a child type indicator (e.g., branching summary node vs. leaf storage node).”
The disclosed “branch” node is a branching summarization node because it provides access to a leaf node, as a traversal must be performed through the branches to reach a leaf node. This aligns with paragraph 21 of the present application’s specification, which states “The integrated circuit 110 includes an event summarization tree 140 including an event summarization circuitry 142 that serves as a branching node in the event summarization tree 140. The event summarization circuitry 142 may be configured to take a plurality of event identifiers output by its child nodes as input and output a highest priority event identifier from this set of inputs.”
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Stefanov, the node information structure from Simkins is stored in the processor that outputs the transaction identifier, from Rago in view of Vivekraja, Xie, and Bentkofsky.),
and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates (
Simkins discloses, “Address lookup techniques are presented that process input data and that utilize a number of node information structures. One or more of the node information structures is part of a radix tree. A bit or bits of the input data are selected by using a next node selector from a first node information structure. The first node information structure also comprises a pointer. One or more memory accesses are performed by using at least one memory address defined at least in part by the selected one or more bits and the pointer from the first node information structure. The one or more memory accesses access another node information structure comprising another pointer. In an illustrative embodiment, this process is repeated until a resultant address is determined. Node information structures may comprise leaf/branch indicators, which indicate whether a node is a leaf or a branch. When a leaf branch indicator indicates a leaf, the resultant address is found,” Abstract.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Simkins are both considered to be analogous to the claimed invention because they are in the same field of data access using pointers/references. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Simkins and provide to store, in a memory-mapped register, a pointer to the child node that outputs the selected event identifier and child identification data for the child node that outputs the selected event identifier, the child identification data including a child type indicator that indicates whether the child node is a branching summarization node or a leaf storage node corresponding to one of the plurality of event reporting circuitries, and the child type indicator stored for each traversed child node determines whether the traversal continues to a next child node or terminates. Doing so would help allow for more memory-efficient data access (Simkins discloses, “Because of high memory requirements for direct mapped memory lookup, other memory organizations have been used. One type of structure used to perform memory lookup is a radix tree. A radix tree is separated into nodes. There is a root node that connects through branches to two additional nodes. Each of these two additional nodes are connected through branches to two more nodes and so on until leaves of the radix tree are reached. A leaf is an end of the tree. A benefit to this structure is that nodes may be added, deleted or modified. Thus, if it is known that only a certain number of nodes need be created, the memory requirement for a radix tree can be smaller than that required for direct mapped address lookup,” ¶ 0003.).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Chausanski (US 6382758 B1).
Regarding Claim 4, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller.
However, Chausanski teaches wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller (
Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.
The claimed “interrupt controller” is mapped to the disclosed “interrupt control circuit”. Said “interrupt control circuit” must be connected to other circuits via a conductor.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Chausanski are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Chausanski and provide wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller. Doing so would help allow for controlling interrupt signals. (Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Lin (US 20190251047 A1).
Regarding Claim 5, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier.
However, Lin teaches wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier (
Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.
The claimed “hardware response circuitry” is mapped to the disclosed “embedded controller” that responds to a hardware event, corresponding to an event identifier, occurring by performing an operation of recording the leading byte and event identifier of the event.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Lin, the notification channels from Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins include the embedded controller from Lin in order to respond to an event corresponding to an event identifier.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Lin are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Lin and provide wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier. Doing so would help allow for responding to the events more quickly and appropriately (Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Cai (US 20190273737 A1).
Regarding Claim 8, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes; and output the action identifier to the event map circuitry.
However, Cai teaches wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes (
Cai discloses, “The server can determine the action (or an identifier of the action) corresponding to the event of the event identifier based on preset associations of events to actions. For example, the server can determine an event associated with the event message and can query a mapping of events to actions, or a mapping of event identifiers to action identifiers,” ¶ 0205.);
and output the action identifier to the event map circuitry (
Cai discloses, “In response to determining the action or action identifier, the server generates a first message based at least in part on the action or action identifier. For example, the server includes the action identifier in a first message. The server communicates the first message to the terminal (e.g., via one or more networks),” ¶ 0205.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Cai, Cai’s action identifier is transmitted to the event map circuitry as specified by Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Cai are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Cai and provide wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes; and output the action identifier to the event map circuitry. Doing so would help allow for generating responses to the event based on the action identifier (Cai discloses, “In response to determining the action or action identifier, the server generates a first message based at least in part on the action or action identifier,” ¶ 0205.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Yadavalli (US 6973422 B1).
Regarding Claim 10, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores.
However, Yadavalli teaches wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores (
Yadavalli discloses, “FIG. 4 is a diagram of a model sequential circuit 29 with race resolution in accordance with one embodiment of the present invention. The "real" elements of model sequential circuit 29 include a flip-flop 30 with a clock clk input and a data1 input. The output of flip-flop 30 is coupled to the input of an AND gate 32. Another input of AND gate 32 is coupled to the clk. The output of AND gate 32 is coupled to the clock input of a flip-flop 34, which has a data2 input. Model sequential circuit 29 also includes a virtual delay element 36 coupled between the clock source and the clock input of flip-flop 30. Virtual delay element 36 has a clock input, which is coupled to a virtual clock vclk,” Col 3, Lines 61-67 and Col 4, Lines 1-5,
“If an updated value of data1 is different than the old value of data1, then the output of flip-flop 30 will be different depending on whether the updated data1 signal or the rising edge of the clk pulse wins the race to the input of flip-flop 30. In the following example, the clock-to-output delay of flip-flop 30 is less than the delay of AND gate 32 and the old value of data1 is "1" and an updated value of data1 is "0". If the rising edge of the clk pulse wins the race, then flip-flop 30 will continue to latch the old value "1", which propagates to AND gate 32. AND gate 32 will then evaluate to a "1" and allow data2 to be latched in flip-flop 34. If the "1" value on the clock input of flip-flop 30 arrives after the new "0" value on data1, then flip-flop 30 will latch "0" to AND gate 32, which outputs a "0" disabling flip-flop 34,” Col 4, Lines 6-19.
Here, the disclosed “model sequential circuit” uses race resolution in order to control updates to data. After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Yadavalli, Yadavalli’s controlling of updates to data is done for the events associated with the data, from Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Yadavalli are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Yadavalli and provide wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores. Doing so would help ensure that the first update of data does not become accidentally overridden by a subsequent update (Yadavalli discloses, “If an updated value of data1 is different than the old value of data1, then the output of flip-flop 30 will be different depending on whether the updated data1 signal or the rising edge of the clk pulse wins the race to the input of flip-flop 30,” Col 4, Lines 6-10.).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Jeon (US 20150106678 A1).
Regarding Claim 11, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein the one or more detected events are errors detected by components of a system on a chip.
However, Jeon teaches wherein the one or more detected events are errors detected by components of a system on a chip (
Jeon discloses, "The system on chip (SOC) may further include an error detector configured to detect errors from output data of the parity-bit decoder," ¶ 0030.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Jeon are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Jeon and provide wherein the one or more detected events are errors detected by components of a system on a chip. Doing so would help allow for ensuring that errors can be identified more quickly in order to be corrected. (Jeon discloses, "The system on chip (SOC) may further include an error detector configured to detect errors from output data of the parity-bit decoder," ¶ 0030.).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Auernhammer (US 20220398130 A1).
Regarding Claim 21, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1, further comprising a local event map circuitry connected to a child node at a level of the tree below a root node of the tree, the local event map circuitry configured to control a notification channel (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, and “The specific destination routing number is specified in a customer record stored within one or more databases residing within a service control point (SCP). This record typically contains one and often more destination routing numbers and associated inter-exchange carrier selections that are associated with a dialed 800 number and the manner in which one of these destination routing numbers and its associated inter-exchange carrier is to be selected, e.g. time of day, day of month, originating numbering plan of the caller and the like. An SCP is an on-line real time fault tolerant transaction processing system that provides call processing information (responses) in response to queries received via STPs connected within the signalling network. This call processing information includes call routing instructions, and for enhanced network services, as discussed below, instructions to obtain additional information from a caller. In particular, several different database applications can be concurrently executing on an SCP,” Col 7, Lines 39-58.
The claimed “event map circuitry” is mapped to the circuitry of the “service control point” (responding node) that controls communication routes (notification channels) between different STPs (signalling transfer point, or originating node).
The claimed “input event identifier” is mapped to the disclosed transaction identifier of the messages associated with the communication between the STP (originating node) and the SCP (responding node).
As previously stated in the rejection of claim 1, the “notification channels” are mapped to the communication routes established between the service control point/responding node and different signalling transfer points/originating nodes. Each of these routes will have associated transaction identifiers from the messages sent between the associated originating node and the responding node.
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach that the local event map circuitry’s notification channel is connected to a tile-level interrupt controller based on an event identifier output by that child node.
However, Auernhammer teaches a tile-level interrupt controller based on an event identifier output by that child node (
Auernhammer discloses, “Each processor core 200 is coupled to an interrupt presentation controller (IPC) 240 and an interrupt routing controller (IRC) 260 via memory I/O bus 210,” ¶ 0017.
The present application’s specification appears to equate the term “tile” with the term “processor core” (“an error detector in an L1 instruction cache 310 in a first processor core or tile, an error detector in an L1 data cache 312 in the first processor core or tile, an error detector in an L1 instruction cache 314 in a second processor core or tile, an error detector in an L1 data cache 316 in the second processor core or tile, an error detector in an L1 instruction cache 318 in a third processor core or tile,” ¶ 0036 of specification, and “Signals driven on this notification channel may cause the tile level interrupt controller 486 to generate interrupts that may be consumed by a third processor core or tile that was the source of the underlying event,” ¶ 0038 of specification.). The disclosed portion of the reference used aligns with the present application’s specification.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Auernhammer, the local event map circuitry’s notification channel would be connected to a processor core and its interrupt controller, as specified by Auernhammer, based on an event identifier output from the local event map circuitry as specified by Vivekraja.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Auernhammer are both considered to be analogous to the claimed invention because they are in the same field of distributed computer processor-based notifications. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Auernhammer and provide that the local event map circuitry’s notification channel is connected to a tile-level interrupt controller based on an event identifier output by that child node. Doing so would help provide correspondence between each notification channel and an interrupt controller in order to interrupt execution of the associated processor if an exception is encountered.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), Auernhammer (US 20220398130 A1), and Fukui (JP 2015228611 A).
Regarding Claim 22, Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Auernhammer teaches the apparatus of claim 21. Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Auernhammer does not teach wherein the local event map circuitry is configured to selectively mask an event identifier output by the child node so that the masked event identifier is not forwarded to a parent node of the child node in the tree.
However, Fukui teaches wherein the local event map circuitry is configured to selectively mask an event identifier output by the child node so that the masked event identifier is not forwarded to a parent node of the child node in the tree (
Fukui discloses, “Therefore, event processing processing such as event filtering processing and event aggregation processing performed at the root node is performed by a front node such as a sensor node or a GW (gateway) node that relays the event (hereinafter referred to as a ‘lower node’). )) Has been devised to reduce the network traffic and the load on the route node (see, for example, Patent Document 1). The event filtering process is a process of discarding unnecessary events, for example. The event aggregation process is a process for aggregating a plurality of events and outputting an event obtained based on the plurality of events. For example, a process of aggregating events indicating power every hour and outputting an event indicating the amount of power is an example of the aggregation process. By performing filtering processing, aggregation processing, and the like at the lower nodes, the number of events that reach the upper nodes and the root node can be reduced. As a result, the network traffic and the load on the route node can be reduced,” Page 2.).
Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Auernhammer, and Fukui are both considered to be analogous to the claimed invention because they are in the same field of tree/graph-based event filtering. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Auernhammer to incorporate the teachings of Fukui and provide wherein the local event map circuitry is configured to selectively mask an event identifier output by the child node so that the masked event identifier is not forwarded to a parent node of the child node in the tree. Doing so would help reduce the data load that is sent to the parent node. (Fukui discloses, “By performing filtering processing, aggregation processing, and the like at the lower nodes, the number of events that reach the upper nodes and the root node can be reduced. As a result, the network traffic and the load on the route node can be reduced,” Page 2.).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), Stolfo (US 4860201 A), and Tapolcai (US 20090182814 A1).
Regarding Claim 23, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising a second tree including a second event summarization circuitry having a root node separate from a root node of the tree, wherein the tree is configured to output event identifiers to a first agent and the second tree is configured to output event identifiers to a second agent that is different from the first agent.
However, Stolfo teaches further comprising a second tree including a second event summarization circuitry having a root node separate from a root node of the tree, (
Stolfo discloses, “Bentley and Kung proposed a specific tree structure illustrated in FIG. 1 which was designed to achieve throughputs on the order described above. As shown in FIG. 1, their tree structure comprises an array of processors P1-P10 organized into two binary trees that share leaf processors P4-P7. Data flows in one binary tree from root processor P1 to leaf processors P4-P7. Data is operated on at the leaf processors and the results flow in the second tree from leaf processors P4-P7 to root processor P10. Obviously, many more processors can be used in the array if desired,” Col 3, Lines 6-16.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Stolfo are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Stolfo and provide further comprising a second tree including a second event summarization circuitry having a root node separate from a root node of the tree. Doing so would help allow for utilizing multiple trees, each consisting of multiple processors, for improving performance.
Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Stolfo does not teach wherein the tree is configured to output event identifiers to a first agent and the second tree is configured to output event identifiers to a second agent that is different from the first agent.
However, Tapolcai teaches wherein the tree is configured to output event identifiers to a first agent and the second tree is configured to output event identifiers to a second agent that is different from the first agent (
Tapolcai discloses, “In another aspect of the present invention, a system for solving at least one computationally significant problem on a distributed basis is provided, the system comprising a plurality of interconnected agent computers providing a distributed network of computers, each agent computer including or being linked to a distributed processing management utility for enabling distributed solution of the problem; at least one agent computer being operable to define a computationally significant problem for solving by the distributed network, such agent computer being the first computer(s); the distributed processing management utility being operable to: (a) define a plurality of sub-trees for the problem using a branch and bound algorithm; (b) assign each sub-tree to one of the agent computers, wherein each agent computer is operable to solve the sub-tree; (c) return the result of each sub-tree solution to the first computer(s) from the agent computers remote from the first computer(s); and (d) aggregate the solutions on the first computer(s) to provide a solution to the problem,” ¶ 0021.
Here, each tree outputs a result to its own respective agent.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Stolfo, with Tapolcai, each tree from Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Stolfo would be configured to output event identifiers to its own agent, as specified by Tapolcai.).
Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Stolfo, and Tapolcai are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Stolfo to incorporate the teachings of Tapolcai and provide wherein the tree is configured to output event identifiers to a first agent and the second tree is configured to output event identifiers to a second agent that is different from the first agent. Doing so would help ensure that multiple trees do not output event identifiers to the same agent, thus preventing data from being overwritten.
Regarding Claim 24, Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, Stolfo, and Tapolcai teaches the apparatus of claim 23, wherein the tree and the second tree share a common one of the plurality of event reporting circuitries as a leaf node (
Stolfo discloses, “Bentley and Kung proposed a specific tree structure illustrated in FIG. 1 which was designed to achieve throughputs on the order described above. As shown in FIG. 1, their tree structure comprises an array of processors P1-P10 organized into two binary trees that share leaf processors P4-P7. Data flows in one binary tree from root processor P1 to leaf processors P4-P7. Data is operated on at the leaf processors and the results flow in the second tree from leaf processors P4-P7 to root processor P10. Obviously, many more processors can be used in the array if desired,” Col 3, Lines 6-16.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Stolfo are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Stolfo and provide wherein the tree and the second tree share a common one of the plurality of event reporting circuitries as a leaf node. Doing so would help allow for multiple event summarization circuitries to access context data from a leaf node, in order to improve accessibility of the context data.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Chen (US 8918388 B1).
Regarding Claim 25, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach wherein the multiple levels of summarization nodes are distributed across different physical regions of an integrated circuit and are configured to aggregate event identifiers from event reporting circuitries located in the respective regions.
However, Chen teaches wherein the multiple levels of summarization nodes are distributed across different physical regions of an integrated circuit and are configured to aggregate event identifiers from event reporting circuitries located in the respective regions (
Chen discloses, “A computer-implemented method for using a data warehouse comprising a cluster of nodes, comprising:… performing, by a scan processor at said each node of said one or more nodes, a scan over said at least one virtual views based on said particular query and any of said particular optimization techniques; performing, by an aggregation processor at said each node of said one or more nodes, local aggregation of said scanned results; at a third node of said one or more nodes, performing global aggregation of said local aggregations to generate search results of said particular query for further post-processing,” Claim 1.
Here, a distributed system of multiple node devices has each node comprising an aggregation processor, thus forming a distributed circuit. Each processor aggregates data in parallel, with a global aggregation being performed at the end to generate search results for a query.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Chen, the multiple levels of summarization nodes from Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins are distributed across multiple different processors, and are configured to aggregate event identifiers in parallel, as specified by Chen.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Chen are both considered to be analogous to the claimed invention because they are in the same field of distributed computer architectures. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Chen and provide wherein the multiple levels of summarization nodes are distributed across different physical regions of an integrated circuit and are configured to aggregate event identifiers from event reporting circuitries located in the respective regions. Doing so would help allow for increased parallelism from utilizing the nodes to aggregate data from different regions at the same time, thus improving performance.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Amano (US 20060161922 A1).
Regarding Claim 26, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the method of claim 12. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising configuring, by software, a set of possible event identifier values to be prioritized in an arbitrary order, wherein selecting the highest priority event identifier is performed according to the arbitrary order.
However, Amano teaches further comprising configuring, by software, a set of possible event identifier values to be prioritized in an arbitrary order, wherein selecting the highest priority event identifier is performed according to the arbitrary order (
Amano discloses, “FIG. 1 shows a case where the task #1 having a priority "4" registers a signal handler A1 having a priority "1" in correspondence with a signal "a" and registers a signal handler B1 having a priority "3" in correspondence with a signal "b". Likewise, the task #2 having a priority "2" registers a signal handler A2 having a priority "5" in correspondence with the signal "a". Here, the smaller the numerical values representing the priorities, the higher the priorities. That is to say, the priority "1" is meant to be highest. However, the relationship is not generally restricted to this. In the present invention, the priorities can be expressed in any arbitrary form as long as they are distinguishable. This holds not only for the example of FIG. 1, but also for examples shown in all the other figures,” ¶ 0030, “Further, an arbitrary priority is set for the signal handler to be registered in response to the request from the task. In other words, the signal handler is registered in the OS 100 while having the task to which it belongs, the corresponding signal and the priority unique thereto as attributes,” ¶ 0032, “The priority of the signal-handler processing task #S to be recorded in the task priority table 101A may be any arbitrary value if no signal handler exists in the queue 12,” ¶ 0091.
Here, priority values can be set in an arbitrary order, meaning that a user/software can freely specify which of the priority values is highest (choose from any of the available values), which one is second highest… and which one is lowest. In other words, the priority values are set based on personal choice or preferences rather than a mathematical formula.
This aligns with paragraph 41 of the present application’s specification, which states “In some implementations, software may be able to configure an event summarization circuitry implementing the process 500 to prioritize a set of possible event identifier values in an arbitrary order.”
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Amano, the event identifier values from Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins can be used to define priorities in an arbitrary order, where the event identifier value with the highest priority, based on this arbitrary order, is selected, as specified by Amano.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Amano are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Amano and provide further comprising configuring, by software, a set of possible event identifier values to be prioritized in an arbitrary order, wherein selecting the highest priority event identifier is performed according to the arbitrary order. Doing so would help allow the user to prioritize specific event identifier values for selection based on the user’s preferences, thus increasing flexibility of the system.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Tan (US 10649824 B1).
Regarding Claim 27, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the method of claim 12. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising overriding an event identifier assigned to a detected event when a condition specified for the detected event is satisfied.
However, Tan teaches further comprising overriding an event identifier assigned to a detected event when a condition specified for the detected event is satisfied (
Tan discloses, “In some embodiments, the subscriber server, upon receiving and/or detecting the event, may automatically modify and/or update the event identifier and the event body based on a computer-executable rule corresponding to an organization policy that is associated with a type of the event,” Col 15, Lines 48-53.
Here, an event identifier assigned to a detected event is modified/updated (overridden) based on a rule that is specified for the event’s type.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Tan are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Tan and provide further comprising overriding an event identifier assigned to a detected event when a condition specified for the detected event is satisfied. Doing so would help allow for easier determination of whether the condition is satisfied by checking the value of the event identifier to see if it has been overridden based on the rule.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), Hoffman (US 7062523 B1), and Dorfman (US 20160378881 A1).
Regarding Claim 28, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the method of claim 12. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising storing a temporally ordered list of event identifiers received from the plurality of child nodes, and retaining an entry of the temporally ordered list after context data for a corresponding event has been cleared from one of the plurality of event reporting circuitries.
However, Hoffman teaches further comprising storing a temporally ordered list of event identifiers received from the plurality of child nodes, (
Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Hoffman, Hoffman’s processor storing the memory with N time-ordered data values is configured to store an ordered list of event identifiers from a plurality of child nodes as specified by Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Hoffman are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Hoffman and provide wherein the event summarization circuitry comprises: a history circuitry configured to store a temporally ordered list of event identifiers received from the plurality of child nodes. Doing so would help allow for more quickly determining the order of which each event occurred, and/or improve response time (Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31).
Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Hoffman does not teach retaining an entry of the temporally ordered list after context data for a corresponding event has been cleared from one of the plurality of event reporting circuitries.
However, Dorfman teaches retaining an entry of the temporally ordered list after context data for a corresponding event has been cleared from one of the plurality of event reporting circuitries (
Dorfman discloses, “In some embodiments, the software application may periodically and/or upon prompting by the user backup the OS contact list with all of the information contained or selected portions, such as name and essential contact information (e.g. phone number, email address, etc.). This may be stored separately by the software application from the OS contact list and/or the software application's synchronization log. Further, the pointers in the synchronization log may be modified to point to the appropriate contact entries in the backup in addition to pointing to the contact entries in the OS contact list. The backup may also be stored remotely, such as on a cloud or other remote storage service, such that it may not be subject to loss due to loss or destruction of the device. The software application may, as described above, detect modification events from the OS contact list, such as the deletion of a contact entry, and may reflect in the synchronization log that a contact entry is deleted such that the backup contact entry may be retained for future recovery,” ¶ 0055.
Here, Dorfman teaches that entries in an OS backup contact list are retained even after the same entries in a different, main OS contact list are cleared.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Hoffman, with Dorfman, the ordered list would retain entries for each event, even after the data has been cleared from the tree, as specified by Dorfman.).
Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Hoffman, and Dorfman are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, Simkins, and Hoffman to incorporate the teachings of Dorfman and provide retaining an entry of the temporally ordered list after context data for a corresponding event has been cleared from one of the plurality of event reporting circuitries. Doing so would help ensure that entries that were lost or deleted can be easily recovered.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Kitahara (US 20210089383 A1).
Regarding Claim 29, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the method of claim 12. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising incrementing a respective one of a plurality of counters in response to receiving an event identifier having a respective value.
However, Kitahara teaches further comprising incrementing a respective one of a plurality of counters in response to receiving an event identifier having a respective value (
Kitahara discloses, “For each matched event, block 306 increments a counter that corresponds to the respective matched pattern. In some embodiments, an event may match multiple different patterns, in which case block 306 can increment multiple respective counters,” ¶ 0028, and “An event pattern can include, for example, a container selector and an attribute matcher. The container selector can specify things like a namespace, a prefix of a pod name, and a container name. An attribute matcher can specify things like a key, an operator, and a value. A tuple of (key, operator, value) can be used to define the condition to check for an event to match with a pattern,” ¶ 0030.
Here, an event may correspond to a pattern, which is a respective value according to paragraph 30 of Kitahara. If an event matches a pattern (a respective value), then the associated counters that correspond to the pattern are incremented.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Kitahara are both considered to be analogous to the claimed invention because they are in the same field of distributed computer architectures. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Kitahara and provide further comprising incrementing a respective one of a plurality of counters in response to receiving an event identifier having a respective value. Doing so would help allow for keeping track of how many event identifiers of a specific value have been received, for each of the possible event identifier values.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), Simkins (US 20040210588 A1), and Deutsch (US 20190138970 A1).
Regarding Claim 30, Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins teaches the method of claim 12. Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins does not teach further comprising propagating an initialization signal through the tree in a direction opposite to a direction in which the event identifiers propagate through the tree, to initialize the plurality of event reporting circuitries.
However, Deutsch teaches further comprising propagating an initialization signal through the tree in a direction opposite to a direction in which the event identifiers propagate through the tree, to initialize the plurality of event reporting circuitries (
Deutsch discloses, “When the behavior broker 622 receives one of these requests it can starts a chain of behaviors that produce the instance of the digital twin. In this example, a first behavior may pull all of the data needed to instantiate a digital twin instance. This behavior may also trigger some additional requests (recursive tree) which trigger a next behavior with some new information which is picked up by the next layer down in the recursive tree of the graph of the digital twin template. Each individual element of the digital twin instance has a behavior to generate itself. All of the instances elements are created based on graph model of the digital twin template. The behaviors continue to be triggered throughout the graph until all assemblies, sub-assemblies, and components of the digital twin are generated. The result is an instance tree of the specific data of the specific elements of the asset,” ¶ 0088.
Here, a tree with individual nodes is instantiated/initialized, from top (root) to bottom (child nodes/leaves). The claimed “initialization signal” is mapped to the signal that triggers initialization of each of the nodes of the tree.
After the combination of Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, with Deutsch, the tree from Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins would have a signal propagated downwards through it to trigger initialization of the event reporting circuitries of each node, as specified by Deutsch.).
Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins, and Deutsch are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, Bentkofsky, and Simkins to incorporate the teachings of Deutsch and provide further comprising propagating an initialization signal through the tree in a direction opposite to a direction in which the event identifiers propagate through the tree, to initialize the plurality of event reporting circuitries. Doing so would help ensure that each of the event reporting circuitries is initialized before reporting events, in order to prevent crashes or errors from an uninitialized event reporting circuitry.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Georgiev et al. (US 20220200845 A1): Scalable Notification Delivery for Network Computing Environments
This reference discloses a user identifier associated with a client device or a session-based notification channel, similar to how event identifiers are associated with notification channels in Claim 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW NMN SUN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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