DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/14/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to the 35 U.S.C. 103 rejections (Remarks pp. 7-9) have been fully considered but are moot in view of the Examiner’s new ground of rejections based on added references to address applicant’s amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 12-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), and Bentkofsky (US 20120278335 A1).
Regarding Claim 1, Rago teaches an apparatus comprising:
a plurality of event reporting circuitries that are each configured to store context data for one or more detected events, including an event identifier for each of the one or more detected events (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract.
The claimed “event reporting circuitries” is mapped to the disclosed “plurality of processors” on a responding node (also known as a service control point (SCP)) that store context information regarding transactions between the responding node and different originating nodes (also known as signalling transfer points (STPs)).
The claimed “context data” is mapped to the disclosed “context information”.
The claimed “event identifier” is mapped to the disclosed “transaction identifier field” associated with a transaction event between an originating node and a responding node.);
an event map circuitry configured to control one or more notification channels based on an input event identifier (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, and “The specific destination routing number is specified in a customer record stored within one or more databases residing within a service control point (SCP). This record typically contains one and often more destination routing numbers and associated inter-exchange carrier selections that are associated with a dialed 800 number and the manner in which one of these destination routing numbers and its associated inter-exchange carrier is to be selected, e.g. time of day, day of month, originating numbering plan of the caller and the like. An SCP is an on-line real time fault tolerant transaction processing system that provides call processing information (responses) in response to queries received via STPs connected within the signalling network. This call processing information includes call routing instructions, and for enhanced network services, as discussed below, instructions to obtain additional information from a caller. In particular, several different database applications can be concurrently executing on an SCP,” Col 7, Lines 39-58.
The claimed “event map circuitry” is mapped to the circuitry of the “service control point” (responding node) that controls communication routes (notification channels) between different STPs (signalling transfer point, or originating node).
The claimed “input event identifier” is mapped to the disclosed transaction identifier of the messages associated with the communication between the STP (originating node) and the SCP (responding node).
The claimed “notification channels” is mapped to the communication routes established between the service control point/responding node and different signalling transfer points/originating nodes. Each of these routes will have associated transaction identifiers from the messages sent between the associated originating node and the responding node.);
and an event summarization circuitry configured to: receive event identifiers from a plurality of child nodes, wherein each child node is one of the plurality of event reporting circuitries or another event summarization circuitry configured to output an event identifier from one of the plurality of event reporting circuitries (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device,” Abstract, and “Specifically, BE processors 220.sub.1, 220.sub.2, 220.sub.3, . . . , 220.sub.n access corresponding transaction database sets 560.sub.1, 560.sub.2, 560.sub.3, . . . , 560.sub.n that collectively form databases 560 through respective software links 541.sub.1, 541.sub.2, 541.sub.3, . . . , 541.sub.n that collectively form links 541,” Col 16, Lines 10-14, and “Access occurs by using the specific values of a responding transaction identifier embedded within the transaction ID field of the transaction portion of a TCAP conversational message, as described above, as a relative address to an appropriate location in the desired context file. Disk drives 262 store transaction databases 570 for BE processors 220 and specifically transaction database sets 570.sub.1, 570.sub.2, 570.sub.3, . . . , 570.sub.n for BE processors 220.sub.1, 220.sub.2, 220.sub.3, . . . , 220n, respectively. Each of these transaction database sets associated with a specific BE processor contains a separate context file for records created by each call processor executing thereon. Specifically, context files 575 residing within transaction database set 570.sub.1 are collectively formed of individual context files 575.sub.1, 575.sub.2, . . . , 575.sub.m that contain records created by call processors 221.sub.1, 221.sub.2, . . . , 221.sub.m, respectively. As part of each transaction database set, disk drives 262 also store databases 579, such as customer records and other remaining files, which are needed in processing calls that require remote database translation and appropriately accessed by the call processors executing on the back end processors. Other routines (not shown) located within transaction database access routines 227.sub.1 provide access to databases 579,” Col 24, Lines 4-28.
The claimed “event summarization circuitry” is mapped to the disclosed overall “databases 560” that collectively stores each of the transaction identifiers from the plurality of processors within the responding node. This is a summarization circuitry because it can be used to summarize a communication history between each of the originating nodes and the responding node, and the databases are associated with corresponding processors.
The claimed “child nodes” is mapped to the disclosed “processors” within the responding node. Each of these processors sends a transaction identifier to the database from within a context file.).
Rago does not teach that the event summarization circuitry is part of a tree including multiple levels of summarization nodes, or to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; output the selected event identifier to the event map circuitry; and store a pointer to the child node that output the selected event identifier, wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Vivekraja teaches to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes (
Vivekraja discloses, “In some examples, the read pointer can also be controlled by an arbiter which can determine the priority of the newly stored exchange tasks. If the arbiter determines that the newly stored exchange tasks are of highest priority,” ¶ 0027.
Here, the highest priority tasks are selected. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and only the processor with the highest priority level is selected.);
output the selected event identifier to the event map circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, the selected highest priority task is outputted to be processed. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will be outputted.);
and store a pointer to the child node that outputs the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with the processor.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide to select a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; output the selected event identifier to the event map circuitry; and store a pointer to the child node that output the selected event identifier. Doing so would help provide easier access to the highest priority identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Rago in view of Vivekraja does not teach that the event summarization circuitry is part of a tree including multiple levels of summarization nodes, or wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Xie teaches that the event summarization circuitry is part of a tree including multiple levels of summarization nodes (
Xie discloses, “determining a time interval to be queried and a key of the time sequence corresponding to a summary data to be queried; searching the hard disk file corresponding to the summary data to be queried from the on-board hard disk according to the key of the time sequence corresponding to the summary data to be queried; loading the summary tree corresponding to the summary data to be queried from the hard disk file; and matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶¶ 0056-0059.
The claimed “tree” is mapped to the disclosed “summary tree”, which consists of multiple levels/layers of nodes. The summary tree is iterated through each node until a satisfactory node is found and then accessed in order to obtain summary data corresponding to a queried time interval.
After the combination of Rago in view of Vivekraja, with Xie, the selected event identifier from Rago in view of Vivekraja is used to find and then access Xie’s tree’s node in order to obtain context data for the event.).
Rago in view of Vivekraja, and Xie are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja to incorporate the teachings of Xie and provide that the event summarization circuitry is part of a tree including multiple levels of summarization nodes. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the tree structure. (Xie discloses, “matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶ 0059.).
Rago in view of Vivekraja and Xie does not teach wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier.
However, Bentkofsky teaches wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide that the event summarization circuitry is part of a tree including multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load the context data for the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Claim 20 is a non-transitory computer readable medium claim corresponding to the method Claim 1 (Rago Col 32, Lines 66-68, Col 33, Lines 1-38.). Therefore, Claim 20 is rejected for the same reasons set forth in the rejection of Claim 1.
Regarding Claim 2, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1, comprising: a processor core configured to execute instructions (
Rago discloses, “(BE) processors that is connected within the SCP to each physical link for handling the processing of packets appearing on that link. Each FE processor is connected to a corresponding link in a link set and is, also, connected to an associated BE processor. All the BE processors are connected through an appropriate coupling device, such as a star coupler, to a shared disk farm in order to provide access to files stored therein. The protocol, hereinafter referred to as signalling system 7 (SS7), is the ANSI (American National Standards Institute) implementation, as recommended by the ANSI T1X1.1 working group of the signalling system 7 standard that has been initially promulgated by CCITT. All the FE and BE processors are loosely coupled together, through various local area networks, for purposes of processor synchronization and re-assignment,” Col 2, Lines 28-44.);
and a memory storing instructions that, when executed by the processor core, cause the processor core to: load the pointer to the child node that output the selected event identifier that is stored by the event summarization circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with it.);
and accessing, using the pointer, the child node that outputs the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors of the responding node in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the transaction associated with it.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide a memory storing instructions that, when executed by the processor core, cause the processor core to: load the pointer to the child node that output the selected event identifier that is stored by the event summarization circuitry; and accessing, using the pointer, the child node that outputs the selected event identifier. Doing so would help provide easier access to the highest priority event identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Regarding Claim 3, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 2, wherein the memory stores instructions that, when executed by the processor core, cause the processor core to: iteratively access the successive child nodes until the one of the plurality of event reporting circuitries is accessed to load the context data for an event corresponding to the selected event identifier (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide wherein the memory stores instructions that, when executed by the processor core, cause the processor core to: iteratively access the successive child nodes until the one of the plurality of event reporting circuitries is accessed to load the context data for an event corresponding to the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Regarding Claim 6, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1, wherein the event map circuitry is configurable by software to associate a list of one or more event identifier values with one of the one or more notification channels (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, “Consequently, a resulting conversational message containing this op code and these originating and responding transaction identifiers is routed by call processor 221.sub.2 through an appropriate output queue (not shown) to TCAP Processes 551 to fabricate an appropriate TCAP conversational message,” Col 25, Lines 23-28, and “For each subsequent TCAP conversational message that forms part of the current transaction and has been generated by SSP 30 and routed as a packet through STP 56 to any FE processor within SCP 200, the corresponding BE processor utilizes the value of the responding transaction identifier in that message to access a specific record stored within context file 575.sub.2 to obtain the current state of transaction processing for this call,” Col 26, Lines 36-44.
The “notification channels”, or the communication routes between the responding node (SCP) and the originating nodes (STPs) have at least one transaction identifier (which are part of a conversational message between the SCP and a STP) associated with them. The conversational message contains a list of said transaction identifiers.).
Regarding Claim 12, Rago teaches a method comprising: receiving event identifiers from a plurality of child nodes, wherein each child node is one of a plurality of event reporting circuitries or an event summarization circuitry configured to output an event identifier from one of the plurality of event reporting circuitries (
Rago discloses, “The responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract.
The claimed “event reporting circuitries” is mapped to the disclosed “plurality of processors” on a responding node (also known as a service control point (SCP)) that store context information regarding transactions between the responding node and different originating nodes (also known as signalling transfer points (STPs)).
The claimed “context data” is mapped to the disclosed “context information”.
The claimed “event identifier” is mapped to the disclosed “transaction identifier field” associated with a transaction event between an originating node and a responding node.);
Rago does not teach selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; outputting the selected event identifier to an event map circuitry; and storing a pointer to the child node that output the selected event identifier, wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier.
However, Vivekraja teaches selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes (
Vivekraja discloses, “In some examples, the read pointer can also be controlled by an arbiter which can determine the priority of the newly stored exchange tasks. If the arbiter determines that the newly stored exchange tasks are of highest priority,” ¶ 0027.
Here, the highest priority tasks are selected. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and only the processor with the highest priority level is selected.);
outputting the selected event identifier to an event map circuitry (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, the selected highest priority task is outputted to be processed. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the processor with the highest priority level will be outputted.);
and storing a pointer to the child node that output the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the context data.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide selecting a highest priority event identifier from a set of event identifiers currently output by the plurality of child nodes; outputting the selected event identifier to an event map circuitry; and storing a pointer to the child node that output the selected event identifier. Doing so would help provide easier access to the highest priority event identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Rago in view of Vivekraja does not teach wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier.
However, Xie teaches wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes (
Xie discloses, “determining a time interval to be queried and a key of the time sequence corresponding to a summary data to be queried; searching the hard disk file corresponding to the summary data to be queried from the on-board hard disk according to the key of the time sequence corresponding to the summary data to be queried; loading the summary tree corresponding to the summary data to be queried from the hard disk file; and matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶¶ 0056-0059.
The claimed “tree” is mapped to the disclosed “summary tree”, which consists of multiple levels/layers of nodes. The summary tree is iterated through each node until a satisfactory node is found and then accessed in order to obtain summary data corresponding to a queried time interval.
After the combination of Rago in view of Vivekraja, with Xie, the selected event identifier from Rago in view of Vivekraja is used to find and then access Xie’s tree’s node in order to obtain context data for the event.).
Rago in view of Vivekraja, and Xie are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja to incorporate the teachings of Xie and provide wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the tree structure. (Xie discloses, “matching from a parent node of the summary tree corresponding to the summary data to be queried, traversing multiple layers of nodes of the summary tree corresponding to the summary data to be queried layer by layer until one or more nodes corresponding to the time interval to be queried are found to obtain the summary data from one or more nodes corresponding to the time interval to be queried,” ¶ 0059.).
Rago in view of Vivekraja and Xie does not teach wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide wherein the event summarization circuitry is part of a tree that includes multiple levels of summarization nodes, and wherein the pointer provides access to iteratively traverse successive child nodes in the tree until one of the plurality of event reporting circuitries is accessed to load context data for the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Regarding Claim 13, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12, comprising: loading the pointer to the child node that output the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the context data.);
and access, using the pointer, the child node that output the selected event identifier (
Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.
Here, a pointer is made for the entry with the selected highest priority task. After the combination of Rago with Vivekraja, priority levels are implemented for each of the processors in Rago, and the selected processor with the highest priority level will have a pointer stored for it, to easily access the context data.).
Rago and Vivekraja are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago to incorporate the teachings of Vivekraja and provide loading the pointer to the child node that output the selected event identifier; and access, using the pointer, the child node that output the selected event identifier. Doing so would help provide easier access to the highest priority event identifier and the associated processor. (Vivekraja discloses, “the arbiter can move the read pointer to the entries that stores the high priority exchange tasks to process those tasks first,” ¶ 0027.).
Regarding Claim 14, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 13, comprising: iteratively accessing the successive child nodes until the one of the plurality of event reporting circuitries is accessed to load the context data for an event corresponding to the selected event identifier (
Bentkofsky discloses, “The child group pointer and the number of partial keys may fit within a cache line. A method is disclosed for traversing the index, for bulk-loading the index, and for live deletion of records from the index,” Abstract, and “Historically, relational databases have used an index structure, called a B+ tree, to provide the shortest path possible to the desired data… The leaf nodes point directly to records in the database (the row data),” ¶ 0002, and “Processor 305 may retrieve the value ‘Abner,’ which is stored at the address represented by the third full key pointer of the current node. Because the search key matches the retrieved data, Processor 305 may determine that a record has been found, and may return the location of the retrieved record,” ¶ 0054.
Here, the pointer to the data record provides access for iteratively traversing through the tree until the node with the pointer to the data record is reached. The node is then used to load the data record.
After the combination of Rago in view of Vivekraja and Xie, with Bentkofsky, Bentkofsky’s child/leaf nodes containing the data records now correspond to event reporting circuitries from Rago in view of Vivekraja and Xie, and Bentkofsky’s data records are now the context data from Rago in view of Vivekraja and Xie. The traversal is done iteratively, using the pointer to the data record, as specified by Bentkofsky.).
Rago in view of Vivekraja and Xie, and Bentkofsky are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja and Xie to incorporate the teachings of Bentkofsky and provide iteratively accessing the successive child nodes until the one of the plurality of event reporting circuitries is accessed to load the context data for an event corresponding to the selected event identifier. Doing so would help ensure that the data can be loaded successfully and/or efficiently using the pointer and the iterative traversal (Bentkofsky discloses, “Therefore, it is desirable to introduce an index structure that facilitates faster access to large main-memory databases while still retaining the ability to add and delete records from the index in real time,” ¶ 0009.).
Regarding Claim 17, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12, comprising: associating a list of one or more event identifier values with a notification channel (
Rago discloses, “producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address,” Abstract, “Consequently, a resulting conversational message containing this op code and these originating and responding transaction identifiers is routed by call processor 221.sub.2 through an appropriate output queue (not shown) to TCAP Processes 551 to fabricate an appropriate TCAP conversational message,” Col 25, Lines 23-28, and “For each subsequent TCAP conversational message that forms part of the current transaction and has been generated by SSP 30 and routed as a packet through STP 56 to any FE processor within SCP 200, the corresponding BE processor utilizes the value of the responding transaction identifier in that message to access a specific record stored within context file 575.sub.2 to obtain the current state of transaction processing for this call,” Col 26, Lines 36-44.
The “notification channels”, or the communication routes between the responding node (SCP) and the originating nodes (STPs) have at least one transaction identifier (which are part of a conversational message between the SCP and a STP) associated with them. The conversational message contains a list of said transaction identifiers.).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Chausanski (US 6382758 B1).
Regarding Claim 4, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie,and Bentkofsky does not teach wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller.
However, Chausanski teaches wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller (
Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.
The claimed “interrupt controller” is mapped to the disclosed “interrupt control circuit”. Said “interrupt control circuit” must be connected to other circuits via a conductor.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Chausanski are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Chausanski and provide wherein the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller. Doing so would help allow for controlling interrupt signals. (Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.).
Regarding Claim 15, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12, wherein the event map circuitry is configured to control one or more notification channels based on an input event identifier (
Rago discloses, “The specific destination routing number is specified in a customer record stored within one or more databases residing within a service control point (SCP). This record typically contains one and often more destination routing numbers and associated inter-exchange carrier selections that are associated with a dialed 800 number and the manner in which one of these destination routing numbers and its associated inter-exchange carrier is to be selected, e.g. time of day, day of month, originating numbering plan of the caller and the like. An SCP is an on-line real time fault tolerant transaction processing system that provides call processing information (responses) in response to queries received via STPs connected within the signalling network. This call processing information includes call routing instructions, and for enhanced network services, as discussed below, instructions to obtain additional information from a caller. In particular, several different database applications can be concurrently executing on an SCP,” Col 7, Lines 39-58.
The claimed “event map circuitry” is the circuitry of the “service control point” (responding node) that controls communication routes (notification channels) between different STPs (signalling transfer point, or originating node).
The claimed “notification channels” is the communication routes established between the service control point/responding node and different signalling transfer points/originating nodes. Each of these routes will have associated transaction identifiers from the messages sent between the associated originating node and the responding node.).
Rago in view of Vivekraja, Xie, and Bentkofsky does not teach that the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller.
However Chausanski teaches that the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller (
Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.
The claimed “interrupt controller” is mapped to the disclosed “interrupt control circuit”. Said “interrupt control circuit” must be connected to other circuits via a conductor.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Chausanski are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Chausanski and provide that the one or more notification channels includes a conductor connected between the event map circuitry and an interrupt controller. Doing so would help allow for controlling interrupt signals. (Chausanski discloses, “An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor,” Abstract.).
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Lin (US 20190251047 A1).
Regarding Claim 5, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier.
However, Lin teaches wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier (
Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.
The claimed “hardware response circuitry” is mapped to the disclosed “embedded controller” that responds to a hardware event, corresponding to an event identifier, occurring by performing an operation of recording the leading byte and event identifier of the event.
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Lin, the notification channels from Rago in view of Vivekraja, Xie, and Bentkofsky include the embedded controller from Lin in order to respond to an event corresponding to an event identifier.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Lin are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Lin and provide wherein the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier. Doing so would help allow for responding to the events more quickly and appropriately (Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.).
Regarding Claim 16, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12. wherein the event map circuitry is configured to control one or more notification channels based on an input event identifier (
Rago discloses, “The specific destination routing number is specified in a customer record stored within one or more databases residing within a service control point (SCP). This record typically contains one and often more destination routing numbers and associated inter-exchange carrier selections that are associated with a dialed 800 number and the manner in which one of these destination routing numbers and its associated inter-exchange carrier is to be selected, e.g. time of day, day of month, originating numbering plan of the caller and the like. An SCP is an on-line real time fault tolerant transaction processing system that provides call processing information (responses) in response to queries received via STPs connected within the signalling network. This call processing information includes call routing instructions, and for enhanced network services, as discussed below, instructions to obtain additional information from a caller. In particular, several different database applications can be concurrently executing on an SCP,” Col 7, Lines 39-58.
The claimed “event map circuitry” is the circuitry of the “service control point” (responding node) that controls communication routes (notification channels) between different STPs (signalling transfer point, or originating node).
The claimed “notification channels” is the communication routes established between the service control point/responding node and different signalling transfer points/originating nodes. Each of these routes will have associated transaction identifiers from the messages sent between the associated originating node and the responding node.).
Rago in view of Vivekraja, Xie, and Bentkofsky does not teach that the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier.
However, Lin teaches that the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier (
Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.
The claimed “hardware response circuitry” is mapped to the disclosed “embedded controller” that responds to a hardware event, corresponding to an event identifier, occurring by performing an operation of recording the leading byte and event identifier of the event.
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Lin, the notification channels from Rago in view of Vivekraja, Xie, and Bentkofsky include the embedded controller from Lin in order to respond to an event corresponding to an event identifier.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Lin are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Lin and provide that the one or more notification channels includes an enable conductor connected between the event map circuitry and a hardware response circuitry configured to perform an operation in response to an event corresponding to the selected event identifier Doing so would help allow for responding to the events more quickly and appropriately. (Lin discloses, “In another embodiment, in response to occurrence of a hardware event, the embedded controller 210 further provides a leading byte according to a level of priority of an interrupt event generated by the hardware event and simultaneously records the leading byte and an event identifier of the interrupt event to the internal memory 215 of the embedded controller 210 itself,” ¶ 0058.).
Claims 7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Hoffman (US 7062523 B1).
Regarding Claim 7, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein the event summarization circuitry comprises: a history circuitry configured to store a temporally ordered list of event identifiers received from the plurality of child nodes.
However, Hoffman teaches wherein the event summarization circuitry comprises: a history circuitry configured to store a temporally ordered list of event identifiers received from the plurality of child nodes (
Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31.
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Hoffman, Hoffman’s processor storing the memory with N time-ordered data values is configured to store an ordered list of event identifiers from a plurality of child nodes as specified by Rago in view of Vivekraja, Xie, and Bentkofsky.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Hoffman are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Hoffman and provide wherein the event summarization circuitry comprises: a history circuitry configured to store a temporally ordered list of event identifiers received from the plurality of child nodes. Doing so would help allow for more quickly determining the order of which each event occurred, and/or improve response time (Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31).
Regarding Claim 18, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach comprising: storing a temporally ordered list of event identifiers received from the plurality of child nodes in a history circuitry.
However, Hoffman teaches comprising: storing a temporally ordered list of event identifiers received from the plurality of child nodes in a history circuitry (
Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31.
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Hoffman, Hoffman’s processor storing the memory with N time-ordered data values is configured to store an ordered list of event identifiers from a plurality of child nodes as specified by Rago in view of Vivekraja, Xie, and Bentkofsky.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Hoffman are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Hoffman and provide comprising: storing a temporally ordered list of event identifiers received from the plurality of child nodes in a history circuitry. Doing so would help allow for more quickly determining the order of which each event occurred, and/or improve response time (Hoffman discloses, “each computation stage comprising a first processor stage having an output including a first memory storing N time-ordered first data values,” Col 8, Lines 28-31).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Cai (US 20190273737 A1).
Regarding Claim 8, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes; and output the action identifier to the event map circuitry.
However, Cai teaches wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes (
Cai discloses, “The server can determine the action (or an identifier of the action) corresponding to the event of the event identifier based on preset associations of events to actions. For example, the server can determine an event associated with the event message and can query a mapping of events to actions, or a mapping of event identifiers to action identifiers,” ¶ 0205.);
and output the action identifier to the event map circuitry (
Cai discloses, “In response to determining the action or action identifier, the server generates a first message based at least in part on the action or action identifier. For example, the server includes the action identifier in a first message. The server communicates the first message to the terminal (e.g., via one or more networks),” ¶ 0205.
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Cai, Cai’s action identifier is transmitted to the event map circuitry as specified by Rago in view of Vivekraja, Xie, and Bentkofsky.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Cai are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Cai and provide wherein the event summarization circuitry is configured to: receive an action identifier associated with the selected event identifier from one of the plurality of child nodes; and output the action identifier to the event map circuitry. Doing so would help allow for generating responses to the event based on the action identifier (Cai discloses, “In response to determining the action or action identifier, the server generates a first message based at least in part on the action or action identifier,” ¶ 0205.).
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Stefanov (US 8706701 B1).
Regarding Claim 9, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein the event summarization circuitry is configured to: store child identification data for the child node that outputs the selected event identifier.
However, Stefanov teaches wherein the event summarization circuitry is configured to: store child identification data for the child node that outputs the selected event identifier (
Stefanov discloses, “FIG. 3B is a diagram of a compacted file version tree 300b. White nodes from FIG. 3A are removed in the compacted version on the right. Version numbers are adjacent to nodes. Each leaf node stores the version number of the covered blocks,” Col 11, Lines 51-55.
The claimed “child identification data” is mapped to the disclosed “version number”. This is consistent with paragraph 29 of the present application’s specification, which states that “the child identification data may include a version number and/or a child type indicator (e.g., branching summary node vs. leaf storage node).”
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Stefanov, the version number from Stefanov is stored in the processor that outputs the transaction identifier, from Rago in view of Vivekraja, Xie, and Bentkofsky.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Stefanov are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Stefanov and provide wherein the event summarization circuitry is configured to: store child identification data for the child node that outputs the selected event identifier. Doing so would help allow for more efficient data access. (Stefanov discloses, “This mechanism provides integrity and freshness for individual file blocks and reduces the amount of expensive random access storage needed for the authenticated data structure,” Col 11, Lines 36-39.).
Regarding Claim 19, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the method of claim 12. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach comprising: storing a version number for the child node that outputs the selected event identifier.
However, Stefanov teaches comprising: storing a version number for the child node that outputs the selected event identifier (
Stefanov discloses, “FIG. 3B is a diagram of a compacted file version tree 300b. White nodes from FIG. 3A are removed in the compacted version on the right. Version numbers are adjacent to nodes. Each leaf node stores the version number of the covered blocks,” Col 11, Lines 51-55.
The claimed “child identification data” is mapped to the disclosed “version number”. This is consistent with paragraph 29 of the present application’s specification, which states that “the child identification data may include a version number and/or a child type indicator (e.g., branching summary node vs. leaf storage node).”
After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Stefanov, the version number from Stefanov is stored in the processor that outputs the transaction identifier, from Rago in view of Vivekraja, Xie, and Bentkofsky).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Stefanov are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Stefanov and provide comprising: storing a version number for the child node that outputs the selected event identifier. Doing so would help allow for more efficient data access. (Stefanov discloses, “This mechanism provides integrity and freshness for individual file blocks and reduces the amount of expensive random access storage needed for the authenticated data structure,” Col 11, Lines 36-39.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Yadavalli (US 6973422 B1).
Regarding Claim 10, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores.
However, Yadavalli teaches wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores (
Yadavalli discloses, “FIG. 4 is a diagram of a model sequential circuit 29 with race resolution in accordance with one embodiment of the present invention. The "real" elements of model sequential circuit 29 include a flip-flop 30 with a clock clk input and a data1 input. The output of flip-flop 30 is coupled to the input of an AND gate 32. Another input of AND gate 32 is coupled to the clk. The output of AND gate 32 is coupled to the clock input of a flip-flop 34, which has a data2 input. Model sequential circuit 29 also includes a virtual delay element 36 coupled between the clock source and the clock input of flip-flop 30. Virtual delay element 36 has a clock input, which is coupled to a virtual clock vclk,” Col 3, Lines 61-67 and Col 4, Lines 1-5,
“If an updated value of data1 is different than the old value of data1, then the output of flip-flop 30 will be different depending on whether the updated data1 signal or the rising edge of the clk pulse wins the race to the input of flip-flop 30. In the following example, the clock-to-output delay of flip-flop 30 is less than the delay of AND gate 32 and the old value of data1 is "1" and an updated value of data1 is "0". If the rising edge of the clk pulse wins the race, then flip-flop 30 will continue to latch the old value "1", which propagates to AND gate 32. AND gate 32 will then evaluate to a "1" and allow data2 to be latched in flip-flop 34. If the "1" value on the clock input of flip-flop 30 arrives after the new "0" value on data1, then flip-flop 30 will latch "0" to AND gate 32, which outputs a "0" disabling flip-flop 34,” Col 4, Lines 6-19.
Here, the disclosed “model sequential circuit” uses race resolution in order to control updates to data. After the combination of Rago in view of Vivekraja, Xie, and Bentkofsky, with Yadavalli, Yadavalli’s controlling of updates to data is done for the events associated with the data, from Rago in view of Vivekraja, Xie, and Bentkofsky.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Yadavalli are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Yadavalli and provide wherein at least one of the plurality of event reporting circuitries includes a race resolution circuitry to control updates to context data for events that it stores. Doing so would help ensure that the first update of data does not become accidentally overridden by a subsequent update (Yadavalli discloses, “If an updated value of data1 is different than the old value of data1, then the output of flip-flop 30 will be different depending on whether the updated data1 signal or the rising edge of the clk pulse wins the race to the input of flip-flop 30,” Col 4, Lines 6-10.).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rago (US 5089954 A) in view of Vivekraja (US 20210097396 A1), Xie (US 20230252029 A1), Bentkofsky (US 20120278335 A1), and Jeon (US 20150106678 A1).
Regarding Claim 11, Rago in view of Vivekraja, Xie, and Bentkofsky teaches the apparatus of claim 1. Rago in view of Vivekraja, Xie, and Bentkofsky does not teach wherein the one or more detected events are errors detected by components of a system on a chip.
However, Jeon teaches wherein the one or more detected events are errors detected by components of a system on a chip (
Jeon discloses, "The system on chip (SOC) may further include an error detector configured to detect errors from output data of the parity-bit decoder," ¶ 0030.).
Rago in view of Vivekraja, Xie, and Bentkofsky, and Jeon are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rago in view of Vivekraja, Xie, and Bentkofsky to incorporate the teachings of Jeon and provide wherein the one or more detected events are errors detected by components of a system on a chip. Doing so would help allow for ensuring that errors can be identified more quickly in order to be corrected. (Jeon discloses, "The system on chip (SOC) may further include an error detector configured to detect errors from output data of the parity-bit decoder," ¶ 0030.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Georgiev et al. (US 20220200845 A1): Scalable Notification Delivery for Network Computing Environments
This reference discloses a user identifier associated with a client device or a session-based notification channel, similar to how event identifiers are associated with notification channels in Claim 1.
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/ANDREW NMN SUN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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