DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 26, 2026 has been entered.
In response to Applicant’s claims filed on January 26, 2026 claims 1, 3-20 are now pending for examination in the application.
Response to Arguments
This office action is in response to amendment filed 01/26/2026. In this action 1, 3-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US Pub. No. 20210157606) and Risvek et al. (US Pub. No. 20170091246) in further view of Liao et al. (US Pub. No. 20200242072). The Liao et al. reference has been added to address the amendment of Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and recording the traversal order for all of the vertices during sampling.
Applicant’s arguments:
In regards to claim 1 on Pages 9, applicant argues “Even if amended claim 11 does invoke this interpretation objection, it is sufficiently supported by the specification and drawings, which also include the corresponding structure(s), as described below.”
Examiner’s Reply:
Applicant's argument on page 9 regarding the 112(f) is not persuasive. The claimed "reader", "sub-module", "module", etc. are not recognized terms for structure, material, or acts that perform the claimed functions. They are generic placeholders that act as a substitute for “means.” In the claims, the generic placeholders that are modified by functional language and are not modified by sufficient structure to perform the claimed functions. Thus, 112(f) is invoked.
Applicant’s arguments:
In regards to claim 1 on Pages 10, applicant argues "the description clearly defines each claim limitation as being part of an FPGA" and "a 'module' or a 'sub-module' refers to a component or a collection of components of an integrated circuit (e.g. FPGA), and that the recited functions will be performed by at least one component of an FPGA."
Examiner’s Reply:
This is not persuasive because there is no discussion of how the FPGA performs the claimed functions. There is no disclosure of the actual logic or algorithms implemented by the FPGA necessary for carrying out each of the claimed functions.
Applicant’s arguments:
In regards to claim 1 on Page(s) 12, applicant argues “While Applicant acknowledges that a claim requiring a computer may still recite a mental process, the claimed invention is not merely the mental process, nor is it merely performed on a generic computer or computer environment. There is a specific computer-implemented method for accelerating graph construction executed by a FPGA communicatively coupled to a DRAM, which utilizes the advantages of FPGA platforms and the characteristics of graph construction to perform specific steps that can accelerate graph construction.”
Examiner’s Reply:
The examiner respectfully disagrees and would like to point out that human mind is fully capable of sampling, grouping, and constructing graph data. The abstract idea recited in the claims is generally linking it to a computer environment.
Applicant’s arguments:
In regards to claim 1 on Page(s) 13, applicant argues “Even if the Examiner alleges the claim is not eligible at Prong 1, claim 1 integrates any alleged judicial exception into a practical application, specifically, as it reflects an improvement in the functioning of datacenter and real-world computer processing, through a computer-implemented method for accelerating graph construction executed by a FPGA communicatively coupled to a DRAM.”
Examiner’s Reply:
The examiner notes that the computer as recited in the claims are being used for graph construction (the computer is being used as a generic tool). Therefore, the abstract idea recited in the claims is generally linking it to a computer environment, and does not integrate the abstract idea into a practical application. Constructing a graph does not improve the functioning of a computing system.
Applicant’s arguments:
In regards to claim 1 on Page(s) 15, applicant argues “Similar remarks from above also apply under this step. Claim 1 includes several additional elements that are sufficient to amount to significantly more than any alleged judicial exception, such as in combination, through at least "according to the vertex traversal order, grouping the vertices into a plurality of blocks and processing them by block granularity using the FPGA.”
Examiner’s Reply:
Graph construction is well understood, routine, and conventional. The additional elements merely allow a user to record the node information given a certain amount of processing resources.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 11-14 and 18-19 contain limitations invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph as detailed in the following:
Claim 11:
“a neighbor list reader…”
“a neighbor sampling sub-module…”
“a pre-reading module…”
“a distance computing sub-module…”
“an updating module…”
"a vector caching sub-module..."
"a computing sub-module..."
"a neighbor loading sub-module..."
"a neighbor merging sub-module..."
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses generic placeholder(s) “reader”, “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Claim 12:
“the neighbor sampling sub-module…”
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses a generic placeholder “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Claim 13:
“the pre-reading module…”
“the distance computing sub-module…”
"the processing subsystem configured to..."
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses a generic placeholder “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Claim 14:
“updating module…”
“a neighbor loading sub-module…”
“a neighbor merging sub-module…”
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses a generic placeholder “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Claim 18:
“pre-reading module…”
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses a generic placeholder “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Claim 19:
“the computing sub-module…”
has been interpreted under 35 U.S.C. 112 (f), or pre-AIA 35 U.S.C. 112 sixth paragraph, because it uses a generic placeholder “sub-module”,” module” coupled with functional languages without reciting sufficient structure to achieve the function and equivalents thereof. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claims 11-14 and 18-19 have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: NONE. The specification fails to show the corresponding structures of the components.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
And 18
Claims 11-14 and 18-19 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Claims 11-14 and 18-19 are interpreted under 35 U.S.C. 112(f) (see above). Therefore Claim(s) 11-14 and 18-19 contain placeholders that require corresponding structure(s). It is unclear whether the recited structure, material, or acts in these claims are sufficient for performing the claimed function because the Specification is unclear about the corresponding structure(s) and the logic or algorithms necessary for performing the claimed functions.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims 12-20 are also rejected for inheriting the deficiencies of the independent claims from which they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-patentable subject matter. The claims are directed to an abstract idea without significantly more.
Claim 1, 3-20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The judicial exception is not integrated into a practical application. The claims do not include additional elements that are sufficient to amount to significantly more than judicial exception. The eligibility analysis in support of these findings is provided below, on Claim Rejections - 35 USC 101 accordance with the "2019 Revised Patent Subject Matter Eligibility Guidance" (published on 1/7/2019 in Fed, Register, Vol. 84, No. 4 at pgs. 50-57, hereinafter referred to as the "2019 PEG").
Step 1. in accordance with Step 1 of the eligibility inquiry (as explained in MPEP 2106), it is first noted the claim method (claims 1, 3-10) and system (claims 11-20) are directed to one of the eligible categories of subject matter and therefore satisfies Step 1.
Step 2A. In accordance with Step 2A, prong one of the 2019 PEG, it is noted that the independent claims recite an abstract idea falling within the Mathematical Concepts & Mental Processes enumerated groupings of abstract ideas set forth in the 2019 PEG. Examiner is of the position that independent claims 1 and 11 are directed towards the Mental Process Grouping of Abstract Ideas.
Independent claims 1 recites the following limitations directed towards a Mathematical Concepts & Mental Processes:
Step 1: sampling neighborhood of each vertex in stored data (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by sampling graph data);
Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and
Step 12: repeating the Step 11, until all of the vertices have been processed, and merging the sampling list and the reverse list of each of the vertices;
Step 2: according to the vertex traversal order, grouping the vertices into a plurality of blocks and processing them by block granularity using the FPGA, so as to at least obtain distance values between each two sampled neighbors of each of the vertices in each of the blocks (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by grouping graph data);
Step 3: according to the distance values regarding the sampled neighbors of each of the vertices, updating the neighborhoods of the two relevant vertices (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by updating graph data).
Step 2A. In accordance with Step 2A, prong two of the 2019 PEG, the judicial exception is not integrated into a practical application because of the recitation in claim(s) 1:
A FPGA (filed programmable storage array);
recording a traversal order for all of the vertices (recites insignificant extra solution activity of storing graph data);
Step 4: processing all of the blocks, starting a new iteration from Step 1, until a graph constructed therefrom has a satisfying precision or a predetermined limit of the number of iterations has been reached (recites insignificant extra solution activity of iterating through graph data).
Independent claims 11 recites the following limitations directed towards a Mathematical Concepts & Mental Processes:
update the neighbor lists accordingly, and write the updated neighbor lists back into the DRAM (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by comparing distances).
Step 2A. In accordance with Step 2A, prong two of the 2019 PEG, the judicial exception is not integrated into a practical application because of the recitation in claim(s) 11:
a neighbor list reader (i.e., as a generic processor/component performing a generic computer function),
a neighbor sampling sub-module (i.e., as a generic processor/component performing a generic computer function),
a pre-reading module (i.e., as a generic processor/component performing a generic computer function),
a distance computing sub-module (i.e., as a generic processor/component performing a generic computer function), and
an updating module (i.e., as a generic processor/component performing a generic computer function), which are configured to communicate with a DRAM, wherein:
the neighbor list reader (i.e., as a generic processor/component performing a generic computer function) is configure to read a neighbor list of each of a plurality of vertices from the DRAM;
the neighbour sampling sub-module is configured to
the pre-reading module (i.e., as a generic processor/component performing a generic computer function) is configured to load vector data of the sampled neighbors from the DRAM based on the recorded traversal order of the vertices (recites merely applying the abstract idea on a computer and using the computer to load vector data);
a vector caching sub-module (i.e., as a generic processor/component performing a generic computer function) configured to cache the loaded vector data of the sampled neighbors (recites merely applying the abstract idea on a computer and using the computer to cache vector data); and
a computing submodule (i.e., as a generic processor/component performing a generic computer function) configured to
the updating module (i.e., as a generic processor/component performing a generic computer function) is configured to update neighbor lists of the vertices based on the computed distance values (recites merely applying the abstract idea on a computer and using the computer to update list data), and comprises:
a neighbor loading sub-module (i.e., as a generic processor/component performing a generic computer function), configured to retrieve from the DRAM the neighbor list of two vertices corresponding to each computed distance value (recites merely applying the abstract idea on a computer and using the computer to retrieving vertices data);
a neighbor merging sub-module
Step 2B. Similar to the analysis under 2A Prong Two, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Because the additional elements of the independent claims amount to insignificant extra solution activity and/or mere instructions, the additional elements do not add significantly more to the judicial exception such that the independent claims as a whole would be patent eligible.
Therefore, independent claims 1 and 11 are rejected under 35 U.S.C. 101.
With respect to claim(s) 2:
Step 2A, prong one of the 2019 PEG:
Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by sampling graph data),
adding a ID of each of the vertices into a reverse list of the sampled neighbors (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by adding graph data to a list), and
and Step 12: repeating the Step 11, until all of the vertices have been processed, and merging the sampling list and the reverse list of each of the vertices (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind by adding graph data in a list).
Step 2A Prong Two Analysis:
recording the traversal order for all of the vertices during sampling (recites insignificant extra solution activity of recording graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 3:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
Step 22: computing data loaded in the Step 21 to acquire the distance values regarding the sampled neighbors of each of the vertices (recites insignificant extra solution activity of data gathering).
Step 21: loading the IDs of the sampled neighbors of all of the vertices in one of the blocks and feature vectors corresponding to these sampled neighbors (recites insignificant extra solution activity of data gathering).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 4:
Step 2A, prong one of the 2019 PEG:
Step 32: comparing each said distance value with distance values of existing neighbors of each vertex, so as to determine whether to add new neighbors to the neighbor list of the relevant vertex (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of comparing graph data).
Step 2A Prong Two Analysis:
Step 31: reading a neighbor list of the two vertices to which each said distance value corresponds (recites insignificant extra solution activity of receiving graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 5:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein the Step 21 comprises steps of: Step 211: according to the recorded IDs of all of the vertices in each of the blocks, reading data of the sampling lists of these vertices (recites insignificant extra solution activity of receiving graph data); and
Step 212: according to the read data of the sampling lists of the vertices, reading the feature vectors of the sampled neighbors (recites insignificant extra solution activity of receiving graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 6:
Step 2A, prong one of the 2019 PEG:
Step 222: processing the generated computing tasks, and recording a maximum distance value regarding each of the neighbors during computing, wherein when a computed intermediate result exceeds the maximum distance value, the relevant computing task is early terminated, and the intermediate result is discarded directly without participating in subsequent steps (The limitation recites a mathematical concept of calculating a distance).
Step 2A Prong Two Analysis:
wherein the Step 22 comprises steps of: Step 221: according to loaded data of the sampled neighbors of each of the vertices and the feature vectors of these sampled neighbors, generating computing tasks (recites insignificant extra solution activity of generating graph data); and
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 7:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein all of the vertices are processed in the DRAM by granularity of blocks, all the required vector data are prefetched to the chip from the blocks, the work load for accessing off-chip memories with high latency can be decreased (recites insignificant extra solution activity of pre-fetching graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 8:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein once the neighbor data of the vertices have been loaded, these data are immediately moved to an idle processing module for processing, without waiting complete loading of all data of all neighborhoods in the blocks, so as to optimize efficiency throughout the dataflow (recites insignificant extra solution activity of transmitting graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 9:
Step 2A, prong one of the 2019 PEG:
wherein after each dimension of the vertex pair data are processed, the computed intermediate result is compared with the maximum value, if the computing for the present vertex pair is recognized as unnecessary computing, the computing is directly ended (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of comparing graph data).
Step 2A Prong Two Analysis:
This judicial exception is not integrated into a practical application because there are no
additional elements to provide practical application.
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 10:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein in the process of computing the distance between the sampled neighbors of each of the vertices based on the vector data of the sampled neighbors, the current maximum distance of the neighbors of every vertex is recorded (recites insignificant extra solution activity of recording graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 12:
Step 2A, prong one of the 2019 PEG:
to enable merging of the sampling list and the reverse neighbor list of each of the vertices when sampling finishes (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of merging a sampling list).
Step 2A Prong Two Analysis:
The FPGA-based system of claim 11, wherein the neighbor list reader and the sampler are implemented with a reading subsystem configured to process vertex data in a CHANNEL of the DRAM,
wherein the sampler comprises:
a neighbor list input circuit of each of the vertices from the DRAM (i.e., as a generic processor/component performing a generic computer function), and
a sampling circuit, for selecting a subset of neighbors for each vertex (i.e., as a generic processor/component performing a generic computer function),
recording the traversal order of the vertices, and maintaining a reverse neighbor list for each of the vertices (recites insignificant extra solution activity of receiving graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 13:
Step 2A, prong one of the 2019 PEG:
a distance computation circuit, capable of computing a distance value between each two of the sampled neighbors according to the sampling data and the vector data of all of the vertices from the pre-reading module (The limitation recites a mathematical concept of calculating a distance).
Step 2A Prong Two Analysis:
A data fetching circuit, for reading sampling data of all of vertices in the DRAM and vector data of the sampled neighbors, and on-chip caching the data (recites insignificant extra solution activity of receiving graph data); and.
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 14
Step 2A, prong one of the 2019 PEG:
for generating addresses and reading the neighbor list of each of the vertices from the DRAM (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of generating addresses)
comparing each said distance value with distance values of existing neighbors of each vertex, so as to determine whether to add new neighbors into the neighbor lists of the relevant vertices (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of comparing graph data).
Step 2A Prong Two Analysis:
wherein the updating controller comprises a neighbor data update subsystem configured to process vertex data in a CHANNEL of the DRAM, and the updating module comprises:
a neighbor loading sub-module, (recites insignificant extra solution activity of receiving graph data); and
a neighbor access circuit, for receiving the distance values computed by the distance computing sub-module, reading the neighbor list of the two neighbors to which each said distance value corresponds from the DRAM (recites insignificant extra solution activity of receiving graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 15:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein the system processes all of the vertices in the DRAM by granularity of blocks, since all the required vector data are prefetched to the chip from the blocks, the work load for accessing off-chip memories with high latency can be decreased (recites insignificant extra solution activity).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 16:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein once the neighbor data of the vertices have been loaded, the system can immediately move these data to an idle processing module for processing, without waiting complete loading of all data of all neighborhoods in the blocks, so as to optimize efficiency throughout the dataflow (recites insignificant extra solution activity of loading graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 17:
Step 2A, prong one of the 2019 PEG:
wherein after processing each dimension of the vertex pair data, the processing module of the system compares the computed intermediate result with the maximum value, if the computing for the present vertex pair is recognized as unnecessary computing, the processing module directly ends the computing, and waits for subsequent processing. the intermediate result for which the computing is early terminated is not transferred to the updating module (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of comparing graph data).
Step 2A Prong Two Analysis:
This judicial exception is not integrated into a practical application because there are no
additional elements to provide practical application.
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 18:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein after the pre-reading module reads some vector data, the distance computing module can start execution, when the vector data of a block have been read, the pre-reading module can immediately start to read data of the next block, thereby hiding off-chip access delay and optimizing performance of the system (recites insignificant extra solution activity of receiving graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 19:
Step 2A, prong one of the 2019 PEG:
Examiner is of the position the dependent claim is directed toward additional elements.
Step 2A Prong Two Analysis:
wherein in the process of computing the distance between the sampled neighbors of each of the vertices based on the vector data of the sampled neighbors, the computing unit records the current maximum distance of the neighbors of every vertex (recites insignificant extra solution activity of recording graph data).
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
With respect to claim(s) 20:
Step 2A, prong one of the 2019 PEG:
wherein when the computed intermediate result exceeds the maximum intermediate distance, the relevant computing task is early terminated, and the computed result is discarded directly (The limitation recites a mental process of observation and/or evaluation capable of being performed by the human mind of deleting graph data).
Step 2A Prong Two Analysis:
This judicial exception is not integrated into a practical application because there are no
additional elements to provide practical application.
Step 2B Analysis:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US Pub. No. 20210157606) and Risvek et al. (US Pub. No. 20170091246) in further view of Liao et al. (US Pub. No. 20200242072).
With respect to claim 1, Zhao et al. teaches an FPGA-based method for accelerating graph construction, comprising:
Step 1: sampling neighborhood of each vertex in stored data, respectively, and
Step 3: according to the distance values regarding the sampled neighbors of each of the vertices, updating the neighborhoods of the two relevant vertices (Paragraph 40 discloses neighborhood relationship is defined on various constraints to make graphs applicable for the ANN problem); and
Step 4: processing all of the blocks, starting a new iteration from Step 1, until a graph constructed therefrom has a satisfying precision or a predetermined limit of the number of iterations has been reached (Paragraph 44 discloses the parallel processing unit (such as a GPU) adaptation problem is investigated and a number of optimizations for graph-based ANN methods are presented & inventive concepts disclosed in this patent document are not limited to just GPUs but may be applied to other hardware components, such as Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuit (ASIC), and the like). Zhao et al. does not disclose recording a traversal order for all of the vertices.
However, Risvek et al. teaches Step 1: sampling neighborhood of each vertex in stored data, respectively, and recording a traversal order for all of the vertices (Paragraph 64 discloses to optimize a layout of large vertices, special edge indices can be created within a large vertex based on edge types, edge data, or neighboring vertex data of the large vertex)
Step 2: according to the vertex traversal order, grouping the vertices into a plurality of blocks and processing them by block granularity, so as to at least obtain distance values between each two sampled neighbors of each of the vertices in each of the blocks (Paragraph 65 discloses Given a set of edges of different types for a vertex object, the shared memory module 120 can group the edges by type and store each set of edges of a single type in an edge list).
Therefore, it would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify Zhao et al. with Risvek et al. to include recording a traversal order for all of the vertices. This would have facilitated improved graph construction and acceleration. See Risvek et al. Paragraph(s) 3-5.
Zhao et al. as modified by Risvek et al. does not disclose Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and recording the traversal order for all of the vertices during sampling.
However, Liao et al. teaches Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and recording the traversal order for all of the vertices during sampling (Paragraph 50 discloses determine the traversal process defined by the graph traversal algorithm; transmitting the graph data to be traversed into the global memory 230 of the second processor 200; using a heuristic sampling method to select the data block to be accessed in the next iteration and transmitting the data block into the on-chip memory 240 of the second processor 200, pre-processing the graph data, and converting the CSC data into a graph adjacency list and Paragraph 64 discloses pre-process the data block containing the initial node so as to identify the initial node for traversal);
Step 12: repeating the Step 11, until all of the vertices have been processed, and merging the sampling list and the reverse list of each of the vertices (Paragraph 39 discloses a graph showing the proportions of the numbers of nodes traversed in the iteration of each level against the total number of nodes in a BFS traversal of a social-network graph, wherein the horizontal axis represents the sequence of traversal iterations and the vertical axis represents the number of nodes traversed in the iteration of each level against the total number of the nodes in the graph, the social network has a diameter of 6, so the total number of traversal iteration is 6).
Therefore, it would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify Zhao et al. and Risvek et al. with Liao et al.to include sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and recording the traversal order for all of the vertices during sampling. This would have facilitated improved graph construction and acceleration. See Liao et al. Paragraph(s) 11-21.
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 1. With respect to claim 3, Zhao et al teaches the FPGA-based method of claim1, wherein the Step 2 comprises steps of:
Step 21: loading the IDs of the sampled neighbors of all of the vertices in one of the blocks and feature vectors corresponding to these sampled neighbors (Paragraph 64 discloses the bulk distance computation stage reads the vector values of these vertices from the data matrix and employs GPU warp reduction 310 to compute the distances to the query point p); and
Step 22: computing data loaded in the Step 21 to acquire the distance values regarding the sampled neighbors of each of the vertices (Paragraph 64 discloses the bulk distance computation stage reads the vector values of these vertices from the data matrix and employs GPU warp reduction 310 to compute the distances to the query point p).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 3. With respect to claim 4, Zhao et al teaches the FPGA-based method of claim 3, wherein the Step 3 comprises steps of:
Step 31: reading a neighbor list of the two vertices to which each said distance value corresponds (Paragraph 40 discloses Vertices of proximity graph represent the points in the dataset. Edges in the graph illustrate neighborhood relationships between the connecting nodes & 40 discloses Extremely Fast Approximate k-Nearest Neighbor graph construction Algorithm; the algorithm processes vertices using sampling and identification); and
Step 32: comparing each said distance value with distance values of existing neighbors of each vertex, so as to determine whether to add new neighbors to the neighbor list of the relevant vertex (Paragraph 40 discloses Vertices of proximity graph represent the points in the dataset. Edges in the graph illustrate neighborhood relationships between the connecting nodes & 40 discloses Extremely Fast Approximate k-Nearest Neighbor graph construction Algorithm; the algorithm processes vertices using sampling and identification).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 4. With respect to claim 5, Zhao et al teaches the FPGA-based method of claim 4, wherein the Step 21 comprises steps of:
Step 211: according to the recorded IDs of all of the vertices in each of the blocks, reading data of the sampling lists of these vertices (Paragraph 108 discloses for two data vectors u, v?custom-character.sup.d, a random vector r?custom-character.sup.d with entries in iid (independent and identically distributed) standard normal is generated. Then, Pr(sgn(<u,r>)=sgn(<v,r>)))=1??(u,v)/?, where ?(u, v) is the angle between u and v. If entries of r are sampled from iid cauchy instead of normal, then this collision probability is closely related to the ?.sup.2 similarity); and
Step 212: according to the read data of the sampling lists of the vertices, reading the feature vectors of the sampled neighbors (Paragraph 64 discloses the bulk distance computation stage reads the vector values of these vertices from the data matrix and employs GPU warp reduction 310 to compute the distances to the query point p).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 5. With respect to claim 6, Zhao et al teaches the FPGA-based method of claim 5, wherein the Step 22 comprises steps of:
Step 221: according to loaded data of the sampled neighbors of each of the vertices and the feature vectors of these sampled neighbors, generating computing tasks (Paragraph 67 discloses the data structures are designed specifically for the graph searching task on GPU); and
Step 222: processing the generated computing tasks, and recording a maximum distance value regarding each of the neighbors during computing, wherein when a computed intermediate result exceeds the maximum distance value, the relevant computing task is early terminated, and the intermediate result is discarded directly without participating in subsequent steps (Paragraph 92 discloses a selection before the insertion may be used: the vertices that have larger distances than all the K elements in the topk are filtered out—a vertex is marked as visited and pushed into q only when it is among the current top-K closest vertices to the query point).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 6. With respect to claim 7, Zhao et al teaches the FPGA-based method of claim 6, wherein all of the vertices are processed in the DRAM by granularity of blocks, all the required vector data are prefetched to the chip from the blocks, the work load for accessing off-chip memories with high latency can be decreased (Paragraph 75 discloses GPU shared memory can be accessed by all threads in the same block in low latency).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 7. With respect to claim 8, Zhao et al teaches the FPGA-based method of claim 7, wherein once the neighbor data of the vertices have been loaded, these data are immediately moved to an idle processing module for processing, without waiting complete loading of all data of all neighborhoods in the blocks, so as to optimize efficiency throughout the dataflow (Paragraph 101 discloses Multiple queries may be processed in a warp to improve thread utilization. For example, consider the system is processing 4 queries in a warp. Priority queues and hash tables for each query may be constructed. 4 active threads (say, e.g., threads 0, 1, 2, and 3) extract the vertex id from their corresponding q).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 8. With respect to claim 9, Zhao et al teaches the FPGA-based method of claim 8, wherein after each dimension of the vertex pair data are processed, the computed intermediate result is compared with the maximum value, if the computing for the present vertex pair is recognized as unnecessary computing, the computing is directly ended (Paragraph 63 discloses distances are computed in a batch instead of a large number of independent pair-wise distance computation function calls. Therefore, in one or more embodiments, the distance computation part is extracted from a searching workflow by decoupling the graph searching methodology into three stages: candidates locating, bulk distance computation, and data structures updating).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 9. With respect to claim 10, Zhao et al teaches the FPGA-based method of claim 9, wherein in the process of computing the distance between the sampled neighbors of each of the vertices based on the vector data of the sampled neighbors, the current maximum distance of the neighbors of every vertex is recorded (Paragraph 63 discloses distances are computed in a batch instead of a large number of independent pair-wise distance computation function calls. Therefore, in one or more embodiments, the distance computation part is extracted from a searching workflow by decoupling the graph searching methodology into three stages: candidates locating, bulk distance computation, and data structures updating).
With respect to claim 11, Zhao et al. teaches an FPGA-based system for accelerating graph construction, comprising a neighbor list reader, a neighbor sampling sub-module, a pre-reading module, a distance computing sub-module, and an updating module, which are configured to communicate with a DRAM, wherein:
the pre-reading module is configured to load vector data of the sampled neighbors from the DRAM based on the recorded traversal order of the vertices (Paragraph 64 discloses the bulk distance computation stage reads the vector values of these vertices from the data matrix and employs GPU warp reduction 310 to compute the distances to the query point p);
the distance computing sub-module is configured to compute distance values between each two of the sampled neighbors of each of the vertices (Paragraph 63 discloses distances are computed in a batch instead of a large number of independent pair-wise distance computation function calls. Therefore, in one or more embodiments, the distance computation part is extracted from a searching workflow by decoupling the graph searching methodology into three stages: candidates locating, bulk distance computation, and data structures updating), and comprises:
and the updating module is configured to update neighbor lists of the vertices based on the computed distance values (Paragraph 40 discloses neighborhood relationship is defined on various constraints to make graphs applicable for the ANN problem), and comprises:
a neighbor loading sub-module configured to retrieve from the DRAM the neighbor list of two vertices corresponding to each computed distance value (Paragraph 40 discloses Vertices of proximity graph represent the points in the dataset. Edges in the graph illustrate neighborhood relationships between the connecting nodes & 40 discloses Extremely Fast Approximate k-Nearest Neighbor graph construction Algorithm; the algorithm processes vertices using sampling and identification); and
a neighbor merging sub-module configured to compare each computed distance value with existing neighbor list values, update the neighbor lists accordingly (Paragraph 40 discloses Vertices of proximity graph represent the points in the dataset. Edges in the graph illustrate neighborhood relationships between the connecting nodes & 40 discloses Extremely Fast Approximate k-Nearest Neighbor graph construction Algorithm; the algorithm processes vertices using sampling and identification), and write the updated neighbor lists back into the DRAM (Paragraph 40 discloses neighborhood relationship is defined on various constraints to make graphs applicable for the ANN problem).
However, Risvek et al. teaches the neighbor list reader is configured to read a neighbor list of each of the plurality of vertices in the DRAM (Paragraph 64 discloses to optimize a layout of large vertices, special edge indices can be created within a large vertex based on edge types, edge data, or neighboring vertex data of the large vertex);
a vector caching sub-module configured to cache the loaded vector data of the sampled neighbors:
and a computing sub-module configured to compute the distance values using the cached vector data (Paragraph 65 discloses Given a set of edges of different types for a vertex object, the shared memory module 120 can group the edges by type and store each set of edges of a single type in an edge list).
Therefore, it would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify Zhao et al. with Risvek et al. to include recording a traversal order for all of the vertices. This would have facilitated improved graph construction and acceleration. See Risvek et al. Paragraph(s) 3-5.
Zhao et al. as modified by Risvek et al. does not disclose Step 11: sampling the neighborhood of each of the vertices, adding IDs of some of the neighbors of each of the vertices into a sampling list, adding a ID of each of the vertices into a reverse list of the sampled neighbors, and recording the traversal order for all of the vertices during sampling.
However, Liao et al. teaches the neighbour sampling sub-module is configured to sample sampler is used for sampling a subset of neighbors from the neighbor list of each of the vertices from the DRAM, and record the sampled data and the recorded traversal order of all the vertices into the DRAM (Paragraph 50 discloses determine the traversal process defined by the graph traversal algorithm; transmitting the graph data to be traversed into the global memory 230 of the second processor 200; using a heuristic sampling method to select the data block to be accessed in the next iteration and transmitting the data block into the on-chip memory 240 of the second processor 200, pre-processing the graph data, and converting the CSC data into a graph adjacency list and Paragraph 64 discloses pre-process the data block containing the initial node so as to identify the initial node for traversal).
Therefore, it would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify Zhao et al. and Risvek et al. with Liao et al. to include the neighbour sampling sub-module is configured to sample sampler is used for sampling a subset of neighbors from the neighbor list of each of the vertices from the DRAM, and record the sampled data and the recorded traversal order of all the vertices into the DRAM. This would have facilitated improved graph construction and acceleration. See Liao et al. Paragraph(s) 11-21.
With respect to claim 12, it is rejected on grounds corresponding to above rejected claim 2, because claim 12 is substantially equivalent to claim 2.
With respect to claim 13, it is rejected on grounds corresponding to above rejected claim 3, because claim 13 is substantially equivalent to claim 3.
With respect to claim 14, it is rejected on grounds corresponding to above rejected claim 4, because claim 14 is substantially equivalent to claim 4.
With respect to claim 15, it is rejected on grounds corresponding to above rejected claim 7, because claim 15 is substantially equivalent to claim 7.
With respect to claim 16, it is rejected on grounds corresponding to above rejected claim 8, because claim 16 is substantially equivalent to claim 8.
With respect to claim 17, it is rejected on grounds corresponding to above rejected claim 9, because claim 17 is substantially equivalent to claim 9.
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 17. With respect to claim 18, Zhao et al teaches the FPGA-based system of claim 17, wherein after the pre-reading module reads some vector data, the distance computing module can start execution, when the vector data of a block have been read, the pre-reading module can immediately start to read data of the next block, thereby hiding off-chip access delay and optimizing performance of the system (Paragraph 64 discloses the bulk distance computation stage reads the vector values of these vertices from the data matrix and employs GPU warp reduction 310 to compute the distances to the query point p).
The Zhao et al. reference as modified by Risvek et al. and Liao et al. teaches all the limitations of claim 18. With respect to claim 19, Zhao et al teaches the FPGA-based system of claim 18, wherein in the process of computing the distance between the sampled neighbors of each of the vertices based on the vector data of the sampled neighbors, the computing unit records the current maximum distance of the neighbors of every vertex (Paragraph 63 discloses distances are computed in a batch instead of a large number of independent pair-wise distance computation function calls. Therefore, in one or more embodiments, the distance computation part is extracted from a searching workflow by decoupling the graph searching methodology into three stages: candidates locating, bulk distance computation, and data structures updating).
With respect to claim 20, it is rejected on grounds corresponding to above rejected claim 6, because claim 20 is substantially equivalent to claim 6.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG-PUB 20210097221 is directed to OPTIMIZATION METHOD FOR GRAPH PROCESSING BASED ON HETEROGENEOUS FPGA DATA STREAMS: [0014] an optimization method for graph processing based on heterogeneous FPGA data streams. The optimization method is especially an optimization method for graph processing of data streams based on a CPU+FPGA heterogeneous structure, which can send graph data to a CPU processing module and an FPGA processing module respectively according to the power-law distribution properties of graph for dynamic acceleration processing by means of task assignment, so that the FPGA processing module can work with the CPU processing module to process irregular data streams in the graph data while balancing processing loads between the CPU processing module and the FPGA processing module caused by irregularity of the graph data and thereby obtain a graph processing result. The method comprises: a shared storage module for storing the graph data intended to receive graph processing; the CPU processing module and the FPGA processing module are communicatively connected with the shared storage module, respectively in a parallel manner, so as to enable the CPU processing module and the FPGA processing module to each read at least a part of the graph data in a real-time manner, and to perform graph processing on the parts of the graph data they read, thereby obtaining a CPU graph processing result and/or an FPGA graph processing result; and an integration module integrating the CPU graph processing result and/or the FPGA graph processing result, so as to obtain the graph processing result, the FPGA processing module reading the graph data stored in the shared storage module and, before performing graph processing on the graph data, performing traversal on the graph data based on the power-law distribution properties of the graph data in virtue of editability of the FPGA processing module, so as to acquire at least one irregularity parameter of the irregular data streams in the graph data, and the scheduling module assigning the part of the graph data that agree with the CPU processing module to the CPU processing module for graph processing, so as to obtain the CPU graph processing result, and assigning the other part to the FPGA processing module that has a parallel processing function for graph processing, so as to obtain the FPGA graph processing result by means of matching the at least one irregularity parameter with preset access rules agreeing with the irregularity parameter.
Conclusion
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/N.E.A/Examiner, Art Unit 2154
/SYED H HASAN/Primary Examiner, Art Unit 2154
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