DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed August 4, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the claims, drawings, and specification have overcome each and every objection previously presented in the Non-Final Office Action mailed May 14, 2026, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments filed August 4, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 11-14, that previously presented prior art reference Modi et al. “Efficiency Improvement of Doherty Power Amplifiers using Supply Switching and Gate Bias Modulation”, as cited by applicant, hereafter referred to as Modi, fails to disclose all of the limitations relating to the claimed “second circuit” and “third circuit”. Examiner respectfully disagrees.
First, applicant argues that element “TGBias” of Fig. 3 of Modi fails to disclose the second circuit because it is a lookup table, which a data structure and not a circuit. However, as implemented in Modi, TGBias takes an input signal (Pout-d), modifies it under the function f2, and outputs the signal to generate the bias voltage VgP, which forms all of the functionality of the claimed “second circuit”, and therefore TGBias is appropriately mapped to the claimed “second circuit”.
Applicant further argues that TGBias does not receive the claimed first signal because it does not receive Pin. However, as described in the Non-Final Office Action (see page 4, lines 6-7, “[a] system (Modi, Fig. 3), comprising: a driver (Fig. 3, see element “K”) configured to provide a first signal (Fig. 3, “Pout-d”)”), the claimed first signal was mapped to the signal “Pout-d” in Modi. As TGBias clearly receives Pout-d in Fig. 3, shown below, TGBias does receive the claimed first signal, and therefore is appropriately mapped to the claimed “second circuit”.
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Applicant further argues that the “Peaking PA” of Fig. 3 of Modi fails to disclose all of the limitations relating to the claimed “third circuit” because it does not receive the claimed “first signal”, which applicant incorrectly stated was “Pin”. As stated above, the “first signal” was not mapped to Pin, and was instead mapped to “Pout-d”. Furthermore, the “Peaking PA” does receive a transformed version of signal Pout-d, as shown in Fig. 3, reproduced above (consider that TGBias transforms Pout-d into f2(Pout-d), which becomes the bias voltage VgP. Applicant’s claim language and specification do not explicitly state that a transformed version of a signal cannot be referred to as that signal (by for example, stating a direct connection of the signal to a specified circuit element), so therefore, it is improper to assume this.
Applicant further argues that Modi does not disclose a signal that defines a bias voltage between two terminals. However, as shown in Fig. 3 above, one terminal of the “Peaking PA” receives the gate bias voltage VgP, and a supply terminal VS-P receives a specified supply voltage of either VSH or VSL. Therefore, the gate bias voltage VgP does define a voltage bias between the two terminals, based on the difference between the gate bias voltage VgP and the predetermined level of the supply terminal VS-P.
Therefore, all of applicant’s arguments are unconvincing and the rejections of claims 1-20 are maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 11-15, and 18 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Modi.
Regarding claim 1, Modi discloses:
A system (Modi, Fig. 3), comprising: a driver (Fig. 3, see element “K”) configured to provide a first signal (Fig. 3, “Pout-d”) to indicate a first amount of power and the first signal having a first level (Page 2, Col. 1, lines 21-25); and a device (Fig. 3, see elements after “K”) in communication with the driver (Fig. 3, see connections between “K” and “TGBias” and “TPin”), the device comprising: a first circuit (Fig. 3, “Carrier PA”) configured to: provide, in response to receipt of the first signal (Fig. 3, see connection between “Pout-d” and “Carrier PA” at “Input Splitter”), a second signal that is an amplification of the first signal (Fig. 3, consider output of “Carrier PA”), the second signal having a first level based at least on the first level of the first signal (Fig. 3, consider output of “Carrier PA”); a second circuit (Fig. 3, “TGBias”) configured to: detect, in response to receipt of the first signal, the first level of the first signal (Page 2, Col. 1, lines 21-25); and provide, in response to detection of the first level of the first signal, a third signal to control a third circuit of the device (Fig. 3, consider signal “VgP” to control “Peaking PA, and Page 2, Col. 1, lines 17-20), wherein the third signal controls the third circuit by defining a voltage bias between a first terminal and a second terminal of the third circuit of the device (Fig. 3, consider voltage difference between terminal at input of “Peaking PA” and reference terminal of “Peaking PA”); the third circuit configured to: provide, in response to receipt of the first signal and the third signal, a fourth signal (Fig. 3, consider output of “Peaking PA”), the fourth signal having a first level in response to the voltage bias being smaller than a predetermined value (Fig. 4, consider peaking amplifier level with output power below ~46 dBm), and the fourth signal having a second level in response to the voltage bias being larger than the predetermined value (Fig. 4, consider peaking amplifier level with output power above ~46 dBm); and a fourth circuit (Fig. 3, see node combining signals from “Carrier PA” and “Peaking PA”) configured to: provide, in response to receipt of the second signal and the fourth signal, a fifth signal (Fig. 3, consider node at output resistor), the fifth signal having a first level based at least on the first level of the second signal (Fig. 4, consider output power as <46 dBm without peaking amplifier activated), and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal (Fig. 4, consider output power as >46 dBm with peaking amplifier activated).
Regarding claim 2, Modi further discloses:
wherein: the fifth signal has the first level in response to the fourth signal having the first level (Modi, Fig. 4, consider output power as <46 dBm without peaking amplifier activated); and the fifth signal has the second level in response to the fourth signal having the second level (Fig. 4, consider output power as >46 dBm with peaking amplifier activated).
Regarding claim 3, Modi further discloses:
wherein the second level of the fifth signal is larger than the second level of the fourth signal (Modi, Fig. 4, consider that less than 100% of the output power is provided by “Peaking PA” ), and wherein the second level of the fourth signal is larger than first level of the second signal (Fig. 4, consider portion of output signal contributed by “Peaking PA” above ~46 dBm, and portion of output signal contributed by “Carrier PA” below ~46 dBm).
Regarding claim 4, Modi further discloses:
wherein the first level of the second signal is larger than the first level of the fourth signal (Modi, Fig. 4, consider that all of the output power is provided by “Carrier PA” when the output power is below ~46 dBm), and wherein the first level of the second signal is smaller than the second level of the fourth signal (Fig. 4, consider portion of output signal contributed by “Peaking PA” above ~46 dBm, and portion of output signal contributed by “Carrier PA” below ~46 dBm).
Regarding claim 11, Modi further discloses:
further comprising: the first circuit configured to receive a first instance of the first signal (Modi, Fig. 3, see input of “Carrier PA” connected to “Input splitter”); and the third circuit configured to receive a second instance of the first signal (Fig. 3, see input of “Peaking PA” connected to “Input splitter” via 90° phase offset); wherein the second instance of the first signal is offset from the first instance of the first signal by a predetermined amount (Fig. 3, see 90° phase offset between “Input splitter” and “Peaking PA”).
Regarding claim 12, Modi discloses:
A device (Modi, Fig. 3) in communication with a driver (Fig. 3, see elements after driver “K”), the device configured to receive a first signal from the driver (Fig. 3, see connection between “P-out-d” and “TPin”/”TGBias”), and the device comprising: a first circuit (Fig. 3, “Carrier PA”) configured to: provide, in response to receipt of the first signal (Fig. 3, see connection between “Pout-d” and “Carrier PA” at “Input Splitter”), a second signal that is an amplification of the first signal (Fig. 3, consider output of “Carrier PA”), the second signal having a first level based at least on a first level of the first signal (Fig. 3, consider output of “Carrier PA”); a second circuit (Fig. 3, “TGBias”) configured to: detect, in response to receipt of the first signal, the first level of the first signal (Page 2, Col. 1, lines 21-25); and provide, in response to detection of the first level of the first signal, a third signal to control a third circuit of the device (Fig. 3, consider signal “VgP” to control “Peaking PA, and Page 2, Col. 1, lines 17-20), wherein the third signal controls the third circuit by defining a voltage bias between a first terminal and a second terminal of the third circuit of the device (Fig. 3, consider voltage difference between terminal at input of “Peaking PA” and reference terminal of “Peaking PA”); the third circuit configured to: provide, in response to receipt of the first signal and the third signal, a fourth signal (Fig. 3, consider output of “Peaking PA”), the fourth signal having a first level in response to the voltage bias being smaller than a predetermined value (Fig. 4, consider peaking amplifier level with output power below ~46 dBm), and the fourth signal having a second level in response to the voltage bias being larger than the predetermined value (Fig. 4, consider peaking amplifier level with output power above ~46 dBm); and a fourth circuit (Fig. 3, see node combining signals from “Carrier PA” and “Peaking PA”) configured to: provide, in response to receipt of the second signal and the fourth signal, a fifth signal (Fig. 3, consider node at output resistor), the fifth signal having a first level based at least on the first level of the second signal (Fig. 4, consider output power as <46 dBm without peaking amplifier activated), and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal (Fig. 4, consider output power as >46 dBm with peaking amplifier activated).
Regarding claim 13, Modi further discloses:
wherein: the fifth signal has the first level in response to the fourth signal having the first level (Modi, Fig. 4, consider output power as <46 dBm without peaking amplifier activated); and the fifth signal has the second level in response to the fourth signal having the second level (Fig. 4, consider output power as >46 dBm with peaking amplifier activated).
Regarding claim 14, Modi further discloses:
wherein the second level of the fifth signal is larger than the second level of the fourth signal (Modi, Fig. 4, consider that less than 100% of the output power is provided by “Peaking PA” ), and wherein the second level of the fourth signal is larger than first level of the second signal (Fig. 4, consider portion of output signal contributed by “Peaking PA” above ~46 dBm, and portion of output signal contributed by “Carrier PA” below ~46 dBm).
Regarding claim 15, Modi further discloses:
wherein the first level of the second signal is larger than the first level of the fourth signal (Modi, Fig. 4, consider that all of the output power is provided by “Carrier PA” when the output power is below ~46 dBm), and wherein the first level of the second signal is smaller than the second level of the fourth signal (Fig. 4, consider portion of output signal contributed by “Peaking PA” above ~46 dBm, and portion of output signal contributed by “Carrier PA” below ~46 dBm).
Regarding claim 18, Modi discloses:
A method (Modi, Fig. 3) comprising: receiving, by a device (Fig. 3, see elements after “K”), from a driver (Fig. 3, see element “K”), a first signal (Fig. 3, “Pout-d”) to indicate a first amount of power and the first signal having a first level (Page 2, Col. 1, lines 21-25); providing, by a first circuit of the device (Fig. 3, “Carrier PA”), in response to receipt of the first signal (Fig. 3, see connection between “Pout-d” and “Carrier PA” at “Input Splitter”), a second signal that is an amplification of the first signal (Fig. 3, consider output of “Carrier PA”), the second signal having a first level based at least on the first level of the first signal (Fig. 3, consider output of “Carrier PA”); detecting, by a second circuit of the device (Fig. 3, “TGBias”), in response to receipt of the first signal, the first level of the first signal (Page 2, Col. 1, lines 21-25); providing, by the second circuit of the device, in response to detection of the first level of the first signal, a third signal to control a third circuit of the device (Fig. 3, consider signal “VgP” to control “Peaking PA, and Page 2, Col. 1, lines 17-20), wherein the third signal controls the third circuit by defining a voltage bias between a first terminal and a second terminal of the third circuit of the device (Fig. 3, consider voltage difference between terminal at input of “Peaking PA” and reference terminal of “Peaking PA”); providing, by the third circuit of the device, in response to receipt of the first signal and the third signal, a fourth signal (Fig. 3, consider output of “Peaking PA”), the fourth signal having a first level in response to the voltage bias being smaller than a predetermined value (Fig. 4, consider peaking amplifier level with output power below ~46 dBm), and the fourth signal having a second level in response to the voltage bias being larger than the predetermined value (Fig. 4, consider peaking amplifier level with output power above ~46 dBm); and providing, by a fourth circuit of the device (Fig. 3, see node combining signals from “Carrier PA” and “Peaking PA”), in response to receipt of the second signal and the fourth signal, a fifth signal (Fig. 3, consider node at output resistor), the fifth signal having a first level based at least on the first level of the second signal (Fig. 4, consider output power as <46 dBm without peaking amplifier activated), and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal (Fig. 4, consider output power as >46 dBm with peaking amplifier activated).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Modi as applied to claims 1 and 18, respectively, above, and further in view of Hayes et al. (Patent Publication Number US 2018/0175800 A1), as cited by applicant, hereafter referred to as Hayes.
Regarding claim 5, Modi fails to disclose:
wherein the first level of the first signal has a first value in response to the first amount of power pertaining to a first mode of the device, and wherein the first level of the first signal has a second value in response to the first amount of power pertaining to a second mode of the device.
However, Hayes teaches wherein the first level of the first signal has a first value in response to the first amount of power pertaining to a first mode of the device (Hayes, Paragraph 20, lines 16-25), and wherein the first level of the first signal has a second value in response to the first amount of power pertaining to a second mode of the device (Paragraph 20, lines 25-29).
Modi and Hayes are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art to have modified Modi to incorporate the teachings of Hayes to include the variable biasing system of Hayes in the circuit of Modi, which would have the effect of enabling usage over wide power conditions (Hayes, Paragraph 20, lines 3-7).
Regarding claim 6, Modi fails to disclose:
wherein the first mode of the device pertains to communication corresponding to a first protocol, and wherein the second mode of the device pertains to communication corresponding to a second protocol.
However, Hayes teaches wherein the first mode of the device pertains to communication corresponding to a first protocol (Hayes, Paragraph 20, lines 16-25), and wherein the second mode of the device pertains to communication corresponding to a second protocol (Paragraph 20, lines 25-29).
Modi and Hayes are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art to have modified Modi to incorporate the teachings of Hayes to include the variable biasing system of Hayes in the circuit of Modi, which would have the effect of enabling usage over wide power conditions (Hayes, Paragraph 20, lines 3-7).
Regarding claim 19, Modi fails to disclose:
wherein: the first level of the first signal has a first value in response to the first amount of power pertaining to a first mode of the device; the first level of the first signal has a second value in response to the first amount of power pertaining to a second mode of the device; the first mode of the device pertains to communication corresponding to a first protocol; and the second mode of the device pertains to communication corresponding to a second protocol.
However, Hayes teaches wherein: the first level of the first signal has a first value in response to the first amount of power pertaining to a first mode of the device (Hayes, Paragraph 20, lines 16-25); the first level of the first signal has a second value in response to the first amount of power pertaining to a second mode of the device (Paragraph 20, lines 25-29); the first mode of the device pertains to communication corresponding to a first protocol (Hayes, Paragraph 20, lines 16-25); and the second mode of the device pertains to communication corresponding to a second protocol (Paragraph 20, lines 25-29).
Modi and Hayes are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art to have modified Modi to incorporate the teachings of Hayes to include the variable biasing system of Hayes in the circuit of Modi, which would have the effect of enabling usage over wide power conditions (Hayes, Paragraph 20, lines 3-7).
Claims 7-10, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Modi as applied to claims 1, 12, and 18, respectively, above, and further in view of Cassou et al. (Patent Publication Number WO 2018/0197919 A1), as cited by applicant, hereafter referred to as Cassou.
Regarding claim 7, Modi fails to disclose:
further comprising: a fifth circuit configured to: receive, prior to the fourth circuit, the fourth signal; adjust, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value; and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit; wherein the second value of the first amount of resistance dictates the first level of the fifth signal; and wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance.
However, Cassou teaches further comprising: a fifth circuit (Cassou, Fig. 5, 350) configured to: receive, prior to the fourth circuit, the fourth signal (Fig. 5, see connection between combiner 155 and peaking amplifier 138 via impedance inverter 350); adjust, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value (Page 23, lines 17-21); and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit (Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350); wherein the second value of the first amount of resistance dictates the first level of the fifth signal (Page 23, lines 17-21); and wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance (Page 23, lines 19-21).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 8, Modi fails to disclose:
wherein the fifth circuit is configured to adjust the first amount of resistance by: modifying a second amount of resistance associated with the fourth signal from a first value to a second value; wherein the second value of the second amount of resistance is less than the second value of the first amount of resistance.
However, Cassou further teaches wherein the fifth circuit is configured to adjust the first amount of resistance (Cassou, Page 23, lines 15-21) by: modifying a second amount of resistance associated with the fourth signal from a first value to a second value (Page 23, lines 15-17); wherein the second value of the second amount of resistance is less than the second value of the first amount of resistance (Page 23, lines 15-17).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 9, Modi fails to disclose:
wherein the fifth circuit is positioned between the third circuit and the fourth circuit, and wherein the fifth circuit is located in series to the third circuit and the fourth circuit.
However, Cassou further teaches wherein the fifth circuit is positioned between the third circuit and the fourth circuit (Cassou, Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350), and wherein the fifth circuit is located in series to the third circuit and the fourth circuit (Fig. 5, see series connection between peaking amplifier 138 and combiner 155 via impedance inverter 350).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 10, Modi fails to disclose:
further comprising: a fifth circuit configured to: receive, prior to the fourth circuit, the fourth signal; adjust, in response to the fourth signal having the second level, a first amount of resistance experienced by the first circuit from a first value to a second value; and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit; and wherein the second value of the first amount of resistance is smaller than the first value of the first amount of resistance; wherein an amount of the fifth signal that is based on the first level of the second signal is reduced in response to the first amount of resistance having the second value.
However, Cassou teaches further comprising: a fifth circuit (Cassou, Fig. 5, 350) configured to: receive, prior to the fourth circuit, the fourth signal (Fig. 5, see connection between combiner 155 and peaking amplifier 138 via impedance inverter 350); adjust, in response to the fourth signal having the second level, a first amount of resistance experienced by the first circuit from a first value to a second value (Page 23, lines 14-17); and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit (Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350); and wherein the second value of the first amount of resistance is smaller than the first value of the first amount of resistance (Page 23, lines 14-17); wherein an amount of the fifth signal that is based on the first level of the second signal is reduced in response to the first amount of resistance having the second value (Page 23, lines 14-21).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 16, Modi fails to disclose:
further comprising: a fifth circuit configured to: receive, prior to the fourth circuit, the fourth signal; adjust, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value; and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit; and wherein the second value of the first amount of resistance dictates the first level of the fifth signal; wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance.
However, Cassou teaches further comprising: a fifth circuit (Cassou, Fig. 5, 350) configured to: receive, prior to the fourth circuit, the fourth signal (Fig. 5, see connection between combiner 155 and peaking amplifier 138 via impedance inverter 350); adjust, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value (Page 23, lines 17-21); and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit (Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350); and wherein the second value of the first amount of resistance dictates the first level of the fifth signal (Page 23, lines 17-21); wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance (Page 23, lines 19-21).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 17, Modi fails to disclose:
further comprising: a fifth circuit configured to: receive, prior to the fourth circuit, the fourth signal; adjust, in response to the fourth signal having the second level, a first amount of resistance experienced by the first circuit from a first value to a second value; and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit; and wherein the second value of the first amount of resistance is smaller than the first value of the first amount of resistance; wherein an amount of the fifth signal that is based on the first level of the second signal is reduced in response to the first amount of resistance having the second value.
However, Cassou teaches further comprising: a fifth circuit (Cassou, Fig. 5, 350) configured to: receive, prior to the fourth circuit, the fourth signal (Fig. 5, see connection between combiner 155 and peaking amplifier 138 via impedance inverter 350); adjust, in response to the fourth signal having the second level, a first amount of resistance experienced by the first circuit from a first value to a second value (Page 23, lines 14-17); and provide, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit (Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350); and wherein the second value of the first amount of resistance is smaller than the first value of the first amount of resistance (Page 23, lines 14-17); wherein an amount of the fifth signal that is based on the first level of the second signal is reduced in response to the first amount of resistance having the second value (Page 23, lines 14-21).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Regarding claim 20, Modi fails to disclose:
further comprising: receiving, by a fifth circuit of the device, prior to the fourth circuit, the fourth signal; adjusting, by the fifth circuit of the device, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value; providing, by the first circuit of the device, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit; and wherein the second value of the first amount of resistance dictates the first level of the fifth signal; wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance.
However, Cassou teaches further comprising: receiving, by a fifth circuit of the device (Cassou, Fig. 5, 350), prior to the fourth circuit, the fourth signal (Fig. 5, see connection between combiner 155 and peaking amplifier 138 via impedance inverter 350); adjusting, by the fifth circuit of the device, in response to the fourth signal having the first level, a first amount of resistance experienced by the first circuit from a first value to a second value (Page 23, lines 17-21); providing, by the first circuit of the device, in response to adjustment in the first amount of resistance, the fourth signal to the fourth circuit (Fig. 5, see connection between peaking amplifier 138 and combiner 155 via impedance inverter 350); and wherein the second value of the first amount of resistance dictates the first level of the fifth signal (Page 23, lines 17-21); wherein the second value of the first amount of resistance is larger than the first value of the first amount of resistance (Page 23, lines 19-21).
Modi and Cassou are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Modi to incorporate the teachings of Cassou to include the impedance inverter of Cassou in the circuit of Modi, which would have the effect of improving the signal bandwidth of the Doherty amplifier of Modi (Cassou, Page 24, lines 27-29).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. “A 24-to-30 GHz Series-Doherty Power Amplifier with Novel Broadband Combiner Achieving 2.5% Back-off PAE Variation in 65-nm CMOS” discloses (Fig. 5A) a differential Doherty amplifier with an impedance inverter.
Imai (Patent Publication Number US 2026/0019042 A1) discloses (Fig. 6) a differential Doherty amplifier.
Peng et al. (Patent Publication Number WO 2023/130843 A1) discloses (Fig. 5) a differential Doherty amplifier.
Tiskerling Dynamics LLC (Patent Publication Number WO 2014/151857 A1) discloses (Fig. 3) an amplifier system able to provide communications under either Bluetooth® or WLAN protocols.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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