DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-8, 11-12, & 16-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WO2024/257531A1 hereafter referred to as Nakamura.
In regards to claim 1, Nakamura discloses
An integrated passive device comprising: a first capacitor (10A – fig. 1; [0023]) including a conductive substrate (11 – fig. 1; [0023]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0023]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0023]) on the back side of the conductive substrate, a front conductive polymer layer (12A – fig. 1; [0025]) on the front dielectric layer, and a back conductive polymer layer (12A – fig. 1; [0025]) on the back dielectric layer;
a second capacitor (10B – fig. 1; [0023]) stacked on the first capacitor, the second capacitor including a conductive substrate (11 – fig. 1; [0023]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0023]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0023]) on the back side of the conductive substrate, a front conductive polymer layer (12A – fig. 1; [0025]) on the front dielectric layer, and a back conductive polymer layer (12A – fig. 1; [0025]) on the back dielectric layer;
a first metal contact (32 – fig. 1; [0037]) electrically connected to one or both of the conductive substrates of the first and second capacitors;
a second metal contact (31 – fig. 1; [0036]) electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers of the first and second capacitors; and
a passthrough electrical connection (42 and/or 62 or 41 and/or 61 – fig. 1; [0051], [0056-0057], & [0062]) between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface.
In regards to claim 2, Nakamura discloses
The integrated passive device of claim 1, wherein the first and second capacitors are bonded together by a conductive foil (12Bb – fig. 1; [0189-0191]).
In regards to claim 5, Nakamura discloses
The integrated passive device of claim 2, wherein the first metal contact is provided on the front outer surface of the integrated passive device and is electrically connected to the conductive substrate of the first capacitor by a path including a through via, and
the passthrough connection comprises the first metal contact and the through via (fig. 1).
In regards to claim 6, Nakamura discloses
The integrated passive device of claim 2, wherein the second metal contact is provided on the front outer surface of the integrated passive device and is electrically connected to the back conductive polymer layer of the first capacitor by way of the conductive foil, and
the passthrough connection comprises the second metal contact and the conductive foil (fig. 1).
In regards to claim 7, Nakamura discloses
The integrated passive device of claim 1, further comprising a first metallization layer (12Bb – fig. 1; [0189-0191]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, the first and second capacitors being bonded together by the first metallization layer.
In regards to claim 8, Nakamura discloses
The integrated passive device of claim 7, wherein the first capacitor further includes a front carbonaceous layer (12Ba – fig. 1; [0026]) on the front conductive polymer layer,
the second capacitor further includes a back carbonaceous layer (12Ba – fig. 1; [0026]) on the back conductive polymer layer, and
the first metallization layer is on the front carbonaceous layer of the first capacitor and on the back carbonaceous layer of the second capacitor (fig. 1).
In regards to claim 11, Nakamura discloses
The integrated passive device of claim 7, wherein each of the first and second capacitors further includes a sidewall dielectric layer (20 – fig. 1; [0022]) on a sidewall of the conductive substrate, the sidewall dielectric layer connecting the front and back dielectric layers (fig. 1).
In regards to claim 12, Nakamura discloses
The integrated passive device of claim 11, further comprising a termination pad (41 and/or 61 – fig. 1; [0051] & [0056]) that extends along the sidewall dielectric layers of the first and second capacitors, the second metal contact being electrically connected to the first metallization layer by way of the termination pad.
In regards to claim 16, Nakamura discloses
A method of manufacturing an integrated passive device, the method comprising:
providing a first capacitor (10A – fig. 1; [0023]) including a conductive substrate (11 – fig. 1; [0023]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0023]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0023]) on the back side of the conductive substrate, a front conductive polymer layer (12A – fig. 1; [0025]) on the front dielectric layer, and a back conductive polymer layer (12A – fig. 1; [0025]) on the back dielectric layer;
stacking a second capacitor (10B – fig. 1; [0023]) on the first capacitor, the second capacitor including a conductive substrate (11 – fig. 1; [0023]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0023]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0023]) on the back side of the conductive substrate, a front conductive polymer layer (12A – fig. 1; [0025]) on the front dielectric layer, and a back conductive polymer layer (12A – fig. 1; [0025]) on the back dielectric layer; and,
after said stacking, forming a first metal contact (32 – fig. 1; [0050]) electrically connected to one or both of the conductive substrates of the first and second capacitors, forming a second metal contact (31 – fig. 1; [0050]) electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers of the first and second capacitors, and forming a passthrough electrical connection (42 and/or 62 or 41 and/or 61 – fig. 1; [0051], [0056-0057], & [0062]) between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface.
In regards to claim 17, Nakamura discloses
The method of claim 16, wherein said stacking comprises bonding the first and second capacitors together by a conductive foil (12Bb – fig. 1; [0189-0191]) provided therebetween.
In regards to claim 18, Nakamura discloses
The method of claim 16, wherein said stacking comprises bonding the first and second capacitors together by a metallization layer (12Bb – fig. 1; [0189-0191]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact.
Claim(s) 1-10, 13-14, & 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takahashi et al. (US 2025/0125098).
In regards to claim 1, Takahashi ‘098 discloses
An integrated passive device comprising: a first capacitor (10 – fig. 1; [0053]) including a conductive substrate (11 – fig. 1; [0054]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0054]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0054]) on the back side of the conductive substrate, a front conductive polymer layer (12 – fig. 1; [0055]) on the front dielectric layer, and a back conductive polymer layer (12 – fig. 1; [0055]) on the back dielectric layer;
a second capacitor stacked on the first capacitor, the second capacitor (10 – fig. 1; [0053]) including a conductive substrate (11 – fig. 1; [0054]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0054]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0054]) on the back side of the conductive substrate, a front conductive polymer layer (12 – fig. 1; [0055]) on the front dielectric layer, and a back conductive polymer layer (12 – fig. 1; [0055]) on the back dielectric layer;
a first metal contact (40D – fig. 13 & 22; [0177] & [0254]) electrically connected to one or both of the conductive substrates of the first and second capacitors;
a second metal contact (40C – fig. 13 & 22; [0177] & [0254]) electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers of the first and second capacitors; and
a passthrough electrical connection between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface (seen in fig. 22).
In regards to claim 2, Takahashi ‘098 discloses
The integrated passive device of claim 1, wherein the first and second capacitors are bonded together by a conductive foil (40a & 40b – fig 1 & 22; [0053] & [0256-0257]).
In regards to claim 3, Takahashi ‘098 discloses
The integrated passive device of claim 2, wherein the first capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the conductive foil is arranged to bond the front metallization layer of the first capacitor to the back metallization layer of the second capacitor (fig. 22).
In regards to claim 4, Takahashi ‘098 discloses
The integrated passive device of claim 3, wherein the first capacitor further includes a front carbonaceous layer (carbon layer; [0144-0147]) on the front conductive polymer layer and a back carbonaceous layer (carbon layer; [0144-0147]) on the back conductive polymer layer,
the second capacitor further includes a front carbonaceous layer (carbon layer; [0144-0147]) on the front conductive polymer layer and a back carbonaceous layer (carbon layer; [0144-0147]) on the back conductive polymer layer, and,
in each of the first and second capacitors, the front metallization layer is on the front carbonaceous layer and the back metallization layer is on the back carbonaceous layer ([0144-0147]).
In regards to claim 5, Takahashi ‘098 discloses
The integrated passive device of claim 2, wherein the first metal contact is provided on the front outer surface of the integrated passive device and is electrically connected to the conductive substrate of the first capacitor by a path including a through via (20D – fig. 12 & 22; [0181]), and
the passthrough connection comprises the first metal contact and the through via (fig. 12 & 22).
In regards to claim 6, Takahashi ‘098 discloses
The integrated passive device of claim 2, wherein the second metal contact is provided on the front outer surface of the integrated passive device and is electrically connected to the back conductive polymer layer of the first capacitor by way of the conductive foil (40a; fig. 13 & 22), and
the passthrough connection comprises the second metal contact and the conductive foil (fig. 13 & 22).
In regards to claim 7, Takahashi ‘098 discloses
The integrated passive device of claim 1, further comprising a first metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, the first and second capacitors being bonded together by the first metallization layer (fig. 22; [0144-0147]).
In regards to claim 8, Takahashi ‘098 discloses
The integrated passive device of claim 7, wherein the first capacitor further includes a front carbonaceous layer (carbon layer; [0144-0147]) on the front conductive polymer layer,
the second capacitor further includes a back carbonaceous layer (carbon layer; [0144-0147]) on the back conductive polymer layer, and
the first metallization layer (copper layer; [0144-0147]) is on the front carbonaceous layer of the first capacitor and on the back carbonaceous layer of the second capacitor.
In regards to claim 9, Takahashi ‘098 discloses
The integrated passive device of claim 7, further comprising: a third capacitor carbon stacked underneath the first capacitor, the third capacitor (10 – fig. 1; [0053]) including a conductive substrate (11 – fig. 1; [0054]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0054]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0054]) on the back side of the conductive substrate, a front conductive polymer layer (12 – fig. 1; [0055]) on the front dielectric layer, and a back conductive polymer layer (12 – fig. 1; [0055]) on the back dielectric layer, the first metal contact being electrically connected to the conductive substrates of the first, second, and third capacitors, the second metal contact being electrically connected to the front and back conductive polymer layers of the first, second, and third capacitors (fig. 22; [0255-0257] – teaches stacking and connecting a plurality (thus including three) like capacitors); and
a second metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the front conductive polymer layer of the third capacitor and the second metal contact, the first and third capacitors being bonded together by the second metallization layer (fig. 22; [0255-0257]).
In regards to claim 10, Takahashi ‘098 discloses
The integrated passive device of claim 9, wherein the first capacitor further includes a front carbonaceous layer (carbon layer; [0144-0147]) on the front conductive polymer layer and a back carbonaceous layer (carbon layer; [0144-0147]) on the back conductive polymer layer,
the second capacitor further includes a back carbonaceous layer (carbon layer; [0144-0147]) on the back conductive polymer layer,
the third capacitor further includes a front carbonaceous layer (carbon layer; [0144-0147]) on the front conductive polymer layer,
the first metallization layer (copper layer; [0144-0147]) is on the front carbonaceous layer of the first capacitor and on the back carbonaceous layer of the second capacitor, and
the second metallization layer (copper layer; [0144-0147]) is on the back carbonaceous layer of the first capacitor and on the front carbonaceous layer of the third capacitor.
In regards to claim 13, Takahashi ‘098 discloses
The integrated passive device of claim 1, wherein the first capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the front metallization layer of the first capacitor is bonded to the back metallization layer of the second capacitor by a conductive paste ([0236] – the metal resin used to form 20C & 20D is a conductive paste used to bond and electrically connect the capacitors).
In regards to claim 14, Takahashi ‘098 discloses
The integrated passive device of claim 1, wherein the first capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (copper layer; [0144-0147]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the front metallization layer of the first capacitor and the back metallization layer of the second capacitor are bonded to opposing sides of a metal contact layer by a conductive paste ([0236] – the metal resin used to form 20C & 20D is a conductive paste used to bond and electrically connect the capacitors).
In regards to claim 19, Takahashi ‘098 discloses
A method of manufacturing an integrated passive device, the method comprising:
providing a first capacitor (10 – fig. 1; [0053]) including a conductive substrate (11 – fig. 1; [0054]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0054]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0054]) on the back side of the conductive substrate, a front conductive polymer layer (12 – fig. 1; [0055]) on the front dielectric layer, and a back conductive polymer layer (12 – fig. 1; [0055]) on the back dielectric layer;
establishing electrical connections (40a-40b – fig. 1; [ 0053]) from outside the first capacitor to the conductive substrate of the first capacitor and to the front and back conductive polymer layers of the first capacitor; and,
after said establishing the electrical connections, stacking a second capacitor on the first capacitor (fig. 22) to provide a passthrough electrical connection (fig. 12-13 & 22; [0236]) between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface, the second capacitor (10 – fig. 1; [0053]) including a conductive substrate (11 – fig. 1; [0054]) having a front side and a back side, a front dielectric layer (13 – fig. 1; [0054]) on the front side of the conductive substrate, a back dielectric layer (13 – fig. 1; [0054]) on the back side of the conductive substrate, a front conductive polymer layer (12 – fig. 1; [0055]) on the front dielectric layer, and a back conductive polymer layer (12 – fig. 1; [0055]) on the back dielectric layer.
In regards to claim 20, Takahashi ‘098 discloses
The method of claim 19, wherein said stacking comprises bonding the first and second capacitors together using a conductive paste or solder ([0236] – the metal resin used to form 20C & 20D is a conductive paste used to bond and electrically connect the capacitors).
Claim(s) 1-5, 7-10, 13-15, & 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2008108841A hereafter referred to as Akimoto.
In regards to claim 1, Akimoto discloses
An integrated passive device comprising: a first capacitor (fig. 8-11; [0034]) including a conductive substrate (2 – fig. 1; [0034]) having a front side and a back side, a front dielectric layer (3 – fig. 1; [0034]) on the front side of the conductive substrate, a back dielectric layer (3 – fig. 1; [0034]) on the back side of the conductive substrate, a front conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the front dielectric layer, and a back conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the back dielectric layer;
a second capacitor stacked on the first capacitor, the second capacitor (fig. 8-11; [0034]) including a conductive substrate (2 – fig. 1; [0034]) having a front side and a back side, a front dielectric layer (3 – fig. 1; [0034]) on the front side of the conductive substrate, a back dielectric layer (3 – fig. 1; [0034]) on the back side of the conductive substrate, a front conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the front dielectric layer, and a back conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the back dielectric layer;
a first metal contact (12a – fig. 8-11; [0030]) electrically connected to one or both of the conductive substrates of the first and second capacitors;
a second metal contact (12b – fig. 8-11; [0030]) electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers of the first and second capacitors; and
a passthrough electrical connection between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface (seen in fig. 11; [0037]).
In regards to claim 2, Akimoto discloses
The integrated passive device of claim 1, wherein the first and second capacitors are bonded together by a conductive foil (8a/8b/6 – fig. 10-11; [0026]).
In regards to claim 3, Akimoto discloses
The integrated passive device of claim 2, wherein the first capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the conductive foil is arranged to bond the front metallization layer of the first capacitor to the back metallization layer of the second capacitor (fig. 10-11).
In regards to claim 4, Akimoto discloses
The integrated passive device of claim 3, wherein the first capacitor further includes a front carbonaceous layer (graphite layer; [0026]) on the front conductive polymer layer and a back carbonaceous layer (graphite layer; [0026]) on the back conductive polymer layer,
the second capacitor further includes a front carbonaceous layer (graphite layer; [0026]) on the front conductive polymer layer and a back carbonaceous layer (graphite layer; [0026]) on the back conductive polymer layer, and,
in each of the first and second capacitors, the front metallization layer is on the front carbonaceous layer and the back metallization layer is on the back carbonaceous layer ([0026]).
In regards to claim 5, Akimoto discloses
The integrated passive device of claim 2, wherein the first metal contact is provided on the front outer surface of the integrated passive device and is electrically connected to the conductive substrate of the first capacitor by a path including a through via (16 – fig. 11; [0037]), and
the passthrough connection comprises the first metal contact and the through via (fig. 11).
In regards to claim 7, Akimoto discloses
The integrated passive device of claim 1, further comprising a first metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, the first and second capacitors being bonded together by the first metallization layer (fig. 10-11; [0037]).
In regards to claim 8, Akimoto discloses
The integrated passive device of claim 7, wherein the first capacitor further includes a front carbonaceous layer (graphite layer; [0026]) on the front conductive polymer layer,
the second capacitor further includes a back carbonaceous layer (graphite layer; [0026]) on the back conductive polymer layer, and
the first metallization layer (silver paste; [0026]) is on the front carbonaceous layer of the first capacitor and on the back carbonaceous layer of the second capacitor.
In regards to claim 9, Akimoto discloses
The integrated passive device of claim 7, further comprising: a third capacitor stacked underneath the first capacitor, the third capacitor (fig. 8-11; [0034]) including a conductive substrate (2 – fig. 1; [0034]) having a front side and a back side, a front dielectric layer (3 – fig. 1; [0034]) on the front side of the conductive substrate, a back dielectric layer (3 – fig. 1; [0034]) on the back side of the conductive substrate, a front conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the front dielectric layer, and a back conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the back dielectric layer, the first metal contact being electrically connected to the conductive substrates of the first, second, and third capacitors, the second metal contact being electrically connected to the front and back conductive polymer layers of the first, second, and third capacitors (fig. 10-11); and
a second metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact and to promote electrical conductivity between the front conductive polymer layer of the third capacitor and the second metal contact, the first and third capacitors being bonded together by the second metallization layer (fig. 10-11).
In regards to claim 10, Akimoto discloses
The integrated passive device of claim 9, wherein the first capacitor further includes a front carbonaceous layer (graphite layer; [0026]) on the front conductive polymer layer and a back carbonaceous layer (graphite layer; [0026]) on the back conductive polymer layer,
the second capacitor further includes a back carbonaceous layer (graphite layer; [0026]) on the back conductive polymer layer,
the third capacitor further includes a front carbonaceous layer (graphite layer; [0026]) on the front conductive polymer layer,
the first metallization layer (silver paste; [0026]) is on the front carbonaceous layer of the first capacitor and on the back carbonaceous layer of the second capacitor, and
the second metallization layer (silver paste; [0026]) is on the back carbonaceous layer of the first capacitor and on the front carbonaceous layer of the third capacitor.
In regards to claim 13, Akimoto discloses
The integrated passive device of claim 1, wherein the first capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the front metallization layer of the first capacitor is bonded to the back metallization layer of the second capacitor by a conductive paste (15 – fig. 10; [0036]).
In regards to claim 14, Akimoto discloses
The integrated passive device of claim 1, wherein the first capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact, and
the front metallization layer of the first capacitor and the back metallization layer of the second capacitor are bonded to opposing sides of a metal contact layer by a conductive paste (15 – fig. 10; [0036]).
In regards to claim 15, Akimoto discloses
The integrated passive device of claim 1, wherein the first capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the first capacitor and the second metal contact,
the first capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the first capacitor and the second metal contact,
the second capacitor further includes a front metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the front conductive polymer layer of the second capacitor and the second metal contact,
the second capacitor further includes a back metallization layer (silver paste; [0026]) arranged to promote electrical conductivity between the back conductive polymer layer of the second capacitor and the second metal contact,
the front metallization layer of the first capacitor is bonded to a first metal contact layer (12b – fig. 10-11; [0036-0037]) by a conductive paste (6 – fig. 10-11; [0026]),
the back metallization layer of the second capacitor is bonded to a second metal contact layer (12b – fig. 10-11; [0036-0037]) by a conductive paste (6 – fig. 10-11; [0026]),
and the first and second metal contact layers are bonded together by solder (15 – fig. 10; [0036] & [0034]).
In regards to claim 19, Akimoto discloses
A method of manufacturing an integrated passive device, the method comprising:
providing a first capacitor (fig. 8-11; [0034]) including a conductive substrate (2 – fig. 1; [0034]) having a front side and a back side, a front dielectric layer (3 – fig. 1; [0034]) on the front side of the conductive substrate, a back dielectric layer (3 – fig. 1; [0034]) on the back side of the conductive substrate, a front conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the front dielectric layer, and a back conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the back dielectric layer;
establishing electrical connections (12a & 12 – fig. 10-11; [0036-0037]) from outside the first capacitor to the conductive substrate of the first capacitor and to the front and back conductive polymer layers of the first capacitor; and,
after said establishing the electrical connections, stacking a second capacitor on the first capacitor (fig. 10-11) to provide a passthrough electrical connection (fig. 11; [0037]) between a front outer surface of the integrated passive device and a back outer surface of the integrated passive device opposite the front outer surface, the second capacitor (fig. 8-11; [0034]) including a conductive substrate (2 – fig. 1; [0034]) having a front side and a back side, a front dielectric layer (3 – fig. 1; [0034]) on the front side of the conductive substrate, a back dielectric layer (3 – fig. 1; [0034]) on the back side of the conductive substrate, a front conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the front dielectric layer, and a back conductive polymer layer (4 – fig. 1; [0034] & [0013]) on the back dielectric layer.
In regards to claim 20, Akimoto discloses
The method of claim 19, wherein said stacking comprises bonding the first and second capacitors together using a conductive paste or solder (15 – fig. 10; [0036]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
WO2024/019144A1 – fig. 22 US 2025/0079090 – fig. 1
US 2025/0087427 – fig. 1 US 2025/0037940 – fig. 1
US 2024/0242892 – fig. 1 US 2025/0149261 – fig. 2
US 2024/0128028 – fig. 3 US 2025/0166927 – fig. 1
US 7,821,795 – fig. 2 JP2007251101A – fig. 7
US 2009/0120014 – fig. 2
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2848